JP2008152178A - Data line driving circuit, scanning line driving circuit, display device, electronic apparatus, data line driving method, scanning line driving method, and computer program - Google Patents

Abstract

In a conventional method in which drivers are arranged on the left and right sides of a scanning line, rising and falling characteristics can be improved, while cost and power consumption increase.
In a data line driving circuit of an active matrix driving type display device, a data line applied potential at the start point and end point of each horizontal scanning period is positioned on the on potential side of a switch element from a black level potential of a signal voltage. Equipped with a function to reset to an arbitrary reference voltage value. At this time, the scanning line driver circuit is equipped with a function of controlling the ON period of the switch element within a period in which the potential of the data line is maintained at the signal potential.
[Selection] Figure 5

Description

  The invention described in this specification relates to a driving technique of an active matrix driving type display device. Note that the invention herein has aspects as a data line driving circuit, a scanning line driving circuit, a display device, an electronic device, a data line driving method, a scanning line driving method, and a computer program.

  The trend toward larger screens and higher definition of flat panel display devices is increasing. Along with this, signal delay with respect to the driving frequency of the panel display element and deterioration of the rising / falling characteristics (frequency characteristics) of the driving signal have become problems.

FIG. 1 shows rising and falling characteristics of the write signal WS used in the active matrix drive type display device.
Note that FIG. 1A shows a waveform of a signal potential applied to the data line. FIG. 1B shows an example of a signal waveform of the write signal WS applied to a pixel located near the scanning line driver among the pixels connected to the i-th scanning line.

  FIG. 1C shows an example of a signal waveform of the write signal WS applied to a pixel far from the scan line driver in the pixel circuit connected to the i-th scan line. FIG. 1D shows an example of a signal waveform of the write signal WS applied to a pixel located near the scanning line driver among the pixels connected to the (i + 1) th scanning line.

  FIG. 1E shows an example of a signal waveform of the write signal WS applied to a pixel far from the scanning line driver among the pixels connected to the (i + 1) th scanning line. FIG. 1F shows an example of a signal waveform of the horizontal synchronization signal HS.

  The writing of the signal voltage value to each pixel is executed after the writing signal WS rises to the H level. However, as indicated by a broken line in FIG. 1, the waveform of the write signal WS becomes dull as the distance to the scanning line driver increases. That is, a phase difference occurs at the rising edge of the write signal WS at the H level even between pixels located on the same scanning line.

The occurrence of this phase difference is considered to be caused by a difference in wiring capacitance accompanying a difference in wiring length and an increase in inter-gate drain capacitance Cgd of the switch element accompanying an increase in driving frequency.
Therefore, a method of driving the drive line from both sides has been proposed for the purpose of improving the rise / fall characteristics with respect to the drive frequency.
JP 2005-345910 A

  However, the double-sided drive has a positive aspect that can improve the rising and falling characteristics, but has a negative aspect that increases manufacturing cost and power consumption. In addition, there is a downside that the power consumption tends to increase as the drive frequency increases. Accordingly, there is a need for a proposal of a technology that is excellent in balance between improvement of various characteristics and cost.

  Therefore, the inventor, as a data line driving circuit used in an active matrix drive type display device, determines the data line applied potential at the start and end points of each horizontal scanning period from the black level potential of the signal voltage to the ON potential of the switch element. A device having a function of resetting to an arbitrary reference voltage value located on the side is proposed.

  Further, the inventor, as a scanning line driving circuit for driving an active matrix driving type display device, the data line applied potential at the start point and end point of each horizontal scanning period is higher than the black level potential of the signal voltage. In the case of resetting to an arbitrary reference voltage value located on the side, a switch element having a function of controlling the ON period of the switch element to be shorter than the period in which the potential of the data line is maintained at the signal potential is proposed.

  In the case of the invention proposed by the inventor, the potential of the signal voltage is controlled to the reference voltage value (the potential on the on potential side of the switch element from the black level of the signal voltage) before the on potential is applied to the switch element. This control can reduce the parasitic capacitance of the switch element as viewed from the scanning line. Thus, it is possible to improve the rising / falling characteristics and phase delay of the switch element without increasing the power consumption.

An example of driving control of data lines and scanning lines suitable for an active matrix driving type organic EL display device will be described below.
In addition, the well-known or well-known technique of the said technical field is applied to the part which is not illustrated or described in particular in this specification.
Moreover, the form example demonstrated below is one form example of invention, Comprising: It is not limited to these.

(A) Overall Configuration of Organic EL Display Device FIG. 2 shows the main components of the organic EL display device 1. The organic EL display device 1 includes an organic EL panel 3, a data line driver 5, and a scanning line driver 7 as main components. The organic EL display device 1 also includes a timing generator and the like necessary for generating a timing signal.

  The organic EL panel 3 is a self-luminous display device in which pixels 11 are arranged in a matrix on a base. In the case of this embodiment, the organic EL panel 3 is for color display, and the pixels 11 are arranged for each emission color. However, when the pixel 11 is an organic EL element having a structure in which a plurality of light emitting layers are stacked, one pixel 11 corresponds to a plurality of light emitting colors.

FIG. 3 shows a connection relationship between the pixel 11 formed at the intersection of the data line DL and the scanning line WL and the driving circuit.
The pixel 11 includes a switch element T1, a capacitor C, a current drive element T2, and an organic EL element D.

  The switch element T1 is a transistor that controls writing of the signal voltage applied to the data line DL to the capacitor C. The write signal WS is supplied from the scanning line driver 7 to each switch element T1 through the scanning line WL.

  The capacitor C is a storage element that holds the written signal voltage for one frame. By using the capacitor C, even when the signal voltage is written line-sequentially, a light emission mode similar to that in the case of writing by the frame sequential scanning method is realized.

  The current drive element T2 is a transistor that supplies a drive current corresponding to the signal voltage held in the capacitor C to the organic EL element D. The drive current value here is determined by the voltage Vgs applied between the gate and source of the current drive element T2.

  The data line driver 5 is a circuit device that drives the data line DL of the organic EL panel 3. FIG. 4 shows an internal configuration example of the data line driver 5. The data line driver 5 includes a digital / analog converter 21 that converts a video signal value (digital value) Din corresponding to each pixel into a signal voltage value Vin, and a reference signal value (digital value) Dref for reset as a reference voltage value. It comprises a digital / analog converter 23 for converting to Vref and a switch circuit 25.

In the case of this embodiment, the reference voltage value Vref is the white level voltage value Vw having the highest potential in the variable voltage range of the signal voltage value Vin.
The switch circuit 25 is a circuit device that outputs a signal voltage value Vin or a reference voltage value Vref to the data line DL based on a switching control signal given from a timing generator (not shown).

  The switch circuit 25 performs a switching operation so that the potential of the data line DL is reset to the reference voltage value Vref at least at the start point and end point of the horizontal scanning period. Specifically, the switching operation to the reference voltage value Vref is executed at a time point set in consideration of the potential transition time.

  FIG. 5A shows a change in the potential VD applied to the data line DL. As shown in FIG. 5A, the potential VD at the start and end points of the horizontal scanning period is always reset to the white level potential (= Vref) of the video signal value. Note that the potential in other signal periods changes according to the response characteristics of the pixel 11. Incidentally, FIG. 5F shows a horizontal synchronizing signal HS that defines a horizontal scanning period.

  The scanning line driver 7 is a circuit device that provides the write timing of the signal voltage value Vin. The scanning line driver 7 selectively controls one scanning line to a writable state every time the horizontal synchronization signal HS is input. In the case of this embodiment, the scanning line driver 7 applies the ON potential to the switch element T1 for a period T1 shorter than the horizontal scanning period T0.

Note that the application timing of the ON potential is supplied by a timing generator (not shown).
FIG. 5B to FIG. 5E show signal waveform examples of the write signal WS. FIG. 5B shows writing applied to a pixel 11 (a pixel located on the right side in FIG. 2) located near the scanning line driver 7 among the pixels 11 connected to the i-th scanning line WL. An example of a signal waveform of the signal WS is shown.

  FIG. 5C is applied to the pixel 11 far from the scanning line driver 7 among the pixels 11 connected to the i-th scanning line WL (in the case of FIG. 2, the pixel located on the left side). An example of a signal waveform of the write signal WS is shown. FIG. 5D shows a signal waveform example of the write signal WS applied to the pixel 11 located near the scanning line driver 7 among the pixels 11 connected to the (i + 1) th scanning line WL.

FIG. 5E shows a signal waveform example of the write signal WS applied to the pixel 11 located far from the scanning line driver 7 among the pixels 11 connected to the (i + 1) th scanning line WL.
As shown in FIGS. 5B and 5D, it can be seen that the period T1 in which the write signal WS is at the ON potential is shorter than the horizontal scanning period T0.

  Of course, the writing time of each pixel located near the scanning line driver 7 is shorter than that of the conventional example (FIG. 1). However, as shown in FIGS. 5C and 5E, the writing time of each pixel at a position far from the scanning line driver 7 can be ensured to be equal to or longer than that in the conventional example (FIG. 1).

  This is because the rise / fall characteristics with respect to the drive frequency are improved. That is, the response of the switching element T1 is improved by the driving method proposed in this embodiment. The principle of improving the response characteristic is based on the following phenomenon.

  If a white level signal voltage value Vw (= Vref) is already applied to the data line DL before the write signal WS (H level) is applied to the scanning line WL, the data line DL side of the switch element T1 is always drained. It becomes. Therefore, from the scanning line WL, as shown in FIG. 6, only the parasitic capacitance Cgs on the capacitor C side of the switch element T1 is visible.

  That is, the capacitance Cgd parasitic on the data line DL side of the switch element T1 becomes substantially zero or negligible compared to the capacitance Cgs on the capacitor C side. For this reason, the time constant τ viewed from the scanning line WL can be reduced.

  As a result, the responsiveness of the switch element T1 when the write signal WS is raised or lowered is improved. That is, even if the resolution and driving frequency of the organic EL panel 3 are increased, a sufficient writing time can be ensured without increasing the number of special wiring patterns and driving circuits. As a result, the image quality is improved.

  In addition, the writing phase difference between pixels can be reduced regardless of the pixel position on the scanning line WL. Therefore, in the case of the organic EL display device 1 that does not have a large capacitive element other than the capacitor C, the writing time of the signal voltage value Vin is actively shortened, and the power consumed when writing the signal voltage value Vin can be reduced. it can.

(B) Other Implementation Examples (B-1) Other Reference Voltage Examples In the foregoing embodiment, the case where the reference voltage value Vref is set to the white level voltage value Vw of the signal voltage value Vin has been described.
However, the reference voltage value Vref can be set to a voltage value according to the driving conditions of the organic EL display device 1.

FIG. 7 shows an example of a voltage relationship assumed between the variable range of the signal voltage value Vin and the variable range of the write signal WS. These voltage relationships are selectively used depending on the applied system.
FIG. 7A shows that the on voltage (H level) of the write signal WS is smaller than the H level (white level) of the signal voltage value Vin, and the off voltage (L level) of the write signal WS is L level of the signal voltage value Vin. A relationship smaller than (black level) is shown.

  FIG. 7B shows that the on voltage (H level) of the write signal WS is larger than the H level (white level) of the signal voltage value Vin, and the off voltage (L level) of the write signal WS is L level of the signal voltage value Vin. A relationship smaller than (black level) is shown.

FIG. 7C shows that the on voltage (H level) of the write signal WS is larger than the H level (white level) of the signal voltage value Vin, and the off voltage (L level) of the write signal WS is L level of the signal voltage value Vin. A relationship greater than (black level) is shown.
However, in any case, the reference voltage value Vref is set to a value larger than the black level potential of the signal voltage value Vin (a value from the ON potential of the switch element T1).

  When the switch element T1 is an N-channel FET, the setting condition of the reference voltage value Vref is four minutes of the time constant τ when the signal voltage value Vin is raised from the L level to the H level as shown in FIG. It is desirable that the voltage be equal to or higher than the voltage corresponding to one time point.

FIG. 9A shows a case where the reference voltage value Vref is set to a substantially intermediate potential of the signal voltage value Vin. 9B to 9F correspond to FIGS. 5B to 5F. In this case, the waveform of the signal voltage value Vin always changes with the intermediate potential as a base point. Since the voltage applied to the capacitor C can be instantaneously reduced, it is effective in improving the rise / fall characteristics.
Further, the reference voltage value Vref may be set to be equal to or higher than the ON potential of the switch element T1.

  In addition, the reference voltage value Vref may be set to a value equal to or higher than the white level of the signal voltage value Vin as shown in FIG. 10B to 10F correspond to FIGS. 5B to 5F.

In this case, the data line DL side of the switch element T1 always operates as a drain, and the drain-source voltage Vds of the switch element T1 can be increased.
That is, the switch element T1 can be driven in the saturation region. Therefore, the responsiveness of the switch element T1 can be controlled to be higher.

(B-2) Other Pixel Structure In the above-described embodiment, the case where both the switch element T1 and the current drive element T2 are configured by N-channel FETs has been described.
However, this combination is not necessarily required depending on the manufacturing process.

  For example, the switch element T1 and the switch element T1 may be configured by an N-channel FET, and the current drive element T2 may be configured by a P-channel FET. Further, for example, the switch element T1 may be configured by a P-channel FET, and the current drive element T2 may be configured by an N-channel FET.

  Further, for example, as shown in FIG. 11, both the switch element T1 and the current drive element T2 may be configured by P-channel FETs. In FIG. 11, the same reference numerals are given to the portions corresponding to those in FIG. 3.

  In the case of this circuit configuration, for example, the relationship shown in FIG. 12 is assumed between the variable range of the signal voltage value Vin and the variable range of the write signal WS. FIG. 12A shows that the on voltage (L level) of the write signal WS is smaller than the L level (white level) of the signal voltage value Vin, and the off voltage (H level) of the write signal WS is H level of the signal voltage value Vin. A relationship smaller than (black level) is shown.

  In FIG. 12B, the on voltage (L level) of the write signal WS is smaller than the L level (white level) of the signal voltage value Vin, and the off voltage (H level) of the write signal WS is H level of the signal voltage value Vin. A relationship greater than (black level) is shown.

  FIG. 12C shows that the on voltage (L level) of the write signal WS is larger than the L level (white level) of the signal voltage value Vin, and the off voltage (H level) of the write signal WS is H level of the signal voltage value Vin. A relationship greater than (black level) is shown.

However, in any case, the reference voltage value Vref is preferably set to a value lower than the black level potential of the signal voltage value Vin (a value on the on potential side of the switch element T1).
Incidentally, when the switching element T1 is realized by a P-channel FET, the setting condition of the reference voltage value Vref corresponds to a time point of a quarter of the time constant τ when the signal voltage value Vin falls from the H level to the L level. It is desirable that the voltage is lower than the voltage.

  FIG. 13 shows a driving example suitable for the case where both the switch element T1 and the current drive element T2 are P-channel FETs. FIG. 13A shows an example of a signal waveform of the potential VD applied to the data line DL when the reference voltage value Vref is set to the white level of the signal voltage value Vin. 13B to 13E show examples of the waveform of the write signal WS, and FIG. 13F shows the horizontal synchronization signal HS.

Similarly, FIG. 14A shows an example of the signal waveform of the potential VD applied to the data line DL when the reference voltage value Vref is set to a substantially intermediate potential of the signal voltage value Vin. 14B to 14F show examples of the waveform of the write signal WS, and FIG. 14F shows the horizontal synchronization signal HS.
Incidentally, the reference voltage value Vref may be set to be equal to or lower than the ON potential of the switch element T1.

  In addition, the reference voltage value Vref may be set to be equal to or lower than the white level of the signal voltage value Vin as shown in FIG. 15B to 15F show examples of the waveform of the write signal WS, and FIG. 15F shows the horizontal synchronization signal HS.

(B-3) Product example (a) Drive IC
The organic EL panel 3, the data line driver 5, and the scanning line driver 7 constituting the organic EL display device 1 can all be formed on one panel, but the driver and the pixel matrix are separately manufactured and distributed. You can also

For example, the data line driver 5 and the scanning line driver 7 are independent drive ICs (integrated
circuit) and can be distributed independently from the organic EL panel 3.

(B) Display module The organic EL display device 1 in the embodiment described above can also be distributed in the form of a display module which is an intermediate product.

  FIG. 16 shows an appearance example of the display module 31. The display module 31 has a structure in which a facing portion 33 is bonded to the surface of the support substrate 35. The facing portion 33 is made of glass or other transparent member as a base material, and a color filter, a protective film, a light shielding film, and the like are arranged on the surface thereof.

  The display module 31 may be provided with an FPC (flexible printed circuit) 37 and the like for inputting and outputting signals and the like to the support substrate 35 from the outside.

(C) Electronic device The organic EL display device 1 in the embodiment described above is also distributed in a product form mounted on an electronic device.
FIG. 17 illustrates a conceptual configuration example of the electronic device 41. The electronic device 41 includes the organic EL display device 1 and the system control unit 43 described above. The processing content executed by the system control unit 43 varies depending on the product form of the electronic device 41.

Note that the electronic device 41 is not limited to a device in a specific field as long as it has a function of displaying an image or video generated in the device or input from the outside.
As this type of electronic device 41, for example, a television receiver is assumed. FIG. 18 shows an example of the appearance of the television receiver 51.

  A display screen 57 composed of a front panel 53, a filter glass 55, and the like is arranged on the front surface of the television receiver 51. The portion of the display screen 57 corresponds to the organic EL display device 1 described in the embodiment.

  Further, for example, a digital camera is assumed as this type of electronic device 41. FIG. 19 shows an example of the external appearance of the digital camera 61. FIG. 19A shows an example of the appearance on the front side (subject side), and FIG. 19B shows an example of the appearance on the back side (photographer side).

  The digital camera 61 includes an imaging lens (FIG. 19 shows the state in which the protective cover 63 is closed, and is therefore arranged on the back side of the protective cover 63), a flash light emitting unit 65, a display screen 67, a control switch 69, and a shutter. It consists of buttons 71. Among these, the part of the display screen 67 corresponds to the organic EL display device 1 described in the embodiment.

For example, a video camera is assumed as this type of electronic device 41. FIG. 20 shows an example of the appearance of the video camera 81.
The video camera 81 includes an imaging lens 85 that images a subject in front of a main body 83, a shooting start / stop switch 87, and a display screen 89. Among these, the display screen 89 corresponds to the organic EL display device 1 described in the embodiment.

  Further, for example, a portable terminal device is assumed as this type of electronic device 41. FIG. 21 shows an appearance example of a mobile phone 91 as a mobile terminal device. A cellular phone 91 illustrated in FIG. 21 is a foldable type, and FIG. 21A illustrates an appearance example in a state where the housing is opened, and FIG. 21B illustrates an appearance example in a state where the housing is folded.

  The mobile phone 91 includes an upper housing 93, a lower housing 95, a connecting portion (in this example, a hinge portion) 97, a display screen 99, an auxiliary display screen 101, a picture light 103, and an imaging lens 105. Among these, the display screen 99 and the auxiliary display screen 101 correspond to the organic EL display device 1 described in the embodiment.

Further, for example, a computer is assumed as this type of electronic device 41. FIG. 22 shows an example of the appearance of the notebook computer 111.
The notebook computer 111 includes a lower casing 113, an upper casing 115, a keyboard 117, and a display screen 119. Among these, the display screen 119 corresponds to the organic EL display device 1 described in the embodiment.

  In addition to these, the electronic device 41 may be an audio playback device, a game machine, an electronic book, an electronic dictionary, or the like.

(B-4) Other Display Device Examples In the description of the embodiments, the case where the display device is the organic EL display device 1 has been described.
However, the data line driver 5 and the scanning line driver 7 can be applied to other self-luminous display devices. For example, the present invention can be applied to an inorganic EL display device, a display device in which LEDs are arranged, an FED display device, a PDP display device, and the like.

The data line driver 5 and the scanning line driver 7 can also be applied to non-self light emitting display devices such as liquid crystal display devices.
FIG. 23 shows a connection relationship between the pixel 121 formed at the intersection of the data line DL and the scanning line WL and the driver circuit.

  As shown in FIG. 23, the equivalent circuit of the pixel 121 can be expressed as a switch element T1 and a capacitor C1. The capacitor C1 corresponds to the liquid crystal sandwiched between the pixel electrode and the counter electrode. Even when the driving method proposed by the inventor is applied to a liquid crystal display device, a long writing time can be secured stably. Therefore, the image quality can be improved without increasing the cost.

(B-5) Control Device Configuration In the above description, the case of controlling the switching timing to the reference voltage value Vref by the data line driver 5 and the timing to switch to the off voltage by the scanning line driver 7 are described in hardware. did.
However, these control timings may be controlled through software processing.

(B-6) Others Various modifications can be considered for the above-described embodiments within the scope of the invention. Various modifications and applications created or combined based on the description of the present specification are also conceivable.

It is a figure which shows the example of a conventional drive. It is a figure which shows the structural example of a display device. It is a figure which shows the structural example of a pixel. It is a figure which shows the structural example of a data line driver. It is a figure which shows the example of a drive of a display device. It is a figure explaining how the capacity | capacitance looks by driving. It is a figure which illustrates the assumed voltage relationship. It is a figure which shows the example of a setting of a reference voltage value. It is a figure which shows the other example of a drive of a display device. It is a figure which shows the other example of a drive of a display device. It is a figure which shows the other structural example of a pixel. It is a figure which illustrates other voltage relationships assumed. It is a figure which shows the other example of a drive of a display device. It is a figure which shows the other example of a drive of a display device. It is a figure which shows the other example of a drive of a display device. It is a figure which shows the structural example of a display module. It is a figure which shows the function structural example of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the pixel structure of a liquid crystal display device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Organic EL display device 3 Organic EL panel 5 Data line driver 7 Scan line driver 41 Electronic equipment

Claims (18)

In a data line driving circuit used for an active matrix driving type display device,
A data line driving circuit characterized in that the data line applied potential at the start point and end point of each horizontal scanning period is reset to an arbitrary reference voltage value positioned on the switch element on potential side from the black level potential of the signal voltage . The data line driving circuit according to claim 1,
When the switch element is an N-channel type, the reference voltage value is set to be equal to or higher than the ON potential of the switch element. The data line driving circuit according to claim 1,
When the switch element is a P-channel type, the reference voltage value is set to be equal to or lower than the ON potential of the switch element. The data line driving circuit according to claim 1,
When the switch element is an N-channel type, the reference voltage value is set to be equal to or higher than the white level of the signal voltage. The data line driving circuit according to claim 1,
When the switching element is a P-channel type, the reference voltage value is set to be equal to or lower than the white level of the signal voltage. The data line driving circuit according to claim 1,
When the switch element is an N-channel type, the reference voltage value is set to be equal to or higher than a voltage value corresponding to a time point ¼ of the time constant τ when the signal voltage value rises from the L level to the H level. A data line driving circuit. The data line driving circuit according to claim 1,
When the switch element is a P-channel type, the reference voltage value is set to be equal to or less than a voltage value corresponding to a time point ¼ of the time constant τ when the signal voltage value falls from the H level to the L level. A characteristic data line driving circuit. In a scanning line driving circuit for driving an active matrix driving type display device,
When the data line applied potential at the start point and end point of each horizontal scanning period is reset to an arbitrary reference voltage value positioned on the switch element on potential side from the black level potential of the signal voltage, the switch element on period The scan line driver circuit is controlled within a period in which the potential of the data line is maintained at the signal potential. A display device having a pixel structure corresponding to an active matrix driving method;
A data line driving circuit for resetting the data line applied potential at the start point and end point of each horizontal scanning period to an arbitrary reference voltage value located on the ON potential side of the switch element from the black level potential of the signal voltage;
And a scanning line driving circuit for controlling an ON period of the switch element. The display device according to claim 9, wherein
The scanning line driver circuit controls the ON period of the switch element to be shorter than the period in which the potential of the data line is maintained at the signal potential. The display device according to claim 9, wherein
The display device is a non-self-luminous display device. The display device according to claim 9, wherein
The display device is a self-luminous display device. The display device according to claim 9, wherein
The display device is an electroluminescence type display device. A display device having a structure corresponding to the active matrix driving method;
A data line driving circuit for resetting the data line applied potential at the start point and end point of each horizontal scanning period to an arbitrary reference voltage value located on the ON potential side of the switch element from the black level potential of the signal voltage;
A scanning line driving circuit for controlling the ON period of the switch element;
An electronic device comprising: a signal processing unit. A data line driving method for an active matrix driving display device,
A data line driving method characterized in that the data line applied potential at the start point and end point of each horizontal scanning period is reset to an arbitrary reference voltage value located on the on potential side of the switch element from the black level potential of the signal voltage . A scanning line driving method of an active matrix driving display device,
When the data line applied potential at the start point and end point of each horizontal scanning period is reset to an arbitrary reference voltage value positioned on the switch element on potential side from the black level potential of the signal voltage, the switch element on period Is controlled to be shorter than a period in which the potential of the data line is maintained at the signal potential. In a computer that controls the drive timing of data lines in an active matrix drive type display device,
A process of resetting the data line applied potential at the start point and end point of each horizontal scanning period to an arbitrary reference voltage value positioned on the switch element on potential side with respect to the black level potential of the signal voltage. Computer program. Active matrix drive when the data line applied potential at the start point and end point of each horizontal scanning period is reset to an arbitrary reference voltage value positioned on the switch element on potential side from the black level potential of the signal voltage A computer for controlling the drive timing of scanning lines in a display device,
A computer program for controlling an ON period of a switch element to be shorter than a period in which a potential of a data line is maintained at a signal potential.

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