JP2008147480A - Semiconductor integrated circuit and design method thereof - Google Patents

Abstract

The degree of freedom of logic change is increased.
In a semiconductor integrated circuit design method for generating a semiconductor integrated circuit by arranging and wiring a plurality of types of functional cells in a predetermined region based on circuit connection information, a plurality of logics can be realized by changing the wiring. Prepare one or more types of auxiliary cells composed of more than one stage, and after placing and wiring multiple types of functional cells based on circuit connection information, place one or more arbitrary auxiliary cells that can be placed in unused areas of a given area However, if there is a change in the circuit connection information, the auxiliary cell arranged in the unused area is used.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor integrated circuit design method and a semiconductor integrated circuit designed by such a semiconductor integrated circuit design method.

  In response to the recent demands for smaller products and lower power consumption, the design of semiconductor integrated circuits is accompanied by miniaturization technology and high integration technology. Can be realized in a plurality of macro cells, and as shown in FIG. 5, it is common to realize an IC in which these macro cells are integrated into one chip.

  In the embedded array method, which is one of the methods, the system design is first performed, and after determining the number of gates of the logic part and the macro cells (RAM, ROM, PLL, etc.) to be mounted, Basic cells such as basic cells of a gate array are regularly arranged to form a base portion called a base bulk. Thereafter, the base bulk composed of the necessary macro cells and basic cells is manufactured before the wiring process. In parallel with this manufacturing operation, the circuit design of the logic part to the wiring process to post-simulation are performed in the same manner as the gate array, and after completing the design work, the wiring process is manufactured to complete the chip. As described above, in the embedded array system, the development period can be shortened by performing a part of the manufacturing process and the design work at the same time.

  As an advantage of the embedded array method, the degree of freedom for logic correction is further increased. When logic correction is required in the post-simulation process, change to another functional cell configured with the same base bulk on the basic cell array for configuring the logic unit, and connection information and wiring associated therewith Thus, it is possible to change the function by correcting only the wiring process without recreating the base portion.

  Even if logic correction is necessary after the operation evaluation after the sample is created, if the predetermined problem can be solved by changing the logic part, the base part is the same as the logic correction in the post-simulation process described above. Since the logic can be changed without changing the circuit, it is possible to cope with the problem by simply re-wiring the wiring process, and the development period can be shortened and the development cost can be reduced.

  On the other hand, the standard cell method is a method in which functional cells prepared in advance on a blank wafer are placed and wired. Since each functional cell has a unique bulk structure, it is more expensive than an embedded array method or a gate array. It is characterized in that it is easy to obtain effects such as integration, high speed, and low power consumption. However, since the standard cell method is made from the diffusion layer of the wafer, it is necessary to change not only the wiring process but also the base part as the logic is corrected. Become.

  Therefore, after initial placement of necessary function cells based on predetermined circuit connection information, some function cells are placed in unused areas not related to the original circuit connection information, and logic correction is required. In such a case, there is a technique for performing logic correction using the functional cells in these empty areas.

  For example, Patent Literature 1 and Patent Literature 2 describe a method of temporarily arranging auxiliary cells capable of realizing a plurality of logics in an unused area as means for enabling partial logic correction. Patent Document 3 describes a method of arranging auxiliary cells of a plurality of types according to the size of an unused area.

Japanese Patent Laid-Open No. 10-242289 JP 2002-16143 A JP 2001-358221 A

  However, in the case of the technique of performing logic correction using function cells arranged in the empty area, the function cells previously arranged in the empty area in preparation for logic correction can cope with some logic correction such as adjustment of delay speed. In general, it is not possible to deal with any logic correction.

  In addition, it is difficult for the designer to specify the type of functional cell to be embedded in the empty area in advance, assuming logic correction in the initial stage of design. In addition, even when functional cells that can handle logic correction are embedded in advance, if the location where the logic correction is to be performed and the placement position of the embedded function cell are far from each other, a wiring delay occurs, which is desired. Since the timing cannot be obtained, it may be necessary to recreate the base part.

  In the case of the methods of Patent Document 1 and Patent Document 2, the standard cell type functional cells are standardized at a certain height due to the restrictions of the layout method. It is also necessary to keep this as low as possible. For this reason, it is necessary to align the heights of the auxiliary cells arranged in advance in the empty area of the logic part, and the logic that can be configured by the auxiliary cells created under such conditions is limited. Therefore, logic correction using such an array of auxiliary cells is limited to simple logic changes such as a change in cell driving capability, and there are more advanced design changes such as insertion of flip-flops. In this case, changes from the base bulk structure are added, and the development period becomes longer, resulting in an increase in development costs due to re-creation.

  Further, in the case of the method of Patent Document 3, the feature for enabling various logic corrections is not described as the structure of the auxiliary cell.

  The present invention has been made in view of such circumstances, and by arranging predetermined auxiliary cells using unused areas in a semiconductor integrated circuit, the types of functional cells that can cope with logic correction are enhanced. And flexibly respond to various logic correction requirements like a gate array without losing the advantages of the conventional standard cell system that enables designers to achieve higher integration and lower power consumption more effectively. It is an object of the present invention to provide a semiconductor integrated circuit design method that can be used and a semiconductor integrated circuit designed by such a semiconductor integrated circuit design method.

  In order to solve the above-described problems, in a semiconductor integrated circuit design method of the present invention, a semiconductor integrated circuit design for generating a semiconductor integrated circuit by arranging and wiring a plurality of types of functional cells in a predetermined region based on circuit connection information. In the method, one or more types of auxiliary cells composed of one or more stages in the height direction of a cell capable of realizing a plurality of logics by changing the wiring are prepared, and the plurality of types of functional cells are arranged based on the circuit connection information. After wiring, one or more arbitrary auxiliary cells that can be arranged in the unused area of the predetermined area are arranged, and when there is a change in the circuit connection information, the auxiliary cells arranged in the unused area are The gist is to use.

  According to this configuration, a plurality of auxiliary cells that can realize complex logic such as latches and flip-flops are prepared by changing the wiring in the auxiliary cells, and the auxiliary cells are laid out so as to fit the unused area space. Thus, even when a complicated logic circuit such as a flip-flop is modified, it can be flexibly dealt with. In addition, by preparing auxiliary cells that can realize the same logic in different shapes such as one-stage configuration, two-stage configuration, and three-stage configuration, an unused area that can be arranged in two stages, three stages, etc. Therefore, it is possible to achieve high integration.

  In order to solve the above-described problems, in a semiconductor integrated circuit design method of the present invention, a semiconductor integrated circuit design for generating a semiconductor integrated circuit by arranging and wiring a plurality of types of functional cells in a predetermined region based on circuit connection information. In the method, one or more types of auxiliary cells configured in one or more stages capable of realizing a plurality of logics by changing wiring are prepared, and at least one or more of the functional cells included in the circuit connection information are defined as the functional cells. Any auxiliary cell that can be placed in an unused area of the predetermined area after the placement and routing by replacing the auxiliary cell that can realize the same logic, using it from the initial stage based on the circuit connection information, performing placement and routing When the circuit connection information is changed, the gist is to use the auxiliary cell arranged in the predetermined area.

  According to this configuration, a plurality of auxiliary cells capable of realizing a plurality of logics are prepared by changing the wiring in the auxiliary cell, the function cell included in the circuit connection information is replaced with a replaceable auxiliary cell, and the unused area By arranging the auxiliary cells so as to fit the space, even when the logic circuit is corrected, it is possible to flexibly cope with the change of the wiring in the auxiliary cell. In addition, by preparing the same auxiliary cell in a one-stage configuration, a two-stage configuration, a three-stage configuration, etc., even in an area where cell placement has been difficult conventionally (for example, an area like a rectangle in the vertical direction) It is possible to arrange in unused areas that can be arranged in two stages, three stages, etc., and high integration can be achieved.

  In the method for designing a semiconductor integrated circuit according to the present invention, the one or more auxiliary cells are formed of at least one or more N-type MOSFETs and P-type MOSFETs, and can constitute at least one or more logic functions. is there.

  According to this configuration, since the auxiliary logic cell can be used to realize a minimum logic gate to a complex logic gate, flexibility for logic change is improved.

  In the method for designing a semiconductor integrated circuit according to the present invention, the first auxiliary cell included in one or more types of auxiliary cells and at least one auxiliary cell other than the first auxiliary cell have the same logic. At least one or more functions can be realized.

  According to this configuration, since a plurality of logics that can be realized in the first auxiliary cell can be configured by at least one auxiliary cell other than the first auxiliary cell, a logic change is necessary. In the case where a predetermined functional cell configured using the first auxiliary cell is a change target, if there is at least one auxiliary cell other than the first auxiliary cell arranged in the vicinity thereof, The logic of the first auxiliary cell can be realized by using at least one auxiliary cell other than the first auxiliary cell, and the degree of freedom with respect to the logic change is improved.

  Further, in the method for designing a semiconductor integrated circuit according to the present invention, a logical function equivalent to that of the auxiliary cell constituted by one stage can be realized in the auxiliary cell constituted by a plurality of stages.

  According to this configuration, by preparing the same auxiliary cell in a one-stage configuration, a two-stage configuration, a three-stage configuration, etc., an area that has conventionally been difficult to arrange cells (for example, an area that is rectangular in the vertical direction) ) Can be arranged in an unused area that can be arranged in two stages, three stages, etc., and high integration can be achieved.

  In the semiconductor integrated circuit design method of the present invention, at least one of the auxiliary cells included in one or more types of auxiliary cells has a capacitive element for suppressing conduction noise from a power supply line.

  According to this configuration, by arranging the auxiliary cell in the unused area, an effect of stabilizing the power supply voltage can be obtained and noise countermeasures can be taken.

  In the method for designing a semiconductor integrated circuit according to the present invention, at least one of the N-type MOSFET and the P-type MOSFET forming the auxiliary cell composed of one or more types is configured with at least one type of gate size. ing.

  According to this configuration, the gate size of the N-type MOSFET and the P-type MOSFET can be changed by changing the wiring in the auxiliary cell.

  A semiconductor integrated circuit according to the present invention is designed by the method for designing a semiconductor integrated circuit according to the present invention.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings.
(First embodiment)

<Auxiliary cell configuration>
First, the configuration of the auxiliary cell according to the first embodiment will be described with reference to FIG. 1, FIG. 2, and FIG. FIG. 1 is a block diagram showing a configuration of an auxiliary cell according to the first embodiment of the present invention. Three types of auxiliary cells are prepared: the auxiliary cell 10 in FIG. 1A, the auxiliary cell 20 in FIG. 1B, and the auxiliary cell 30 in FIG. 1C.

  As shown in FIG. 1A, the auxiliary cell 10 includes a P + diffusion region 12 for forming a P channel MOS transistor, an N + diffusion region 13 for forming an N channel MOS transistor, and two polySi gates. 11a and 11b.

  The auxiliary cell 10 forms an inverter by switching wiring, for example, if only one polySi gate 11a is used as shown in FIG. 2 (A), and two polySi gates are used as shown in FIG. 1 (A). If 11a and 11b are utilized, it becomes a functional cell which comprises logic gates, such as a buffer, 2 input NAND, and 2 input NOR. As described above, in the auxiliary cell 10, the logic function is limited to a relatively simple logic gate configuration, but it can be flexibly arranged in a small unused area.

  As shown in FIG. 1B, the auxiliary cell 20 includes a P + diffusion region 12 for forming a P channel MOS transistor, an N + diffusion region 13 for forming an N channel MOS transistor, and four polySi gates. 21a to 21d. Further, an N + diffusion region 13 and a polySi gate 24 are disposed at both left and right ends of the auxiliary cell 20 in order to form a capacitor as a capacitive element.

  If the four polySi gates 21a to 21d are used by switching the wiring, the auxiliary cell 20 forms a logic gate such as a 4-input NAND, a 4-input NOR, and the three polySi gates 21a, 21b, and 21c are used. For example, a functional cell constituting a logic gate such as a three-input NAND, a three-input NOR is formed. Further, the auxiliary cell 20 can also constitute a logic gate that can be configured by the auxiliary cell 10. For example, as shown in FIG. 2 (B), if two polySi gates 21a and 21b are used, a logic gate equivalent to the auxiliary cell 10 can be formed. Therefore, the auxiliary cell 20 can be used instead of the auxiliary cell 10. it can.

  As shown in FIG. 1C, the auxiliary cell 30 includes a P + diffusion region 12 for forming a P channel MOS transistor, an N + diffusion region 13 for forming an N channel MOS transistor, and eight polySi gates. 31a to 31h. Further, an N + diffusion region 13 and a polySi gate 34 are disposed at both left and right ends of the auxiliary cell 30 in order to form a capacitor as a capacitive element.

  The auxiliary cell 30 becomes a functional cell constituting a complex logic gate such as a latch or a flip-flop by switching the wiring. Furthermore, the auxiliary cell 30 can also be configured as a logic gate that can be configured by the auxiliary cell 20 by switching the wiring. For example, as shown in FIG. 2C, a logic gate equivalent to the auxiliary cell 20 can be configured by using four polySi gates 31d to 31g.

  In addition, an auxiliary cell that is horizontally long like the auxiliary cell 30 may have a two-stage configuration or a three-stage configuration.

  FIG. 3 is a block diagram illustrating an auxiliary cell having two stages. The auxiliary cell 30 in FIG. 1C can be configured in two stages as shown in FIG. That is, the auxiliary cell 300 constituted by two stages includes four polySi gates 31a to 31d, a P + diffusion region 12, an N + diffusion region 13 and a polySi gate 34 arranged in the upper stage, and four polySi gates 31e to 31h. The P + diffusion region 12, the N + diffusion region 13, and the polySi gate 34 are arranged in the lower stage.

<Auxiliary cell placement>
Next, a method of arranging auxiliary cells in unused areas will be described with reference to FIG. The functional cell 40 is configured by a conventional standard cell system, and has a unique structure optimized not only for the wiring portion but also for the base portion for each functional cell. FIG. 4A is a layout diagram for explaining a case where auxiliary cells 10 and auxiliary cells 300 configured in two stages are laid out in an unused area after the functional cells 40 are arranged based on circuit connection information. The auxiliary cell 20 has a width in which four auxiliary cells 10 are arranged in the horizontal direction, and the auxiliary cell 30 has a width in which eight auxiliary cells 10 are arranged in the horizontal direction. Further, it is assumed that the auxiliary cell 300 has a width in which the auxiliary cells 10 are arranged in two steps in the vertical direction and four in the horizontal direction.

  In FIG. 4A, in the cell groups 101 and 103 surrounded by a black frame, eight auxiliary cells 10 are continuously arranged in the horizontal direction and can be replaced with the auxiliary cells 30. In the cell groups 102 and 104 surrounded by a black frame, four auxiliary cells 10 are continuously arranged in the horizontal direction and can be replaced with the auxiliary cells 20. Further, in the cell group 105 surrounded by a black frame, the auxiliary cells 10 are continuously arranged in two rows in the vertical direction and four in the horizontal direction, and can be replaced with the auxiliary cells 300.

  FIG. 4B is a layout diagram showing a state in which the cell groups 101 and 103 are replaced with the auxiliary cell 30, the cell groups 102 and 104 are replaced with the auxiliary cell 20, and the cell group 105 is replaced with the auxiliary cell 300. Since the auxiliary cells 30, 20, and 300 are arranged in the vicinity of the functional cell 40, if there is a logic change request such as a latch or flip-flop in the post-simulation process, these auxiliary cells The logic can be changed using.

  According to the embodiment described above, the following effects can be obtained.

  In this embodiment, a plurality of types of auxiliary cells including auxiliary cells capable of realizing complicated logic such as latches and flip-flops are prepared by changing the wiring, and auxiliary cells are laid out so as to fit the unused area space. By doing so, even when a complicated logic circuit correction such as adding a flip-flop occurs, it is possible to flexibly cope with it. In addition, by preparing the same auxiliary cell in a one-stage configuration, a two-stage configuration, a three-stage configuration, etc., even in an area where it has been difficult to arrange functional cells in the past, it has two stages, three stages, etc. It becomes possible to arrange in an unused area that can be arranged across, and high integration can be achieved.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to such embodiment at all, In the range which does not deviate from the meaning of this invention, it can be implemented with various forms. Hereinafter, a modification will be described.

  (Modification 1) Modification 1 of the method for designing a semiconductor integrated circuit according to the present invention will be described. In the first embodiment, the case where three types of auxiliary cells as shown in FIGS. 1A to 1C are used has been described, but the auxiliary cells may be limited to two types. Further, a plurality of types of auxiliary cells may be prepared. For example, an auxiliary cell composed of 6 gates may be provided between the auxiliary cell 20 (4 gates) and the auxiliary cell 30 (8 gates), or an auxiliary cell having a larger number of gates than the auxiliary cell 30 is prepared. May be. In addition, the number of gates of each auxiliary cell in the first embodiment is illustrated for simplification of description, and is not limited thereto. Further, auxiliary cells having the same number of gates but different gate sizes and MOSFET shapes may be prepared.

  (Modification 2) Modification 2 of the method for designing a semiconductor integrated circuit according to the present invention will be described. In the first embodiment, an example in which a plurality of transistor sizes are combined in each of the N-channel MOS transistor and the P-channel MOS transistor included in the three types of auxiliary cells as shown in FIGS. However, the transistor size is not limited to the transistor size, and the transistor size in the auxiliary cell may be uniform or limited to a predetermined size, and optimization is possible by the structure of the auxiliary cell according to the purpose.

  (Modification 3) Modification 3 of the method for designing a semiconductor integrated circuit according to the present invention will be described. In the first embodiment, it has been described that the capacitive elements are arranged at the left and right ends of the auxiliary cell as shown in FIGS. 1B and 1C. However, the capacitive element may be arranged only on one side or the auxiliary cell. The arrangement position and the number of capacitive elements are not limited. Or it does not necessarily need to arrange.

  (Modification 4) Modification 4 of the method for designing a semiconductor integrated circuit according to the present invention will be described. In the first embodiment, the capacitive element is configured in the auxiliary cell as shown in FIGS. 1B and 1C. However, for the purpose of improving the characteristics of the semiconductor integrated circuit, a resistive element, a diode or the like is used as the auxiliary cell. You may comprise in.

  (Modification 5) Modification 5 of the method for designing a semiconductor integrated circuit according to the present invention will be described. For example, four auxiliary cells 10 shown in FIG. 1A can be arranged in a region where the auxiliary cells 30 shown in FIG. 1C are arranged. Further, two auxiliary cells 10 can be arranged in the region where the auxiliary cells 20 shown in FIG. 1B are arranged. In this way, since more functional cells can be arranged and the logic can be corrected, the degree of freedom can be further improved.

The block diagram which shows the structure of the auxiliary cell which concerns on 1st Embodiment of this invention. The block diagram which shows the structure by switching of wiring of an auxiliary cell. The block diagram explaining the auxiliary cell comprised in 2 steps | paragraphs. The layout diagram explaining the method of arrange | positioning an auxiliary cell in an unused area | region. The block diagram of the semiconductor integrated circuit by an embedded array system.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Auxiliary cell, 11a, 11b ... polySi gate, 12 ... P + diffusion region, 13 ... N + diffusion region, 20 ... Auxiliary cell, 21a-21d ... PolySi gate, 24 ... PolySi gate, 30 ... Auxiliary cell, 31a-31h ... polySi gate, 34... polySi gate, 40... functional cell, 101 to 105.

Claims (8)

In a method for designing a semiconductor integrated circuit for generating a semiconductor integrated circuit by arranging and wiring a plurality of types of functional cells in a predetermined region based on circuit connection information,
Prepare one or more types of auxiliary cells with one or more stages in the height direction of the cells that can realize multiple logics by changing the wiring,
After placing and wiring the plurality of types of functional cells based on the circuit connection information, placing one or more arbitrary auxiliary cells that can be placed in an unused area of the predetermined area,
When there is a change in the circuit connection information, use the auxiliary cell arranged in the unused area,
A method for designing a semiconductor integrated circuit. In a semiconductor integrated circuit design method for generating a semiconductor integrated circuit by arranging and wiring a plurality of types of functional cells in a predetermined region based on circuit connection information,
Prepare one or more auxiliary cells composed of one or more stages that can realize multiple logics by changing the wiring.
Replacing at least one function cell included in the circuit connection information with the auxiliary cell capable of realizing the same logic as the function cell, using the circuit connection information based on the initial stage, performing placement and routing;
Arranging one or more arbitrary auxiliary cells that can be arranged in an unused area of the predetermined area after the arrangement and wiring,
When there is a change in the circuit connection information, use the auxiliary cell arranged in the predetermined area,
A method for designing a semiconductor integrated circuit.   3. The method of designing a semiconductor integrated circuit according to claim 1, wherein the one or more auxiliary cells are formed of at least one N-type MOSFET and a P-type MOSFET, and have at least one logic function. A design method of a semiconductor integrated circuit, which is configurable.   4. The method for designing a semiconductor integrated circuit according to claim 1, wherein at least one of the first auxiliary cell and the first auxiliary cell included in the auxiliary cell composed of one or more types. 5. The auxiliary cell can realize at least one equivalent logical function. A method for designing a semiconductor integrated circuit, wherein:   5. The semiconductor integrated circuit design method according to claim 1, wherein a logic function equivalent to that of the auxiliary cell configured in one stage can be realized in the auxiliary cell configured in a plurality of stages. A method for designing a semiconductor integrated circuit.   6. The method of designing a semiconductor integrated circuit according to claim 1, wherein at least one of the auxiliary cells included in the one or more types of auxiliary cells suppresses conduction noise from a power line. A design method of a semiconductor integrated circuit, comprising a capacitive element for performing the operation.   7. The method for designing a semiconductor integrated circuit according to claim 1, wherein at least one of the N-type MOSFET and the P-type MOSFET forming the auxiliary cell including one or more types is at least 1. A method of designing a semiconductor integrated circuit, characterized in that it is configured with a gate size of more than one kind.   A semiconductor integrated circuit designed by the method for designing a semiconductor integrated circuit according to claim 1.

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