JP2010225738A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of executing power consumption suppression control in a standby mode without increasing circuit scale. <P>SOLUTION: Each of a supply path of a power voltage to a flip-flop group 11, a supply path to a clock transmission system circuit 12, and a supply path to a combination circuit 13 is branched as a different power line. When a standby mode is set in which the combination circuit 13 of this semiconductor integrated circuit 10 does not need to be driven, a power control circuit 15 blocks only supply of the power voltage to the combination circuit 13 by turning off a switch 53 while switches 51, 52 are kept on. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit incorporated in a small terminal such as a mobile phone.

  Many of the semiconductor integrated circuits incorporated in small terminals such as mobile phones have a mechanism for suppressing current consumption in the standby mode. For example, the semiconductor integrated circuit disclosed in Patent Document 1 includes a data holding type flip-flop that operates only in a standby mode in addition to a circuit group such as a flip-flop that operates in an active mode and other gate circuits. The circuit configuration is such that the signal line forming the power supply voltage supply path to the type flip-flop is narrower than the signal line forming the power supply voltage supply path to the other circuit groups.

JP 2005-167184 A

In the case of the semiconductor integrated circuit disclosed in Patent Document 1, since the layout of some signal lines is narrowed, the wiring space is somewhat smaller than making all the signal lines have the same line width. it can. However, in the case of this semiconductor integrated circuit, there is a problem that an extra signal holding flip-flop which is not necessary in the first place and an extra signal line for supplying a power supply voltage to the data holding flip-flop must be provided.
The present invention has been devised under such a background, and an object of the present invention is to provide a semiconductor integrated circuit capable of performing power consumption suppression control in the standby mode without increasing the circuit scale.

  The present invention has a flip-flop group and a clock transmission system circuit that transmits a clock to the flip-flop group, and also has a combinational circuit in addition to these, and the power supply voltage to the flip-flop group and the clock transmission system circuit Provided is a semiconductor integrated circuit in which a supply path and a supply voltage supply path to the combinational circuit are separated. While a small terminal equipped with a semiconductor integrated circuit is in standby mode, flip-flop groups that store data to be handled when the standby mode returns to active mode, and clocks that transmit clocks to those flip-flop groups Although it is necessary to supply the power supply voltage to the transmission system circuit, it is not necessary to supply the power supply voltage to the combinational circuit that is neither the flip-flop group nor the clock transmission system circuit. The present invention is characterized in that the power supply voltage supply path to the flip-flop group and the clock transmission system circuit and the power supply voltage supply path to the combinational circuit are separated. Therefore, during standby mode, power consumption suppression control such as supplying power supply voltage to the flip-flop group and the clock transmission system circuit while shutting off supply of power supply voltage to the combinational circuit is performed with a small circuit scale such as a switch. It can be realized using an element.

It is a figure which shows an example of the electrical constitution of the semiconductor integrated circuit which is one Embodiment of this invention. It is a figure which shows another example of the electrical constitution of the semiconductor integrated circuit which is one Embodiment of this invention. It is a figure which shows the layout in the case of implement | achieving the semiconductor integrated circuit of the electrical structure shown in FIG. 1 as a cell-based IC chip. FIG. 3 is a diagram showing a layout when the semiconductor integrated circuit having the electrical configuration shown in FIG. 2 is realized as a cell-based IC chip. 5 is a flowchart showing a procedure for layout design of the IC chip shown in FIGS. 3 and 4. Arrangement area C of the clock transmission system circuit and power supply control circuit, arrangement area L of the combinational circuit, arrangement area F of the flip-flop group, and arrangement area S of the power supply control circuit defined in the layout design shown in FIG. FIG. It is a figure which shows an example of the electrical constitution of the semiconductor integrated circuit which is other embodiment of this invention. It is a figure which shows an example of the electrical constitution of the semiconductor integrated circuit which is other embodiment of this invention.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a diagram showing an example of an electrical configuration of a semiconductor integrated circuit 10 according to an embodiment of the present invention. FIG. 2 shows another example of the electrical configuration of the semiconductor integrated circuit 10 according to an embodiment of the present invention. It is a figure which shows an example. The semiconductor integrated circuit 10 according to the present embodiment is mounted on a mobile phone. The semiconductor integrated circuit 10 includes a flip-flop group 11, a clock transmission system circuit 12 that is a circuit that transmits a clock to the flip-flop group 11, and a voltage source VDD external to the semiconductor integrated circuit 10 to the semiconductor integrated circuit 10. A power supply control circuit 15 that is a circuit for controlling the supply of the power supply voltage, and another combinational circuit 13 thereof. In this semiconductor integrated circuit 10, a power supply voltage supply path to the flip-flop group 11, a power supply voltage supply path to the clock transmission system circuit 12, a power supply voltage supply path to the combinational circuit 13, and a power supply control circuit 15. Each of the supply paths of the power supply voltage to is separated as a different power supply line.

  More specifically, in the semiconductor integrated circuit 10 shown in FIG. 1, a power supply voltage supply path to the high-potential side power supply line 21 and the clock transmission system circuit 12 that form a power supply voltage supply path to the flip-flop group 11 is formed. The high potential side power supply line 22 and the high potential side power supply line 23 forming a power supply voltage supply path to the combinational circuit 13 are connected to the voltage source VDD outside the semiconductor integrated circuit 10 via the switches 51, 52 and 53, respectively. The high-potential-side power line 24 that is connected to the positive electrode and forms a power supply voltage supply path to the power supply control circuit 15 is connected to the positive electrode of the voltage source VDD without passing through the switches 51, 52, and 53. Further, the low-potential-side power supply line 30 that forms a power supply voltage supply path to the flip-flop group 11, the clock transmission system circuit 12, the combinational circuit 13, and the power supply control circuit 15 is connected to the negative electrode of the voltage source VDD. The power supply control circuit 15 outputs a control signal for switching on / off of each of the switches 51, 52, 53. When the switch 51 is switched from on to off, the supply of power supply voltage to the flip-flop group 11 is cut off. When the switch 52 is switched from on to off, supply of power supply voltage to the clock transmission system circuit 12 is cut off. When the switch 53 is switched from on to off, the supply of the power supply voltage to the combinational circuit 13 is cut off.

  In the semiconductor integrated circuit 10 shown in FIG. 2, the high-potential side power supply line 20 that forms the supply path of the power supply voltage to the flip-flop group 11, the clock transmission system circuit 12, the combinational circuit 13, and the power supply control circuit 15 is the semiconductor integrated circuit. 10 is connected to the positive electrode of the external voltage source VDD. Further, the low-potential side power supply line 31 that forms the supply path of the power supply voltage to the flip-flop group 11, the low-potential side power supply line 32 that forms the supply path of the power supply voltage to the clock transmission system circuit 12, and the power supply to the combinational circuit 13 A low-potential-side power line 33 that forms a voltage supply path is connected to the negative electrode of the voltage source VDD via switches 51, 52, and 53, and a low-potential-side power supply that forms a supply path for the power supply voltage to the power supply control circuit 15. The line 34 is connected to the negative electrode of the voltage source VDD without going through the switches 51, 52, 53. As in the example of FIG. 1, the power supply control circuit 15 outputs a control signal for switching on / off of each of the switches 51, 52, and 53.

  The semiconductor integrated circuit 10 having the electrical configuration shown in FIGS. 1 and 2 can be realized as a cell-based IC chip. FIG. 3 is a diagram showing a layout when the semiconductor integrated circuit 10 having the electrical configuration shown in FIG. 1 is realized as a cell-based IC chip. FIG. 4 is a diagram showing a layout when the semiconductor integrated circuit 10 having the electrical configuration shown in FIG. 2 is realized as a cell-based IC chip.

  In the vicinity of the periphery of the substrate 59 of the semiconductor integrated circuit 10 having the layout shown in FIGS. 3 and 4, a peripheral region in which bonding pads 61-k (k = 1 to 22) and I / O buffers (not shown) are provided in a ring shape. 60. Further, switches 51, 52, and 53 are arranged in the peripheral region 60. It is desirable that the switches 51, 52 and 53 are constituted by large-sized N-type MOS transistors and P-type MOS transistors capable of flowing a large current, or a combination thereof. Inside the peripheral area 60 is an internal circuit arrangement area 63, and the flip-flop group 11, the clock transmission system circuit 12, the combinational circuit 13, and the power supply control circuit 15 divide the occupied area in the internal circuit arrangement area 63. And a wiring pattern including a power supply line and a signal line is formed.

  This will be described in more detail. In the layout shown in FIG. 3, a power supply trunk line 64 and a ground trunk line 65 are laid inside the left end and the right end of the internal circuit arrangement region 63, respectively. Is connected to the bonding pad 61-10. Between the power supply trunk line 64 and the ground trunk line 65, the high potential side power supply line 22, the low potential side power supply line 30a, the high potential side power supply line 23, the low potential side power supply line 30b, the high potential side power supply line 21, and the low potential side Seven power lines, that is, the power line 30c and the high-potential side power line 24, are laid with an interval in the vertical direction. Of these seven power lines, the high potential side power lines 22, 23, and 21 are connected to the power source trunk line 64 via the switches 52, 53, and 51, and the high potential side power line 24 is connected to the switches 52, 53, and 51. It is connected to the power supply trunk line 64 without being interposed. Further, the low potential side power supply lines 30 a, 30 b and 30 c are connected to the ground trunk line 65.

  Between the high potential side power supply line 22 and the low potential side power supply line 30a, cells for realizing the functional macro of the clock transmission system circuit 12 are densely arranged so as to form a row 70-1, and the low potential side power supply line 30a and Cells between the high-potential side power supply line 23 and between the high-potential side power supply line 23 and the low-potential side power supply line 30b are so dense that cells that realize the functional macro of the combinational circuit 13 form rows 70-2 and 70-3. Has been placed. Between the low-potential side power supply line 30b and the high-potential side power supply line 21 and between the high-potential side power supply line 21 and the low-potential side power supply line 30c, cells that realize the functional macro of the flip-flop group 11 are arranged in the row 70-4. , 70-5, and a cell that realizes a functional macro of the power supply control circuit 15 forms a row 70-6 between the low-potential-side power supply line 30 c and the high-potential-side power supply line 24. It is densely arranged. Here, the cell is a set of layout patterns of transistors and wiring between transistors for realizing various function macros. The gates of the switches 52, 53, 51 are connected to the power supply control circuit 15 through signal lines 66-2, 66-3, 66-1.

  In the layout shown in FIG. 4, a ground trunk 65 and a power trunk 64 are respectively laid inside the left end and the right end of the internal circuit arrangement region 63, and the ground trunk 65 is composed of the bonding pad 61-20 and the power trunk. 64 is connected to the bonding pad 61-10. Between the ground trunk 65 and the power trunk 64, the low potential power line 32, the high potential power line 20a, the low potential power line 33, the high potential power line 20b, the low potential power line 31, and the high potential side. Seven power lines, that is, the power line 20c and the low-potential-side power line 34, are laid out with an interval in the vertical direction. Of these seven power lines, the low potential side power lines 32, 33 and 31 are connected to the ground trunk line 65 via the switches 52, 53 and 51, and the low potential side power line 34 is connected to the switches 52, 53 and 51. It is connected to the ground trunk 65 without being interposed. The high potential side power supply lines 20 a, 20 b and 20 c are connected to the power supply trunk line 64.

  Between the low potential side power supply line 32 and the high potential side power supply line 20a, cells for realizing the functional macro of the clock transmission system circuit 12 are densely arranged so as to form a row 70-1, and the high potential side power supply line 20a and Cells between the low-potential power supply line 33 and between the low-potential power supply line 33 and the high-potential power supply line 20b are so dense that cells that realize the function macro of the combinational circuit 13 form rows 70-2 and 70-3. Be placed. Between the high-potential side power supply line 20b and the low-potential side power supply line 31, and between the low-potential side power supply line 31 and the high-potential side power supply line 20c, cells that realize the function macro of the flip-flop group 11 are arranged in the rows 70-4. 70-5 is densely arranged so as to form a cell 70, and between the high-potential-side power supply line 20c and the low-potential-side power supply line 34, a cell that realizes a function macro of the power supply control circuit 15 is arranged so as to form a row 70-6. Has been. Similar to the layout of FIG. 4, the gates of the switches 52, 53, 51 are connected to the power supply control circuit 15 via signal lines 66-2, 66-3, 66-1.

  When the semiconductor integrated circuit 10 having the layout shown in FIGS. 3 and 4 is mounted on a small terminal, the bonding pads 61-k (k = 1 to 22) are externally connected via the lead wires of the package of the semiconductor integrated circuit 10. It can be connected to any element. Therefore, the semiconductor integrated circuit 10 having the layout shown in FIG. 3 has a mounting mode in which the bonding pad 61-20 is connected to the positive electrode of the voltage source VDD and the bonding pad 61-10 is connected to the negative electrode of the voltage source VDD. By adopting it, an electrical configuration equivalent to that in FIG. 1 can be realized. Further, the semiconductor integrated circuit 10 having the layout shown in FIG. 4 has a mounting mode in which the bonding pad 61-20 is connected to the negative electrode of the voltage source VDD, and the bonding pad 61-10 is connected to the positive electrode of the voltage source VDD. By adopting it, an electrical configuration equivalent to FIG. 2 can be realized.

Here, the semiconductor integrated circuit 10 according to the present embodiment operates in three operation modes: an active mode, a data output mode, and a standby mode.
The active mode is a mode in which all of the flip-flop group 11, the clock transmission system circuit 12, the combinational circuit 13, and the power supply control circuit 15 are operated. In this active mode, the semiconductor integrated circuit 10 performs various processes related to telephone calls and web browsing. The power supply control circuit 15 of the semiconductor integrated circuit 10 switches the switch 51 when an event (referred to as an “active mode activation event”) that prompts the transition to the active mode occurs due to an operation of the mobile phone on which the semiconductor integrated circuit 10 is mounted. , 52 and 53 are output as control signals. As a result, the power supply voltage is supplied to the flip-flop group 11, the clock transmission system circuit 12, and the combinational circuit 13.

  The data output mode is a mode in which the flip-flop group 11, the combinational circuit 13, and the power supply control circuit 15 are operated. In this data output mode, the semiconductor integrated circuit 10 processes the data stored in the flip-flop group 11 by the combinational circuit 13 and outputs the processed data. When the power control circuit 15 of the semiconductor integrated circuit 10 generates an event (referred to as a “data output mode activation event”) that prompts a transition to the data output mode by operating a mobile phone on which the semiconductor integrated circuit 10 is mounted. A control signal for turning on the switches 51 and 53 and turning off the switch 52 is output. As a result, the power supply voltage is supplied to the flip-flop group 11 and the combinational circuit 13, and the supply of the power supply voltage to the clock transmission system circuit 12 is cut off.

  The standby mode is a mode in which the flip-flop group 11, the clock transmission system circuit 12, and the power supply control circuit 15 are operated. In the standby mode, the semiconductor integrated circuit 10 continues to hold the stored contents of the flip-flop group 11 before the transition to the standby mode. The power supply control circuit 15 of the semiconductor integrated circuit 10 turns on the switches 51 and 52 and turns off the switch 53 when neither an active mode activation event nor a data output mode activation event occurs for a certain length of time. Output a control signal. As a result, the power supply voltage is supplied to the flip-flop group 11 and the clock transmission system circuit 12, and the supply of the power supply voltage to the combinational circuit 13 is cut off.

Next, the layout design procedure of the semiconductor integrated circuit 10 according to the present embodiment will be explained. FIG. 5 is a flowchart showing a layout design procedure.
The layout design of the semiconductor integrated circuit 10 is performed using the cells recorded in the cell library. The cell library is a database that collects data related to cells that realize various function macros that may be frequently used, such as combinational logic circuits and sequential logic circuits. In this cell library, the data related to cells that implement various function macros includes data for specifying the size of the cell itself, as well as the layout pattern of the transistors and wiring between transistors for realizing the function macro, and the input terminals in the cell. And data specifying the position of the output terminal.

  A series of processing shown in FIG. 5 is performed based on the net list. The netlist defines cells constituting each element of the flip-flop group 11, the clock transmission system circuit 12, the combinational circuit 13, and the power supply control circuit 15 of the semiconductor integrated circuit 10 that is the layout design target, and the elements. This data defines the connection relationship between the two.

First, based on the netlist, an arrangement area C where the clock transmission system circuit 12 is arranged, an arrangement area L where the combinational circuit 13 is arranged, an arrangement area F where the flip-flop group 11 is arranged, and the power supply control circuit 15 An arrangement possible area S to be arranged is defined (S100). More specifically, among the cells defined by the netlist, data specifying the size of the cells constituting the clock transmission system circuit 12 is obtained from the cell library, and the sum of the cell sizes is obtained from these data, A rectangular area in which cells corresponding to the total size can be arranged is defined as an arrangementable area C. As shown in FIG. _6A , the vertical width W _CELL of the dispositionable region C is slightly larger than the vertical width of one cell, and the horizontal width is sufficiently larger than the vertical width. Subsequently, data specifying the size of the cells constituting the combinational circuit 13 among the cells defined by the netlist is obtained from the cell library, the total cell size is obtained from these data, and cells for the total size are obtained. One or a plurality of rectangular areas that can be accommodated collectively or divided are defined as an arrangementable area L. As shown in FIG. 6B, the arrangeable area L is arranged in the vertical direction with a gap W _LINE below the arrangeable area C, and the dimensions thereof are the same as those of the arrangeable area C. Further, data specifying the size of the cells constituting the flip-flop group 11 among the cells defined by the netlist is obtained from the cell library, and the total cell size is obtained from the data, and cells corresponding to the total size are obtained. One or a plurality of rectangular areas that can be accommodated collectively or divided are defined as an arrangementable area F. As shown in FIG. 6C, the dispositionable area F is arranged in the vertical direction with a gap _WLINE below the dispositionable area L, and the dimensions thereof are the same as those of the dispositionable area C. Finally, data specifying the size of the cells constituting the power supply control circuit 15 among the cells defined by the netlist is acquired from the cell library, and the total of the cell sizes is obtained from these data, and the amount of the total size is obtained. One or a plurality of rectangular areas that can be accommodated by collecting or dividing cells are defined as an arrangementable area S. As shown in FIG. 6 (D), allocable area S is arranged vertically with a gap W _LINE under allocable area F, the dimension is the same as the arrangement area C.

Next, a voltage source VDD that is a supply source of the power supply voltage to the semiconductor integrated circuit 10 is defined (S110), and the arrangeable regions C, L, F, and S are associated with the voltage source VDD (S120).
Thereafter, the cells constituting the functional macros of the flip-flop group 11, the combinational circuit 13, and the power supply control circuit 15 are respectively arranged in the arrangementable areas F, L, and S (S130). More specifically, in this step S130, cells constituting the function macro of the flip-flop group 11 are selected from the cells defined by the net list, and these cells are arranged in the arrangementable region F. Next, the cells constituting the function macro of the combinational circuit 13 are selected from the cells defined by the list, and these cells are arranged in the arrangementable region L. Further, the cells constituting the function macro of the power supply control circuit 15 are selected from the cells defined by the list, and these cells are arranged in the arrangementable region S. The placement of each cell in step S130 may be performed according to a known cell placement algorithm.

  In the subsequent step S140, the cell placement destination is set to the placeable area C, and the clock tree which is the clock transmission system circuit 12 based on the placement in the placeable areas L and F of the cells having clock input terminals among the cells. And the cells constituting the buffer forming the clock tree are arranged. More specifically, the clock tree is transmitted so that the clock is transmitted to the clock input terminal of each cell with a delay time within the allowable range, and the clock arrival timing skew between the input terminals is within the allowable range. Decide where to place the buffers that make up

  Furthermore, when the arrival timing of the clock from the cell arranged in the arrangeable area C to the clock input terminal of the cell arranged in the arrangeable areas L and F is simulated, and the arrival timing calculated by the simulation does not satisfy the timing constraint Changes the arrangement of cells in the arrangeable areas L and F so as to satisfy the timing constraint (S150).

  Further, the wiring pattern of the signal wiring between the cells arranged in the arrangement possible areas C, L, F, S is determined (S160). The determination of the wiring pattern in step S160 may be performed according to a known wiring pattern determination algorithm.

  Further, the arrival timing of the clock from the cell arranged in the arrangementable area C to the clock input terminal of the cell arranged in the arrangementable areas L, F, S is considered in consideration of the delay amount of the signal wiring in the wiring pattern determined in step S160. Then, the simulation is performed again, and if the arrival timing determined by the simulation does not satisfy the timing constraint, the wiring pattern is changed so as to satisfy the timing constraint (S170).

  Finally, data (referred to as “mask data”) indicating the cell arrangement and the wiring pattern in the arrangement possible areas C, L, F, and S in a GDS (Graphic Design System) format is generated (S180).

  In the semiconductor integrated circuit 10 described above, the power supply voltage supply path to the flip-flop group 11, the power supply voltage supply path to the clock transmission system circuit 12, and the power supply voltage supply path to the combinational circuit 13 are different from each other. Divided as lines. The power supply control circuit 15 then switches all of the switches 51, 52, and 53 on the power supply lines that form the power supply voltage supply path to each of the flip-flop group 11, the clock transmission system circuit 12, and the combinational circuit 13. Or cut off the supply of the power supply voltage to a part. Therefore, when the standby mode in which the combinational circuit 13 of the semiconductor integrated circuit 10 does not need to be operated is entered, the power supply voltage to the combinational circuit 13 is reduced by turning off the switch 53 while turning on the switches 51 and 52. Only the supply can be cut off, and the current consumption of the semiconductor integrated circuit 10 can be suppressed.

Although one embodiment of the present invention has been described above, the present invention may have other embodiments. For example, it is as follows.
(1) In the above embodiment, the flip-flop group 11, the clock transmission system circuit 12, and the combinational circuit 13 are supplied with the power supply voltage from the common voltage source VDD, and the power supply voltage supply path extending from the voltage source VDD to each of them. Were separated by different power lines. However, as shown in FIGS. 7 and 8, the flip-flop group 11, the clock transmission system circuit 12, and the combinational circuit 13 are supplied with power supply voltages from different voltage sources VDD_FF, VDD_CK, VDD via different power supply lines. You may do it. In these cases, in the layout design of the semiconductor integrated circuit 10A shown in FIGS. 7 and 8, step S110 shown in FIG. 5 includes the voltage source VDD_FF, which is the supply source of the power supply voltage to the flip-flop group 11, and the clock transmission. A step of defining a power supply voltage VDD_CK that is a power supply voltage supply source to the system circuit 12 and a power supply voltage VDD that is a power supply voltage supply source to the combinational circuit 13; It is preferable to include a step of associating VDD_CK, the arrangeable region F with the voltage source VDD_FF, and the arrangeable region L with the voltage source VDD. 7 and 8, the power supply control circuit 15 is configured to receive power supply voltage from the voltage source VDD_FF, but may be configured to receive power supply voltage from the voltage source VDD_CK. The power supply voltage may be supplied from the voltage source VDD.

(2) In the above embodiment, the layout design of the semiconductor integrated circuit 10 is performed using the cells recorded in the cell library. However, the semiconductor integrated circuit 10 may be configured by a gate array or an embedded cell array.

(3) In the above embodiment, the internal circuit arrangement region 63 of the semiconductor integrated circuit 10 is divided into a plurality of rows 70-n (n = 1 to 6), and the cells that realize the functional macro of the clock transmission system circuit 12 are the rows 70. −1, the cells realizing the function macro of the combinational circuit 13 form rows 70-2 and 70-3, the cells realizing the function macro of the flip-flop group 11 form rows 70-4 and 70-5, The cells for realizing the function macro of the power supply control circuit 15 are densely arranged so as to form a row 70-6. However, the internal circuit arrangement region 63 of the semiconductor integrated circuit 10 is divided into a plurality of columns, and the cells for realizing the function macros of the clock transmission system circuit 12, the flip-flop group 11, the combinational circuit 13, and the power supply control circuit 15 are different columns. It may be densely arranged to form.

(4) In the above embodiment, the power supply voltage supply path to the flip-flop group 11, the power supply voltage supply path to the clock transmission system circuit 12, and the power supply voltage supply path to the combinational circuit 13 are respectively connected to the switch 51, 52 and 53 are inserted, and the power supply control circuit 15 switches on / off of the switches 51, 52 and 53, thereby supplying power supply voltages to the flip-flop group 11, the clock transmission system circuit 12, and the combinational circuit 13. The supply of was cut off. However, a switch may be inserted only into the high-potential side power supply line or the low-potential side power supply line that forms the power supply voltage supply path to the combinational circuit 13. According to this embodiment, the current consumption control in the standby mode when the operation mode transitions only between the standby mode that does not require the operation of the combinational circuit 13 and the active mode that requires the operation of the combinational circuit 13 is performed by the switch This can be realized by switching.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor integrated circuit, 11 ... Flip-flop group, 12 ... Clock transmission system circuit, 13 ... Combination circuit, 15 ... Power supply control circuit, 20, 21, 22, 23, 24 ... High potential side power supply line, 30, 31, 32, 34 ... low potential side power supply line, 51, 52, 53 ... switch, 59 ... substrate, 61 ... bonding pad.

Claims (3)

  A flip-flop group and a clock transmission system circuit that transmits a clock to the flip-flop group, and in addition to these, a combinational circuit, a supply voltage supply path to the flip-flop group and the clock transmission system circuit, and A semiconductor integrated circuit characterized in that a power supply voltage supply path to a combinational circuit is separated.   2. The semiconductor integrated circuit according to claim 1, wherein a switch is inserted into a high-potential side power line or a low-potential side power line that forms a power supply voltage supply path to the combinational circuit.   3. The semiconductor integrated circuit according to claim 1, wherein the flip-flop group, the clock transmission system circuit, and the combinational circuit are densely arranged by dividing an occupied area.

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