JP2008034514A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device formed with lead-free solder capable of suppressing the occurrence of cracks in a semiconductor chip.
SOLUTION: A semiconductor chip 21, a die pad 12 facing the back surface of the semiconductor chip 21, and an intermetallic compound 19 mainly composed of Cu-Sn are arranged between the peripheral portion of the back surface of the semiconductor chip 21 and the die pad 12. Then, an Sn-based solder 18 containing Sn as a main component is disposed between the center portion of the back surface of the semiconductor chip 21 and the die pad 12, and a joining member 17 that joins the die pad 12 facing the back surface of the semiconductor chip 21. Have.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device that can cope with external lead-free solder connection.

  Solder (external connection solder) used when mounting an electronic device including a semiconductor device or the like on a printed board or the like has a large environmental load, and therefore lead-free is rapidly progressing. For example, Sn-3Ag-0.5Cu (the number represents mass%. 96.5 mass% of the maximum Sn is omitted. The same shall apply hereinafter) is the mainstream as a highly versatile solder. .

  Inside the semiconductor device, for example, solder is used when connecting a semiconductor chip to an internal substrate, but the solder used internally (internal connection solder) needs to be lead-free. Even if lead-free solder used inside is connected to the outside of the semiconductor device by, for example, Sn-3Ag-0.5Cu-based solder, a connection failure that deteriorates the characteristics of the semiconductor device does not occur. It is necessary to do so. Therefore, an appropriate material that does not cause poor connection to the connection process of Sn-3Ag-0.5Cu solder as an external connection solder (melting temperature range is solid phase line 217 ° C., liquid phase line 219 ° C.) Developments have been made to find ways.

  Conventionally, the solder composed of Sn and Pb can be selectively used as an internal connection solder convenient for internal connection of a semiconductor device and an external connection solder convenient for external connection by changing the composition ratio. It was. For example, by using Sn-37Pb solder with a low melting point of 183 ° C. and Pb-10Sn solder with a high melting point of 275 to 302 ° C. as an external connection solder and an internal connection solder, respectively, The connection solder between the semiconductor chip and the internal substrate did not melt, and the characteristics of the semiconductor device due to poor connection did not deteriorate. However, like Sn—Pb solder, the difference in melting point can be taken moderately, and the requirements necessary for connection such as absorption of stress caused by the difference in thermal expansion can be satisfied. No high lead-free solder has been found.

  Therefore, a solder material in which Sn powder and Cu powder are mixed, and this solder material is used for the purpose of preventing a connection failure even if remelting occurs in part during external connection of a semiconductor device or the like. A disclosed semiconductor device or the like is disclosed (for example, see Patent Document 1). When a semiconductor chip is connected using a solder material in which this Sn powder and Cu powder are mixed, Sn and Cu combine to form an intermetallic compound having a high melting point, and the external connection mounting reflow temperature (around 240 ° C.) The intermetallic compound and Cu are not melted, and the connection strength can be secured.

However, in the disclosed method, the solder material on the back surface of the semiconductor chip inside the semiconductor device is connected to the entire surface by the Sn—Cu intermetallic compound. Intermetallic compounds are hard and brittle, so when applied to large area semiconductor chips (for example, rectangles with a side of about 3 mm or more), the temperature difference during cooling after connecting the semiconductor chip or the heat after completion of the semiconductor device There was a possibility that a crack was generated in the semiconductor chip due to thermal shock caused by the cycle.
JP 2002-280396 A (page 7, FIG. 2)

  The present invention provides a semiconductor device in which lead-free solder capable of suppressing the occurrence of cracks in a semiconductor chip is formed.

  A semiconductor device according to one embodiment of the present invention includes a semiconductor chip, a metal member facing the back surface of the semiconductor chip, an intermetallic compound containing Cu—Sn as a main component, a peripheral portion on the back surface of the semiconductor chip, and the metal member. Between any one of Sn and Sn as a main component between the central part of the back surface of the semiconductor chip and the metal member, and facing the back surface of the semiconductor chip. It has the joining member which joins a metal member, It is characterized by the above-mentioned.

  ADVANTAGE OF THE INVENTION According to this invention, it is possible to provide the semiconductor device in which the lead free solder which can suppress generation | occurrence | production of the crack of a semiconductor chip was formed.

  Embodiments of the present invention will be described below with reference to the drawings. In each figure, the same components are denoted by the same reference numerals.

  A semiconductor device according to Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 1 is a cross-sectional view schematically showing a semiconductor device. FIG. 2 is a cross-sectional view schematically showing an enlarged connection portion by solder of the semiconductor device shown in FIG. FIG. 3 is a cross-sectional view schematically showing a state where solder is supplied in the process of manufacturing a semiconductor device. FIG. 4 is a cross-sectional view schematically showing a state where the semiconductor device is mounted on the mounting substrate.

  As shown in FIG. 1, a semiconductor device 1 includes a semiconductor chip 21, a die pad 12 that forms part of a lead frame 11 that is a metal member facing the back surface of the semiconductor chip 21, and a metal mainly composed of Cu—Sn. The intermetallic compound 19 is disposed between the peripheral portion of the back surface of the semiconductor chip 21 and the die pad 12, and the Sn-based solder 18 mainly composed of Sn is disposed between the central portion of the back surface of the semiconductor chip 21 and the die pad 12. A joining member 17 for joining the back surface of the semiconductor chip 21 and the die pad 12 facing the semiconductor chip 21 is provided as a main component.

  Further, in the semiconductor device 1, the electrode 23 formed on the surface of the semiconductor chip 21 is connected to the inner lead 13 through the fine metal wire 25, and the die pad 12 and the inner lead 13 are connected to the outer lead 14, respectively. The inner lead 13, the joining member 17, the semiconductor chip 21, the fine metal wire 25, and the like are sealed with a sealing resin 31. Here, the joining member 17 bears internal connection.

  The lead frame 11 is an alloy containing Cu as a main component. The lead frame 11 has a thickness of about 0.5 mm, and a portion where the semiconductor chip 21 is mounted is a die pad 12 and a portion where the thin metal wire 25 is connected is an inner lead 13. The die pad 12 and the inner lead 13 are respectively formed integrally with the outer lead 13, and the bottom surfaces to be mounted are substantially the same surface. Further, the die pad 12 and the inner lead 13 may be connected to the outer lead 13 via a thin metal wire (not shown), respectively. Further, the bottom surfaces of the die pad 12 and the inner lead 13 are set higher than the bottom surface of the outer lead 13 (on the semiconductor chip 21 side), and the bottom surfaces of the die pad 12 and the inner lead 13 are also sealed with the sealing resin 31. Good.

The joining member 17 is composed of an Sn-based solder 18 and an intermetallic compound 19. As shown in FIG. 2, an intermetallic compound 19 is formed between the die pad 12 facing the semiconductor chip 21 and in the periphery of the back surface of the semiconductor chip 21. The intermetallic compound 19 is in contact with the high-concentration Cu compound 27 mainly composed of Cu ₃ Sn and the high-concentration Cu compound 27, which has a relatively large proportion of continuous Cu on the die pad 12, and the back surface of the semiconductor chip 21. The ratio of Cu reaching to is relatively small, and is composed of a low-concentration Cu compound 28 mainly composed of Cu ₆ Sn ₅ .

  The boundary line between the high-concentration Cu compound 27 and the Cu alloy of the die pad 12 has an irregular shape, and is formed at a position entering the inside of the die pad 12 as compared with the surface of the peripheral region. The boundary line between the high-concentration Cu compound 27 and the low-concentration Cu compound 28 has an irregular shape and is compared with the film thickness of the low-concentration Cu compound 28 (distance between the high-concentration Cu compound 27 and the back surface of the semiconductor chip 21). Thus, the film thickness of the high concentration Cu compound 27 is much smaller. The low-concentration Cu compound 28 is mixed in a lump shape, a plate shape, a needle shape, or the like.

  The Sn-based solder 18 is a metal whose main component is Sn. The Sn-based solder 18 is in contact with the Ag layer 15 formed on the upper surface of the die pad 12 facing the central portion of the back surface of the semiconductor chip 21 and in a region (referred to as the central portion) excluding the peripheral portion of the back surface of the semiconductor chip 21. Has reached. The Ag layer 15 has a film thickness of about 5 μm and is produced by plating, but may be produced by other methods such as vapor deposition or sputtering. The Sn-based solder 18 contains a small amount of Cu, Ag, and the like taken from surrounding members in contact therewith. In addition, island-shaped Sn-based solder 18 is distributed in the region of the low concentration Cu compound 28.

  The thickness of the intermetallic compound 19 is approximately equal to the distance between the die pad 12 and the back surface of the semiconductor chip 21 and is about 20 μm. The intermetallic compound 19 tends to have a relatively large width or a dense distribution on the die pad 12 side except for a region in contact with the Ag layer 15. On the semiconductor chip 21 side, the width tends to be relatively small or coarsely distributed. The Sn-based solder 18 is distributed so as to be bonded to the back surface of the semiconductor chip 21 and fill a gap surrounded by the intermetallic compound 19 surrounding the periphery and the Ag plating 15 on the bottom surface.

  A process of forming the bonding member 17 of the semiconductor device 1, that is, fixing the semiconductor chip 21 to the die pad 12 will be described. As shown in FIG. 3, the die pad 12 of the lead frame 11 on which the semiconductor chip 21 having a side of about 5 mm square is to be placed is opposed to the back surface of the semiconductor chip 21 and is the outermost surface of the back surface of the semiconductor chip 21. An Ag layer 15 having a rectangular shape with an inner periphery of about 100 μm from the periphery is plated.

  A paste-like Sn-based solder 18a in an amount necessary for the bonding interval between the die pad 12 and the semiconductor chip 21 is formed in a rectangular parallelepiped shape, for example, by protruding outward from the outer periphery of the Ag layer 15 by about 100 μm. The Sn-based solder 18a is pure Sn excluding unintended impurities, or a binary system such as Sn—Ag, Sn—Sb, Sn—Cu, etc. containing Sn as a main component, and Sn as a main component. One of ternary systems or the like may be used, and a small amount of flux (not shown) can be added as necessary. Note that the Sn-based solder 18a has an amount of about 20 μm when solidified to form the joining member 17, but the thickness can be increased or decreased as necessary. The flux is preferably a type that does not require cleaning.

  Next, the semiconductor chip 21 is reflow-heated in an inert atmosphere such as nitrogen or a reducing atmosphere obtained by adding a little hydrogen to nitrogen, with the back surface in contact with the Sn-based solder 18a. When flux is added, atmospheric reflow may be used. If the heating temperature is the Sn melting point of 232 ° C. or higher, the Sn-based solder 18a melts, but the Sn-based solder 18a and the Cu of the die pad 12 react to form an intermetallic compound 19 around the Sn-based solder 18a. The heating time is set to 320 ° C. to 380 ° C. and the heating time is set to 60 seconds or longer. Further, in order to improve the wettability with the Sn-based solder 18a, for example, Ti / Ni / Ag is sequentially formed on the back surface of the semiconductor chip 21, and when the Sn-based solder 18a is melted, the Sn-based solder is formed. 18a.

  Next, the semiconductor chip 21 is bonded to the die pad 12 by the Sn-based solder 18 that has been cooled and solidified. The electrode 23 on the surface of the semiconductor chip 21 and the inner lead 13 are electrically connected through a fine metal wire 25 made of, for example, a bonding wire. Then, the die pad 12, the inner lead 13, the bonding member 17, the semiconductor chip 21, the metal thin wire 25, and the like are sealed with a sealing resin 31 made of an epoxy resin or the like. As shown in FIG. 1, the sealed semiconductor device 1 forms a so-called flat type having a heat dissipation plate in which the exposed bottom surface of the die pad 12 and the bottom surface of the outer lead 14 are substantially flush with each other. .

  As described above, the semiconductor device 1 that is internally joined via the Sn-based solder 18, as shown in FIG. 4, is Sn-AgCu solder 45, which is Sn-3Ag-0.5Cu-based solder, for example, on a printed circuit board. It is externally connected to a wiring (not shown) of a mounting board 41 and fixed. This reflow temperature is about 240 ° C. with respect to the melting temperature (217 ° C. to 219 ° C.) of the SnAgCu solder 45.

  The semiconductor device 1 fixed to the mounting substrate 41 with the SnAgCu solder 45 has electrical characteristics before being fixed to the mounting substrate 41. Next, the semiconductor device 1 mounted on the mounting substrate 41 was subjected to a temperature cycle test. The temperature cycle test is the same as the case where a semiconductor device internally connected in the conventional Sn-Pb system is externally connected (that is, mounted) in the conventional Sn-Pb system. In the temperature cycle test, there is no abnormality in the electrical characteristics of the semiconductor device 1 and no other inconvenience is observed.

  That is, the semiconductor chip 21 does not crack when it is internally connected using the Sn-based solder 18 (18a). Even when the semiconductor device 1 is fixed to the mounting substrate 41 via the SnAgCu solder 45, the semiconductor chip 21 does not have a defect such as a crack, and the connection between the semiconductor chip 21 and the die pad 12 is disconnected. It shows that it will not be.

The reason why the semiconductor device 1 is strong against thermal shock during mounting and temperature cycling is the structure in which the periphery of the joining member 17 is composed of an intermetallic compound 19 and an Sn-based solder 18 is disposed therein. The intermetallic compound 19 is mainly composed of Cu ₃ Sn fixed to the die pad 12 and Cu ₆ Sn ₅ grown thereon, and has a melting point of 400 ° C. or higher and does not melt at the time of external connection. Even if the Sn-based solder 18 containing Sn as a main component is melted at the time of external connection, the intermetallic compound 19 can suppress the outflow of the Sn-based solder 18. As a result, the semiconductor chip 21 can maintain almost the same positional relationship with respect to the die pad 12.

  Further, the Sn-based solder 18 does not melt in a temperature cycle in which high temperature and low temperature are repeated. There are many differences in thermal expansion between the semiconductor chip 21 and the bonding member 17 and the die pad 12. Since the intermetallic compound 19 having a hard and brittle property is distributed around the back surface of the semiconductor chip 21, the intermetallic compound 19 is not firmly connected to the entire back surface, and the intermetallic compound 19 is made of Cu from the die pad 12 side. Since it is supplied and grows toward the semiconductor chip 21, the connection with the semiconductor chip 21 is relatively weak. On the other hand, the central portion of the back surface of the semiconductor chip 21 is joined with Sn solder 18. The Sn-based solder 18 is softer than the intermetallic compound 19, can relieve stress generated due to the difference in thermal expansion, and can suppress the occurrence of cracks in the semiconductor chip 21. As a result, the semiconductor device 1 of the present embodiment can be put to practical use by mounting the semiconductor chip 21 having a larger area as compared with the case where the entire back surface of the semiconductor chip is firmly connected via an intermetallic compound. It is.

  A semiconductor device according to Embodiment 2 of the present invention will be described with reference to FIGS. 1 and 4 to 6. FIG. 5 is a cross-sectional view schematically showing an enlarged connection portion by solder of the semiconductor device. FIG. 6 is a cross-sectional view schematically showing a state where solder is supplied in the process of manufacturing a semiconductor device. The lead frame material, that is, the material such as the die pad is different from that of the first embodiment. In the following, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different components will be described.

  The semiconductor device of the present embodiment is roughly similar to the semiconductor device 1 of the first embodiment shown in FIG. 1, but as shown in FIG. 5, the lead frame 51 is composed of 42 alloy 53, The difference is that the surface of the die pad 12 is covered with a Cu layer 55.

  As shown in FIGS. 5 and 6, the lead frame 51 constituting the die pad 12 and the like is based on an Fe—Ni alloy 42 alloy 53 containing 42 mass% of Ni, and a Cu layer 55 is formed on the surface of the 42 alloy 53. Only the required film thickness is plated, for example, 1 to 10 μm. The shape and the like of the lead frame 51 are the same as those of the lead frame 11 of the first embodiment.

  As shown in FIG. 5, the structure from the upper Cu layer 55 to the upper semiconductor chip 21 is the same as that of the first embodiment. Most of the Cu layer 55 adjacent to the side portion of the Ag layer 15 is used to form the intermetallic compound 19. In order to sufficiently form the intermetallic compound 19, it is possible to increase the thickness of the Cu layer 55.

  As shown in FIG. 6, the Ag layer 15 is formed on the die pad 12 of the lead frame 51 plated with the Cu layer 55 on which the semiconductor chip 21 having a side of about 5 mm square is placed, as in the first embodiment. The Sn-based solder 18a is formed so as to cover the Ag layer 15 and the Cu layer 55 adjacent to the side of the Ag layer 15 after plating. Thereafter, a semiconductor device is formed in the same manner as in the first embodiment.

  As described above, the semiconductor device of the present embodiment joined internally via the Sn-based solder 18 is externally connected and fixed as in the first embodiment, as shown in FIG.

  The semiconductor device of this embodiment has the same effect as that of the semiconductor device 1 because the structure of the bonding member 17 is the same as that of the semiconductor device 1 of the first embodiment. In addition, even in the lead frame of 42 alloy 53 that does not have Cu, by forming the Cu layer 55 in contact with the peripheral portion of the back surface of the semiconductor chip 21 so as to contact the Sn-based solder 18a, The Cu—Sn-based intermetallic compound 19 can be formed on the periphery of the bonding member 17 by a simple process. As a result, it is possible to provide a semiconductor device in which lead-free solder capable of suppressing the occurrence of cracks in the semiconductor chip 21 using the 42 alloy 53 is formed at low cost.

  The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

  For example, in the embodiments, a semiconductor device having a lead structure with a flat outer lead is shown. However, a so-called gull wing type, J lead type or the like in which a lead extending from a side portion of the sealing resin is bent may be used. In addition, the present invention can also be applied to a leadless type in which the outer lead does not protrude from the sealing resin.

  Further, in the embodiment, the example in which the back surface of the semiconductor chip is bonded to the die pad via the bonding member is shown. However, when the electrode on the surface of the semiconductor chip is flip-chip connected to the electrode on the internal substrate via the bump. Is also applicable. Although the size of the bump is small, a bonding member is used in which the peripheral portion is made of an intermetallic compound and the central portion is made of Sn-based solder for each bump.

  In the embodiment, the lead frame mainly composed of Cu and the lead frame made of 42 alloy material are shown. However, the present invention can be applied to lead frames made of other compositions. At that time, if Cu is sufficiently supplied from the die pad, as exemplified in Example 1, an Ag layer is plated on the lead frame by plating or the like, and the amount of Cu at the position corresponding to the central portion of the semiconductor chip is set. It is effective to adjust. Further, when Cu is not sufficiently supplied from the die pad, as exemplified in Example 2, it is attached by plating or the like so that a Cu layer is present at a position facing the periphery of the semiconductor chip on the lead frame, It is effective to adjust the amount of Cu.

  In the examples, an example in which an Ag layer is disposed in order to suppress the reaction between the Sn-based solder and the underlying Cu has been shown. However, as a material for suppressing the reaction, other than a metal layer mainly composed of Ag. For example, Ti, Cr, Ta, Ni, Pd, Au, TiN, TaN, or a laminated film, a mixture, a compound, or the like thereof can be used.

Sectional drawing which shows typically the semiconductor device which concerns on Example 1 of this invention. Sectional drawing which expands and shows typically the connection part by the solder of the semiconductor device which concerns on Example 1 of this invention. Sectional drawing which shows typically the state with which the solder was supplied in the process of manufacturing the semiconductor device which concerns on Example 1 of this invention. Sectional drawing which shows typically the state which mounted the semiconductor device which concerns on Example 1 of this invention on the mounting board | substrate. Sectional drawing which expands and shows typically the connection part by the solder of the semiconductor device which concerns on Example 2 of this invention. Sectional drawing which shows typically the state with which the solder was supplied in the process of manufacturing the semiconductor device which concerns on Example 2 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 11, 51 Lead frame 12 Die pad 13 Inner lead 14 Outer lead 15 Ag layer 17 Joining member 18, 18a Sn type solder 19 Intermetallic compound 21 Semiconductor chip 23 Electrode 25 Metal fine wire 27 High concentration Cu compound 28 Low concentration Cu compound 31 Sealing resin 41 Mounting substrate 45 SnAgCu solder 53 42 Alloy 55 Cu layer

Claims (5)

A semiconductor chip;
A metal member facing the back surface of the semiconductor chip;
An intermetallic compound containing Cu-Sn as a main component is disposed between a peripheral portion of the back surface of the semiconductor chip and the metal member, and any one of metals containing Sn and Sn as a main component is provided on the semiconductor chip. A bonding member disposed between a central portion of the back surface and the metal member, and bonding the metal member facing the back surface of the semiconductor chip;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the metal member is one of Cu and a metal containing Cu as a main component.   2. The semiconductor device according to claim 1, wherein a surface of a portion of the metal member facing the back surface of the semiconductor chip includes one of Cu and a metal mainly containing Cu.   The bonding member is characterized in that at least one of an Ag layer and a metal layer mainly composed of Ag is formed at an interface with the metal member facing the central portion of the back surface of the semiconductor chip. The semiconductor device according to claim 1.   The electrode on the surface of the semiconductor chip is connected to one outer lead via a thin metal wire, the metal member is connected to another outer lead, and the one and other outer leads are mounted on the mounting substrate by a molten lead-free material. The semiconductor device according to claim 1, wherein the semiconductor device is connected to the semiconductor device.

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