JP2008011120A - Semiconductor switch circuit - Google Patents

Abstract

To simplify a signal path of a semiconductor switch circuit.
A high-frequency switch 10 includes a control circuit 1, an SP6T (internal circuit unit) 2, an RF terminal P _{RF1 to} P _RF6 , a common RF terminal P _RFCOM , a control terminal P _{V1 to} P _V3 , and a high potential side power terminal P. _VDD , a low potential side power supply terminal P _VSS , and a ground terminal P _VS are provided. SP6T (internal circuit) 2, based on the switch control signal S11 to S16 are outputted from the control circuit 1 activates between any one of the RF terminal of the common RF terminal _{P RFCOM} and RF terminals _{P RF1} through _{P RF6} To propagate a radio frequency (RF) signal.
[Selection] Figure 1

Description

  The present invention relates to a switch, and more particularly to a switch circuit that switches a radio frequency (RF) signal and a switch circuit that switches an internal signal of a semiconductor integrated circuit.

  A radio frequency (RF) switch as a switch circuit is an important component of a wireless communication system such as a mobile communication or LAN field, and is used in a large number in a mobile phone, a wireless infrastructure facility, a satellite communication facility, or a cable TV facility. ing. In addition, a switch circuit that switches an internal signal generated by a semiconductor integrated circuit and outputs the signal to a logic circuit, a memory, or the like is used (for example, see Patent Document 1).

  In the RF switch described in Patent Document 1 or the like, for example, a multi-port RF switch such as SP6T or SP7T is used to switch RF signals of various standards having different frequencies as mobile communication progresses. . Then, control circuits that generate control signals, drivers, and the like are being built in. Further, with the progress of high integration and systemization of semiconductor integrated circuits, multi-port switches that switch internal signals are used.

However, the multi-port switch circuit has a problem in that the number of control signals for controlling switch switching increases, and the control circuit and driver such as a decoder circuit for generating control signals become complicated. Further, the wiring of the control signal becomes complicated, and there is a possibility that a malfunction occurs due to a timing shift.
International Publication Number WO2003 / 032431 Specification

  An object of the present invention is to provide a semiconductor switch circuit capable of simplifying a signal path.

  A semiconductor switch circuit according to an aspect of the present invention includes a through FET including an Nch insulated gate field effect transistor, a shunt FET including a Pch insulated gate field effect transistor having a gate connected to the gate of the through FET, When a switch control signal is output to the gates of the through FET and the shunt FET, and the signal level of the switch control signal is “High”, the through FET is turned “ON”, the shunt FET is turned “OFF”, and And a terminal for turning off the through FET and turning on the shunt FET when the signal level of the switch control signal is “Low”.

  Furthermore, a semiconductor switch circuit according to another aspect of the present invention is provided between a common terminal and a signal terminal, and is provided between a through FET composed of an Nch insulated gate field effect transistor and the common terminal and a ground terminal. A shunt FET composed of a Pch insulated gate field effect transistor whose gate is connected to the gate of the through FET, and a switch control signal is output to the gate of the through FET and the shunt FET, and the signal level of the switch control signal Is “High”, the shunt FET is turned “OFF”, the through FET is turned “ON” to activate between the common terminal and the signal terminal, and the signal level of the switch control signal is “Low”. In this case, the through FET is turned “OFF” and the shunt FET is turned “ON”. And a terminal for turning “OFF” between the common terminal and the signal terminal.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor switch circuit which can simplify a signal path | route can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a semiconductor switch circuit according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a high frequency switch, FIG. 2 is a diagram showing a relationship between RF terminals connected to a common RF terminal by a control signal, and FIG. 3 is a circuit diagram showing an internal circuit portion of the high frequency switch. In this embodiment, the number of control signals is reduced by using a Pch MOS transistor for the shunt FET.

As shown in FIG. 1, the high-frequency switch (SP6T Single Pole 6 Throw) 10 includes a control circuit 1, an SP6T (internal circuit unit) 2, RF terminals P _{RF1 to} P _RF6 , a common RF terminal P _RFCOM , and a control terminal P _V1. To P _V3 , a high-potential side power terminal P _VDD , a low-potential side power terminal P _VSS , and a ground terminal P _VS are provided.

The high-frequency switch (SP6T) 10 is used as, for example, an antenna switch for a mobile phone, and a common RF terminal (common terminal) P _RFCOM is electrically connected to a port on the antenna side, and RF terminals (signal terminals) P _{RF1 to} P _RF6. Is an analog switch that is electrically connected to a port of Tx (transmitter) or Rx (receiver) and switches a radio frequency (RF) signal that is an analog signal.

The control circuit 1 is composed of, for example, a decoder circuit, is provided between the control terminals P _{V1 to} P _V3 and the SP6T (internal circuit unit) 2, and externally receives control signals S _{V1 to} S _V through the control terminals P _{V1 to} P _{V3. V3} is input, and switch control signals S11 to S16 are output to SP6T (internal circuit unit) 2. Then, the high-potential-side power supply V _DD is supplied via the high-potential-side power supply terminal P _VDD, a low potential side power source V _SS is supplied through a low-potential power supply terminal P _VSS.

Here, the high potential power supply _{V DD} voltage is set to, for example, 2.5V, the low potential side power source _{V SS} voltage is set to, for example, -2.5 V. Control signals _{S V1} to _{S V,} for example "Low" level is set to the low potential side power supply _{V SS} voltage level -2.5 V, the "High" level is the high potential side power supply _{V DD} voltage level 2.5V Is set. Switch control signal S11 to S16, for example "Low" level is set to -2.5V the _{V SS} level, "High" level is set to 2.5V for _{V DD} level.

The SP6T (internal circuit unit) 2 is connected to the ground potential V _S via the ground terminal P _VS and is provided between the control circuit 1 and the RF terminals P _{RF1 to} P _RF6 and based on the switch control signals S11 to S16. The radio frequency (RF) signal is propagated by activating between any one of the common RF terminal P _RFCOM and the RF terminals P _{RF1 to} P _RF6 .

As shown in FIG. 2, when the control signals S _{V1 to} S _V3 are at the “Low” level, the switch control signal S11 is at the “High” level (see FIG. 2). The signals other than this signal are “Low” level), and the area between the common RF terminal P _RFCOM and the RF terminal P _RF1 is selected to be “active”. Next, when the control signal S _V1 is at “High” level and the control signals S _V2 and S _V3 are at “Low” level, the switch control signal S12 becomes “High” level (other than this signal becomes “Low” level) and the common RF Between the terminal P _RFCOM and the RF terminal P _RF2 is selected and becomes “active”.

Subsequently, when the control signal S _V2 is “High” level and the control signals S _V1 and S _V3 are “Low” level, the switch control signal S13 is “High” level (other than this signal is “Low” level) and the common RF Between the terminal P _RFCOM and the RF terminal P _RF3 is selected and becomes “active”. When the control signal S _V3 is “High” level and the control signals S _V1 and S _V2 are “Low” level, the switch control signal S14 becomes “High” level (other than this signal is “Low” level) and the common RF terminal Between P _RFCOM and RF terminal P _RF4 is selected and becomes “active”.

Next, when the control signals S _V1 and S _V2 are at the “High” level and the control signal S _V3 is at the “Low” level, the switch control signal S15 is at the “High” level (other than this signal is at the “Low” level), and the common RF between the terminals _{P RFCOM} and RF terminal _{P RF5} is selected and becomes "active". Subsequently, when the control signals S _V1 and S _V3 are at “High” level and the control signal S _V2 is at “Low” level, the switch control signal S16 becomes “High” level (other than this signal becomes “Low” level) and the common RF Between the terminal P _RFCOM and the RF terminal P _RF6 is selected and becomes “active”.

Here, the relationship between the signal levels of the control signals S _V1 and S _{V2 and} the signal levels of the switch control signals S11 to S16 is not necessarily limited to the combinations shown in FIG. Various combinations are possible by changing.

  As shown in FIG. 3, SP6T (internal circuit portion) 2 includes Nch MOS transistors NT1 to NT6 as through FETs, Pch MOS transistors PT1 to PT6 as shunt FETs, resistors R1 to R6, resistors R11 to R16, and A resistor R21 is provided.

Here, the high frequency switch (SP6T) 10 including the SP6T (internal circuit section) 2 is a semiconductor integrated circuit using a thin SOI (Silicon On Insulator) substrate. Note that an SOS (Silicon On Sapphire) substrate may be used instead of the SOI substrate. The MOS transistor is also called a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Here, the high-frequency switch (SP6T) 10 is configured by using a MOSFET, but a SiNxOy film obtained by thermally nitriding a silicon oxide film, a laminated film of a silicon nitride film (Si ₃ N ₄ ) / silicon oxide film, or a high dielectric A MISFET (Metal Insulator Semiconductor Field Effect Transistor) in which a body film (High-K gate insulating film) or the like becomes a gate insulating film may be used. MOSFETs and MISFETs are also called insulated gate field effect transistors.

The through FET serves to make “active” between the common RF terminal P _RFCOM and the RF terminal P _RF when it is “ON”. The shunt FET serves to set the RF terminal P _RF to the ground potential V _S when it is “ON” and to “OFF” the common RF terminal P _RFCOM and the RF terminal P _RF . The resistors R1 to R6 and the resistors R11 to R16 have a resistance value of, for example, 10 KΩ, and are provided for improving the effective breakdown voltage of the transistor when the power level of a high frequency (RF) signal is large. It is. An enhancement mode (also called E-type) transistor is used for the Nch MOS transistor as the through FET and the Pch MOS transistor as the shunt FET.

Resistor R21 is provided between the common RF terminal _{P RFCOM} and Nch MOS transistors NT1 to NT6 ground terminal _{P VS,} having a high resistance value.

Nch MOS transistor NT1 has a drain connected to a common RF terminal _{P RFCOM,} a source connected to the RF terminal _{P RF1,} the switch control signal S11 to the gate through a resistor R1 is inputted. Pch MOS transistor PT1 has a drain connected to the ground terminal _{P VS,} the source is connected to the RF terminal _{P RF1,} the switch control signal S11 to the gate through a resistor R11 is input.

Here, when the switch control signal S11 is at “High” level (2.5 V), the Nch MOS transistor NT1 as the through FET is “ON”, and the Pch MOS transistor PT1 as the shunt FET is “OFF”. Between the RF terminal P _RFCOM and the RF terminal P _RF1 is “active”. On the other hand, when the switch control signal S11 is at the “Low” level (−2.5 V), the Nch MOS transistor NT1 as the through FET is “OFF”, the Pch MOS transistor PT1 as the shunt FET is “ON”, and RF The terminal P _RF1 becomes the ground potential V _S , and the _portion between the common RF terminal P _RFCOM and the RF terminal P _RF1 is “OFF”.

Nch MOS transistor NT2 has a drain connected to a common RF terminal _{P RFCOM,} a source connected to the RF terminal _{P RF2,} the switch control signal S12 to the gate through a resistor R2 is input. Pch MOS transistor PT2 has a drain connected to the ground terminal _{P VS,} the source is connected to the RF terminal _{P RF2,} the switch control signal S12 to the gate through a resistor R12 is input.

Here, when the switch control signal S12 is at “High” level (2.5 V), the Nch MOS transistor NT2 as the through FET is “ON”, and the Pch MOS transistor PT2 as the shunt FET is “OFF”. Between the RF terminal P _RFCOM and the RF terminal P _RF2 is “active”. On the other hand, when the switch control signal S12 is at the “Low” level (−2.5V), the Nch MOS transistor NT2 as the through FET is “OFF”, the Pch MOS transistor PT2 as the shunt FET is “ON”, and RF The terminal P _RF2 becomes the ground potential V _S , and the area between the common RF terminal P _RFCOM and the RF terminal P _RF2 is “OFF”.

Nch MOS transistor NT3 has a drain connected to a common RF terminal _{P RFCOM,} a source connected to the RF terminal _{P RF3,} the switch control signal S13 to the gate via a resistor R3 is inputted. Pch MOS transistor PT3 has a drain connected to the ground terminal _{P VS,} the source is connected to the RF terminal _{P RF3,} the switch control signal S13 to the gate through a resistor R13 is input.

Here, when the switch control signal S13 is at “High” level (2.5 V), the Nch MOS transistor NT3 as the through FET is “ON”, and the Pch MOS transistor PT3 as the shunt FET is “OFF”. Between the RF terminal P _RFCOM and the RF terminal P _RF3 is “active”. On the other hand, when the switch control signal S13 is at the “Low” level (−2.5 V), the Nch MOS transistor NT3 as the through FET is “OFF”, the Pch MOS transistor PT3 as the shunt FET is “ON”, and RF The terminal P _RF3 becomes the ground potential V _S , and the _portion between the common RF terminal P _RFCOM and the RF terminal P _RF3 is “OFF”.

Nch MOS transistor NT4 has a drain connected to a common RF terminal _{P RFCOM,} a source connected to the RF terminal _{P RF4,} the switch control signal S14 to the gate through a resistor R4 is input. Pch MOS transistor PT4 has a drain connected to the ground terminal _{P VS,} the source is connected to the RF terminal _{P RF4,} the switch control signal S14 to the gate through a resistor R14 is input.

Here, when the switch control signal S14 is at “High” level (2.5 V), the Nch MOS transistor NT4 as the through FET is “ON” and the Pch MOS transistor PT4 as the shunt FET is “OFF”. Between the RF terminal P _RFCOM and the RF terminal P _RF4 is “active”. On the other hand, when the switch control signal S14 is at the “Low” level (−2.5 V), the Nch MOS transistor NT4 as the through FET is “OFF”, the Pch MOS transistor PT4 as the shunt FET is “ON”, and RF The terminal P _RF4 becomes the ground potential V _S , and the area between the common RF terminal P _RFCOM and the RF terminal P _RF4 is “OFF”.

Nch MOS transistor NT5 has a drain connected to a common RF terminal _{P RFCOM,} a source connected to the RF terminal _{P RF5,} the switch control signal S15 to the gate through a resistor R5 is input. Pch MOS transistor PT5 has a drain connected to the ground terminal _{P VS,} the source is connected to the RF terminal _{P RF5,} the switch control signal S15 to the gate through a resistor R15 is input.

Here, when the switch control signal S15 is at “High” level (2.5 V), the Nch MOS transistor NT5 as the through FET is “ON”, and the Pch MOS transistor PT5 as the shunt FET is “OFF”. between RF terminals _{P RFCOM} and RF terminal _{P RF5} is "active". On the other hand, when the switch control signal S15 is at the “Low” level (−2.5 V), the Nch MOS transistor NT5 as the through FET is “OFF”, the Pch MOS transistor PT5 as the shunt FET is “ON”, and RF terminal _{P RF5} the ground potential _{V S} becomes, the between the common RF terminal _{P RFCOM} and RF terminal _{P RF5} becomes "OFF".

In the Nch MOS transistor NT6, the drain is connected to the common RF terminal _PRFCOM , the source is connected to the RF terminal _PRF6 , and the switch control signal S16 is input to the gate through the resistor R6. Pch MOS transistors PT6, the drain is connected to the ground terminal _{P VS,} the source is connected to the RF terminal _{P RF6,} the switch control signal S16 to the gate through a resistor R16 is input.

Here, when the switch control signal S16 is at “High” level (2.5 V), the Nch MOS transistor NT6 as the through FET is “ON” and the Pch MOS transistor PT6 as the shunt FET is “OFF”. Between the RF terminal P _RFCOM and the RF terminal P _RF6 is “active”. On the other hand, when the switch control signal S16 is at the “Low” level (−2.5 V), the Nch MOS transistor NT6 as the through FET is “OFF”, the Pch MOS transistor PT6 as the shunt FET is “ON”, and RF The terminal P _RF6 becomes the ground potential V _S , and the area between the common RF terminal P _RFCOM and the RF terminal P _RF6 is “OFF”.

  Next, the configuration and operation of a conventional high-frequency switch will be described with reference to FIGS. 4 is a block diagram showing the configuration of a conventional high-frequency switch, FIG. 5 is a conventional high-frequency switch, showing the relationship between RF terminals connected to a common RF terminal by a control signal, and FIG. 6 is an internal view of the conventional high-frequency switch. It is a circuit diagram which shows a circuit part. In the conventional high frequency switch, the number of switch control signals input to the SP6T (internal circuit section) is twice as large as that of the present embodiment, for example.

As shown in FIG. 4, a conventional high-frequency switch (SP6T) 10a includes a control circuit 1a, SP6T (internal circuit portion) 2a, a driver 3, RF terminals P _{RF1 to} P _RF6 , a common RF terminal P _RFCOM , and a control terminal P. _{V1 to} P _V3 , a high potential side power supply terminal P _VDD , and a ground terminal P _VS are provided.

Control circuit 1a is composed of, for example, a decoder circuit, a control terminal _{P V1} through is provided between the _{P V3} and the driver 3, respectively input a control signal _{S V1} to _{S V3} from the outside through a control terminal _{P V1} to _{P V3} The switch control signals S11a to S16a are output to the driver 3. Then, the high potential side power supply V _DD is supplied through the high potential side power supply terminal _PVDD .

Here, the high potential side power supply V _DD voltage is set to 2.5 V, for example. Control signals _{S V1} to _{S V,} for example "Low" level is set to the ground potential _{V S} level 0 (zero) V, "High" level is set to 2.5V of the high potential power supply _{V DD} voltage level The Switch control signal S11a to S16a, for example "Low" level is set to _{V S} level 0 (zero) V, "High" level is set to 2.5V for _{V DD} level.

  The driver 3 is provided between the control circuit 1a and the SP6T (internal circuit unit) 2a, and receives switch control signals S11a to S16a (six switch control signals), a switch control signal S110, a switch control signal S111, and a switch Control signal S120, switch control signal S121, switch control signal S130, switch control signal S131, switch control signal S140, switch control signal S141, switch control signal S150, switch control signal S151, switch control signal S160, and switch control signal S161 ( 12 switch control signals) are output to the SP6T (internal circuit section) 2a.

Here, the switch control signals S110, S111, S120, S121, S130, S131, S140, S141, S150, S151, S160, and S161, for example "Low" level of the ground potential _{V S} level 0 (zero) V The “High” level is set to the high potential side power supply _VDD voltage level of 2.5V. Switch control signals S110 and S111, switch control signals S120 and S121, switch control signals S130 and S131, switch control signals S140 and S141, switch control signals S150 and S151, and switch control signals S160 and S161 each have a pair of signal levels. Have.

  For example, when the switch control signal S110 is at the “High” level (2.5 V), the switch control signal S111 is set at the “Low” level (0 (zero) V). When S110 is at “Low” level (0 (zero) V), the switch control signal S111 is set to “High” level (2.5 V). In order to generate a paired signal level, the signal is inverted using, for example, an inverter.

The SP6T (internal circuit unit) 2a is connected to the ground potential V _S via the ground terminal P _VS and is provided between the driver 3 and the RF terminals P _{RF1 to} P _RF6 , and the switch control signals S110, S111, S120, S121. , S130, S131, S140, S141, S150, S151, S160, and S161, and activates the RF terminal between any one of the common RF terminal P _RFCOM and the RF terminals P _{RF1 to} P _{RF6 to generate} a high frequency (RF) signal. Propagate the signal.

As shown in FIG. 5, first, when the control signals S _{V1 to} S _V3 are at the “Low” level, the switch control signal S111 is at the “High” level. The switch control signal S110 becomes “Low” level (the signal level is different except for this signal pair), and the common RF terminal P _RFCOM and the RF terminal P _RF1 are selected and become “active”. Next, when the control signal S _V1 is at the “High” level and the control signals S _V2 and S _V3 are at the “Low” level, the switch control signal S121 is at the “High” level and the switch control signal S120 is at the “Low” level (this signal The signal levels are different except for the pair), and the area between the common RF terminal P _RFCOM and the RF terminal P _RF2 is selected to be “active”.

Subsequently, when the control signal S _V2 is “High” level and the control signals S _V1 and S _V3 are “Low” level, the switch control signal S131 is “High” level and the switch control signal S130 is “Low” level (this signal). The signal level is different except for the pair), and the area between the common RF terminal P _RFCOM and the RF terminal P _RF3 is selected to be “active”. When the control signal S _V3 is at the “High” level and the control signals S _V1 and S _V2 are at the “Low” level, the switch control signal S141 is at the “High” level and the switch control signal S140 is at the “Low” level. The signal levels are different from each other), and the area between the common RF terminal P _RFCOM and the RF terminal P _RF4 is selected and becomes “active”.

Next, when the control signals S _V1 and S _V2 are at “High” level and the control signal S _V3 is at “Low” level, the switch control signal S151 is at “High” level and the switch control signal S150 is at “Low” level (this signal pair except that the signal level varies) between next common RF terminal _{P RFCOM} and RF terminal _{P RF5} is selected and becomes "active". Subsequently, when the control signals S _V1 and S _V3 are “High” level and the control signal S _V2 is “Low” level, the switch control signal S161 is “High” level and the switch control signal S160 is “Low” level (this signal The signal levels are different except for the pair), and the area between the common RF terminal P _RFCOM and the RF terminal P _RF6 is selected to be “active”.

  As shown in FIG. 6, the SP6T (internal circuit portion) 2a includes Nch MOS transistors NT1 to NT6 as through FETs, Nch MOS transistors NT11 to NT16 as shunt FETs, resistors R1 to R6, resistors R31 to R36, and A resistor R21 is provided.

Resistor R21 is provided between the common RF terminal _{P RFCOM} and Nch MOS transistors NT1 to NT6 ground terminal _{P VS,} having a high resistance value.

Nch MOS transistor NT1 has a drain connected to a common RF terminal _{P RFCOM,} a source connected to the RF terminal _{P RF1,} the switch control signal S111 to the gate through a resistor R1 is inputted. Nch MOS transistor NT11 has a source connected to the ground terminal _{P VS,} the drain is connected to the RF terminal _{P RF1,} the switch control signal S110 is input to the gate through a resistor R31.

Here, when the switch control signal S111 is at the “High” level (2.5V) and the switch control signal S110 is at the “Low” level (0 (zero) V), the Nch MOS transistor NT1 as the through FET is “ON”. Then, the Nch MOS transistor NT11 as the shunt FET is turned “OFF”, and the area between the common RF terminal P _RFCOM and the RF terminal P _RF1 becomes “active”. On the other hand, when the switch control signal S111 is at the “Low” level (0 (zero) V) and the switch control signal S110 is at the “High” level (2.5 V), the Nch MOS transistor NT1 as the through FET is turned “OFF”. The Nch MOS transistor NT11 as the shunt FET is turned “ON”, the RF terminal P _RF1 becomes the ground potential V _S , and the common RF terminal P _RFCOM and the RF terminal P _RF1 are turned “OFF”.

Nch MOS transistor NT2 has a drain connected to a common RF terminal _{P RFCOM,} a source connected to the RF terminal _{P RF2,} the switch control signal S121 to the gate through a resistor R1 is inputted. Nch MOS transistor NT12 has a source connected to the ground terminal _{P VS,} the drain is connected to the RF terminal _{P RF2,} the switch control signal S120 is input to the gate through a resistor R32.

Here, when the switch control signal S121 is at "High" level (2.5V) and the switch control signal S120 is at "Low" level (0 (zero) V), the Nch MOS transistor NT2 as the through FET is "ON". Then, the Nch MOS transistor NT12 as the shunt FET is turned “OFF”, and the area between the common RF terminal P _RFCOM and the RF terminal P _RF2 becomes “active”. On the other hand, when the switch control signal S121 is “Low” level (0 (zero) V) and the switch control signal S120 is “High” level (2.5 V), the Nch MOS transistor NT2 as the through FET is turned “OFF”. Then, the Nch MOS transistor NT12 as the shunt FET is turned “ON”, the RF terminal P _RF2 becomes the ground potential V _S , and the common RF terminal P _RFCOM and the RF terminal P _RF2 are turned “OFF”.

Nch MOS transistor NT3 has a drain connected to a common RF terminal _{P RFCOM,} a source connected to the RF terminal _{P RF3,} the switch control signal S131 to the gate via a resistor R3 is inputted. Nch MOS transistor NT13 has a source connected to the ground terminal _{P VS,} the drain is connected to the RF terminal _{P RF3,} the switch control signal S130 is input to the gate through a resistor R33.

Here, when the switch control signal S131 is at "High" level (2.5V) and the switch control signal S130 is at "Low" level (0 (zero) V), the Nch MOS transistor NT3 as the through FET is "ON". Then, the Nch MOS transistor NT13 as the shunt FET is “OFF”, and the area between the common RF terminal P _RFCOM and the RF terminal P _RF3 becomes “active”. On the other hand, when the switch control signal S131 is “Low” level (0 (zero) V) and the switch control signal S130 is “High” level (2.5 V), the Nch MOS transistor NT3 as the through FET is turned “OFF”. The Nch MOS transistor NT13 as the shunt FET is turned “ON”, the RF terminal P _RF3 becomes the ground potential V _S , and the common RF terminal P _RFCOM and the RF terminal P _RF3 are turned “OFF”.

Nch MOS transistor NT4 has a drain connected to a common RF terminal _{P RFCOM,} a source connected to the RF terminal _{P RF4,} the switch control signal S141 to the gate through a resistor R4 is input. Nch MOS transistor NT14 has a source connected to the ground terminal _{P VS,} the drain is connected to the RF terminal _{P RF4,} the switch control signal S140 is input to the gate through a resistor R34.

When the switch control signal S141 is “High” level (2.5V) and the switch control signal S140 is “Low” level (0 (zero) V), the Nch MOS transistor NT4 as the through FET is “ON”. Then, the Nch MOS transistor NT14 as the shunt FET is turned “OFF”, and the area between the common RF terminal P _RFCOM and the RF terminal P _RF4 becomes “active”. On the other hand, when the switch control signal S141 is “Low” level (0 (zero) V) and the switch control signal S140 is “High” level (2.5 V), the Nch MOS transistor NT4 as the through FET is turned “OFF”. Then, the Nch MOS transistor NT14 as the shunt FET is turned “ON”, the RF terminal P _RF4 becomes the ground potential V _S , and the common RF terminal P _RFCOM and the RF terminal P _RF4 are turned “OFF”.

Nch MOS transistor NT5 has a drain connected to a common RF terminal _{P RFCOM,} a source connected to the RF terminal _{P RF5,} the switch control signal S151 is input to the gate through a resistor R5. Nch MOS transistor NT15 has a source connected to the ground terminal _{P VS,} the drain is connected to the RF terminal _{P RF5,} the switch control signal S150 is input to the gate through a resistor R35.

Here, when the switch control signal S151 is “High” level (2.5 V) and the switch control signal S150 is “Low” level (0 (zero) V), the Nch MOS transistor NT5 as the through FET is “ON”. and, and Nch MOS transistor NT15 is "OFF" as a shunt FET, while the common RF terminal _{P RFCOM} and RF terminal _{P RF5} is "active". On the other hand, when the switch control signal S151 is at the “Low” level (0 (zero) V) and the switch control signal S150 is at the “High” level (2.5 V), the Nch MOS transistor NT5 as the through FET is “OFF”. , and Nch MOS transistor NT15 is "ON" as a shunt FET, RF terminals _{P RF5} the ground potential _{V S} becomes, the between the common RF terminal _{P RFCOM} and RF terminal _{P RF5} becomes "OFF".

In the Nch MOS transistor NT6, the drain is connected to the common RF terminal _PRFCOM , the source is connected to the RF terminal _PRF6 , and the switch control signal S161 is input to the gate through the resistor R6. Nch MOS transistor NT16 has a source connected to the ground terminal _{P VS,} the drain is connected to the RF terminal _{P RF6,} the switch control signal S160 is input to the gate through a resistor R36.

Here, when the switch control signal S161 is at “High” level (2.5 V) and the switch control signal S160 is at “Low” level (0 (zero) V), the Nch MOS transistor NT6 as the through FET is “ON”. Then, the Nch MOS transistor NT16 as the shunt FET is turned “OFF”, and the area between the common RF terminal P _RFCOM and the RF terminal P _RF6 becomes “active”. On the other hand, when the switch control signal S161 is at the “Low” level (0 (zero) V) and the switch control signal S160 is at the “High” level (2.5 V), the Nch MOS transistor NT6 as the through FET is “OFF”. Then, the Nch MOS transistor NT16 as the shunt FET is turned “ON”, the RF terminal P _RF6 is set to the ground potential V _S , and the common RF terminal P _RFCOM and the RF terminal P _RF6 are turned “OFF”.

As described above, in the semiconductor switch circuit of this embodiment, the control circuit 1, the SP6T (internal circuit portion) 2, the RF terminals P _{RF1 to} P _RF6 , the common RF terminal P _RFCOM , the control terminals P _{V1 to} P _V3 , the high potential A side power terminal P _VDD , a low potential side power terminal P _VSS , and a ground terminal P _VS are provided. The control circuit 1 receives control signals S _{V1 to} S _V3 from outside via control terminals P _{V1 to} P _V3, and outputs switch control signals S11 to S16 to the SP6T (internal circuit unit) 2. SP6T (internal circuit) 2, based on the switch control signal S11 to S16 are outputted from the control circuit 1 activates between any one of the RF terminal of the common RF terminal _{P RFCOM} and RF terminals _{P RF1} through _{P RF6} To propagate a radio frequency (RF) signal. An Nch MOS transistor is used for the through FET, and a Pch MOS transistor is used for the shunt FET.

  For this reason, the number of switch control signals for controlling switch switching can be suppressed as compared with the conventional case, and the configuration of the control circuit for generating the switch control signals can be simplified. In addition, when one through control FET turns on the through FET, the paired shunt FETs turn off simultaneously. By one switch control signal, when the through FET is “OFF”, the paired shunt FETs are simultaneously “ON”. Therefore, there is no possibility of malfunction due to timing shift.

In this embodiment, the “High” level of the control signals S _{V1 to} S _V3 and the switch control signals S11 to S16 is set to be the same as the high potential side power supply V _DD voltage (2.5 V), and the control signals S _{V1 to} While the "low" level of the S _V3 and the switch control signal S11 to S16 are the low potential side power source _{V SS} voltage and the same set (-2.5 V), the control signal _{S V1} to _{S V3} and the switch control signals S11 to the "high" level in S16 is set lower than the high potential side power supply _{V DD,} the control signals _{S V1} to _{S V3} and the switch control signals S11 to S16 "low" level of the absolute value of the low potential side power source _{V SS} voltage It may be set lower than the absolute value. Moreover, although SOI is used for the substrate on which the high frequency switch (SP6T) 10 is formed, a silicon substrate may be used instead of the SOI substrate. In that case, a resistor having a high resistance value between the back gate and the ground potential V _S of the through FET provided, to dispose a resistor having a high resistance value between the backgate and the high potential side power supply V _DD of the shunt FET preferable.

  Next, a semiconductor switch circuit according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a circuit diagram showing an internal circuit portion of the high frequency switch. In this embodiment, the shunt FET and the through FET have a two-stage configuration in parallel.

As shown in FIG. 7, the SP6T (internal circuit portion) 2b includes Nch MOS transistors NT1A to NT6A as through FETs, Nch MOS transistors NT1B to NT6B as through FETs, Pch MOS transistors PT1A to PT6A as shunt FETs, Pch MOS transistors PT1B to PT6B as shunt FETs, resistors R1A to R6A, resistors R1B to R6B, resistors R11A to R16A, resistors R11B to R16B, and a resistor R21 are provided. Resistor R21 is provided between the common RF terminals _{P RFCOM} and Nch MOS transistor NT1B to NT6B and the ground terminal _{P VS,} having a high resistance value. Note that the high frequency switch including the SP6T (internal circuit portion) 2b uses a silicon substrate.

  Here, the resistors R1A to R6A, the resistors R1B to R6B, the resistors R11A to R16A, and the resistors R11B to R16B have a resistance value of, for example, 10 KΩ, and the transistor is effective when the power level of the high frequency (RF) signal is large. This is provided in order to improve the breakdown voltage.

The Nch MOS transistor NT1B has a drain connected to the common RF terminal P _RFCOM , a source connected to the back gate and the drain of the Nch MOS transistor NT1A, and the switch control signal S11 is input to the gate through the resistor R1B. Nch MOS transistor NT1A has a drain connected to the back gate, a source connected to the RF terminal _{P RF1,} the switch control signal S11 to the gate via a resistor R1A is input. Pch MOS transistor PT1A has a source connected to the RF terminal _{P RF1,} a drain connected to the source of the back gate and the Pch MOS transistor PT1B, the switch control signal S11 is input to the gate through a resistor R11A. Pch MOS transistor PT1B has a source connected to the back gate, a drain connected to the ground terminal _{P VS,} switch control signal S11 is input to the gate via a resistor R11B.

Here, when the switch control signal S11 is at “High” level (2.5 V), the Nch MOS transistors NT1A and NT1B as through FETs are “ON”, and the Pch MOS transistors PT1A and PT1B as shunt FETs are “OFF”. Thus, the common RF terminal P _RFCOM and the RF terminal P _RF1 are “active”. On the other hand, when the switch control signal S11 is at the “Low” level (−2.5V), the Nch MOS transistors NT1A and NT1B as the through FET are “OFF”, and the Pch MOS transistors PT1A and PT1B as the shunt FET are “ON”. Then, the RF terminal P _RF1 becomes the ground potential V _S , and the area between the common RF terminal P _RFCOM and the RF terminal P _RF1 is “OFF”.

The Nch MOS transistor NT2B has a drain connected to the common RF terminal _PRFCOM , a source connected to the back gate and the drain of the Nch MOS transistor NT2A, and the switch control signal S12 is input to the gate through the resistor R2B. Nch MOS transistor NT2A has a drain connected to the back gate, a source connected to the RF terminal _{P RF2,} the switch control signal S12 to the gate through a resistor R2A is input. Pch MOS transistor PT2A has a source connected to the RF terminal _{P RF2,} a drain connected to the source of the back gate and the Pch MOS transistor PT2b, the switch control signal S12 is input to the gate through a resistor R12A. Pch MOS transistor PT2B has a source connected to the back gate, a drain connected to the ground terminal _{P VS,} switch control signal S12 is input to the gate via a resistor R12B.

Here, when the switch control signal S12 is at “High” level (2.5V), the Nch MOS transistors NT2A and NT2B as through FETs are “ON”, and the Pch MOS transistors PT2A and PT2B as shunt FETs are “OFF”. Thus, the portion between the common RF terminal P _RFCOM and the RF terminal P _RF2 becomes “active”. On the other hand, when the switch control signal S12 is at the “Low” level (−2.5 V), the Nch MOS transistors NT2A and NT2B as the through FET are “OFF”, and the Pch MOS transistors PT2A and PT2B as the shunt FET are “ON”. Then, the RF terminal P _RF2 becomes the ground potential V _S , and the area between the common RF terminal P _RFCOM and the RF terminal P _RF2 is “OFF”.

In the Nch MOS transistor NT3B, the drain is connected to the common RF terminal P _RFCOM , the source is connected to the back gate and the drain of the Nch MOS transistor NT3A, and the switch control signal S13 is input to the gate through the resistor R3B. Nch MOS transistor NT3A has a drain connected to the back gate, a source connected to the RF terminal _{P RF3,} the switch control signal S13 to the gate through a resistor R3A is input. Pch MOS transistor PT3A has a source connected to the RF terminal _{P RF3,} a drain connected to the source of the back gate and the Pch MOS transistor pT3b, the switch control signal S13 is input to the gate through a resistor R13A. Pch MOS transistor PT3B has a source connected to the back gate, a drain connected to the ground terminal _{P VS,} switch control signal S13 is input to the gate through a resistor R13b.

Here, when the switch control signal S13 is at “High” level (2.5 V), the Nch MOS transistors NT3A and NT3B as through FETs are “ON”, and the Pch MOS transistors PT3A and PT3B as shunt FETs are “OFF”. Thus, the common RF terminal P _RFCOM and the RF terminal P _RF3 are “active”. On the other hand, when the switch control signal S13 is at the “Low” level (−2.5V), the Nch MOS transistors NT3A and NT3B as the through FET are “OFF”, and the Pch MOS transistors PT3A and PT3B as the shunt FET are “ON”. Then, the RF terminal P _RF3 becomes the ground potential V _S , and the area between the common RF terminal P _RFCOM and the RF terminal P _RF3 is “OFF”.

The Nch MOS transistor NT4B has a drain connected to the common RF terminal P _RFCOM , a source connected to the back gate and the drain of the Nch MOS transistor NT4A, and a switch control signal S14 input to the gate via the resistor R4B. Nch MOS transistor NT4A has a drain connected to the back gate, a source connected to the RF terminal _{P RF4,} the switch control signal S14 to the gate through a resistor R4A is input. Pch MOS transistor PT4A has a source connected to the RF terminal _{P RF4,} a drain connected to the source of the back gate and the Pch MOS transistor PT4B, the switch control signal S14 is input to the gate through a resistor R14A. Pch MOS transistor PT4B has a source connected to the back gate, a drain connected to the ground terminal _{P VS,} the switch control signal S14 is input to the gate through a resistor R14b.

Here, when the switch control signal S14 is at “High” level (2.5 V), the Nch MOS transistors NT4A and NT4B as through FETs are “ON”, and the Pch MOS transistors PT4A and PT4B as shunt FETs are “OFF”. Thus, the common RF terminal P _RFCOM and the RF terminal P _RF4 are “active”. On the other hand, when the switch control signal S14 is at the “Low” level (−2.5 V), the Nch MOS transistors NT4A and NT4B as the through FET are “OFF” and the Pch MOS transistors PT4A and PT4B as the shunt FET are “ON”. Then, the RF terminal P _RF4 becomes the ground potential V _S , and the area between the common RF terminal P _RFCOM and the RF terminal P _RF4 is “OFF”.

The Nch MOS transistor NT5B has a drain connected to the common RF terminal _PRFCOM , a source connected to the back gate and the drain of the Nch MOS transistor NT5A, and a switch control signal S15 input to the gate via the resistor R5B. Nch MOS transistor NT5A has a drain connected to the back gate, a source connected to the RF terminal _{P RF5,} the switch control signal S15 to the gate through a resistor R5A is input. Pch MOS transistor PT5A has a source connected to the RF terminal _{P RF5,} a drain connected to the source of the back gate and the Pch MOS transistor PT5B, the switch control signal S15 is input to the gate through a resistor R15A. Pch MOS transistor PT5B has a source connected to the back gate, a drain connected to the ground terminal _{P VS,} switch control signal S15 is input to the gate via a resistor R15B.

Here, when the switch control signal S15 is at “High” level (2.5 V), the Nch MOS transistors NT5A and NT5B as through FETs are “ON”, and the Pch MOS transistors PT5A and PT5B as shunt FETs are “OFF”. and, during the common RF terminal _{P RFCOM} and RF terminal _{P RF5} is "active". On the other hand, when the switch control signal S15 is at the “Low” level (−2.5 V), the Nch MOS transistors NT5A and NT5B as the through FET are “OFF”, and the Pch MOS transistors PT5A and PT5B as the shunt FET are “ON”. to, RF terminals _{P RF5} the ground potential _{V S} becomes, the between the common RF terminal _{P RFCOM} and RF terminal _{P RF5} becomes "OFF".

In the Nch MOS transistor NT6B, the drain is connected to the common RF terminal P _RFCOM , the source is connected to the back gate and the drain of the Nch MOS transistor NT6A, and the switch control signal S16 is input to the gate through the resistor R6B. In the Nch MOS transistor NT6A, the drain is connected to the back gate, the source is connected to the RF terminal _PRF6 , and the switch control signal S16 is input to the gate through the resistor R6A. In the Pch MOS transistor PT6A, the source is connected to the RF terminal _PRF6 , the drain is connected to the back gate and the source of the Pch MOS transistor PT6B, and the switch control signal S16 is input to the gate through the resistor R16A. Pch MOS transistor PT6B has a source connected to the back gate, a drain connected to the ground terminal _{P VS,} switch control signal S16 is input to the gate via a resistor R16B.

Here, when the switch control signal S16 is at “High” level (2.5 V), the Nch MOS transistors NT6A and NT6B as through FETs are “ON”, and the Pch MOS transistors PT6A and PT6B as shunt FETs are “OFF”. _Thus , the portion between the common RF terminal P _RFCOM and the RF terminal P _RF6 becomes “active”. On the other hand, when the switch control signal S16 is at the “Low” level (−2.5 V), the Nch MOS transistors NT6A and NT6B as the through FET are “OFF”, and the Pch MOS transistors PT6A and PT6B as the shunt FET are “ON”. Then, the RF terminal P _RF6 becomes the ground potential V _S , and the area between the common RF terminal P _RFCOM and the RF terminal P _RF6 is “OFF”.

As described above, the semiconductor switching circuit of this embodiment, SP6T (internal circuit) 2b, based on the switch control signal S11 to S16 are outputted from the control circuit, _RF1 through a common RF terminal _{P RFCOM} and RF terminals _P A radio frequency (RF) signal is propagated by activating between any one of RF terminals of P _RF6 . The SP6T (internal circuit section) 2b is provided with two shunt FETs arranged in parallel with two pairs of parallel arranged through FETs, and each gate is provided with a resistor having a high resistance value. . An Nch MOS transistor is used for the through FET, and a Pch MOS transistor is used for the shunt FET.

  For this reason, the number of switch control signals for controlling switch switching can be suppressed as compared with the conventional case, and the configuration of the control circuit for generating the switch control signals can be simplified. In addition, when one through control FET turns on the through FET, the paired shunt FETs turn off simultaneously. By one switch control signal, when the through FET is “OFF”, the paired shunt FETs are simultaneously “ON”. Therefore, there is no possibility of malfunction due to timing shift. Furthermore, since the resistors having high resistance values are provided at the gates of the two through FETs and the shunt FET arranged in parallel, the transistor when the power level of the radio frequency (RF) signal is larger than that of the first embodiment. The effective breakdown voltage can be suppressed from decreasing.

  In this embodiment, the silicon substrate is used for the high-frequency switch including the SP6T (internal circuit portion) 2b. However, an SOI substrate or an SOS substrate may be used. In the case of an SOI substrate or SOS substrate, it is preferable to use partially depleted or non-depleted type transistors for the through FET and shunt FET in the high-frequency analog switch.

  Next, a semiconductor switch circuit according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 8 is a circuit diagram showing an internal circuit portion of the high frequency switch. In this embodiment, the shunt FET and the through FET have a parallel three-stage configuration.

As shown in FIG. 8, the SPDT (internal circuit portion) 2c includes Nch MOS transistors NT1a to NT1c as through FETs, Nch MOS transistors NT2a to NT2c as through FETs, Pch MOS transistors PT1a to PT1c as shunt FETs, Pch MOS transistors PT2a to PT2c as shunt FETs, resistors R1a to R1c, resistors R2a to R2c, resistors R11a to R11c, resistors R12a to R12c, resistors Rb1a to Rb1c, resistors Rb2a to Rb2c, resistors Rb11a to Rb11c, resistors Rb12a to Rb12c , And a resistor R21. Resistor R21 is provided between the common RF terminal _{P RFCOM} and the ground terminal _{P VS,} having a high resistance value.

  Here, the resistors Rb1a to Rb1c, the resistors Rb2a to Rb2c, the resistors Rb11a to Rb11c, and the resistors Rb12a to Rb12c are provided to suppress a decrease in high frequency (RF) characteristics of the SPDT switch, and have a high resistance value. It is preferable to use a resistor having The resistors R1a to R1c, resistors R2a to R2c, resistors R11a to R11c, and resistors R12a to R12c have a resistance value of, for example, 10 KΩ, and are provided to improve the effective breakdown voltage and ESD of the transistor. It is. The high frequency switch including the SPDT (internal circuit portion) 2c uses a silicon substrate.

The Nch MOS transistor NT1c has a drain connected to the common RF terminal _PRFCOM , a source connected to the drain of the Nch MOS transistor NT1b, a resistor Rb1c provided between the back gate and the ground potential V _S , via the resistor R1c. A switch control signal S11 is input to the gate. Nch MOS transistor NT1b has a source connected to the drain of the Nch MOS transistor NT1a, resistance Rb1b is provided between the back gate ground potential _{V S,} the switch control signal S11 is input to the gate through a resistor R1b. Nch MOS transistor NT1a has a source connected to the RF terminal _{P RF1,} resistance Rb1a is provided between the back gate ground potential _{V S,} the switch control signal S11 is input to the gate through a resistor R1a.

Pch MOS transistor PT1a has a source connected to the RF terminal _{P RF1,} a drain connected to the source of the Pch MOS transistor PT1b, resistance Rb11a is provided between the back gate and the high potential side power supply _{V DD,} via a resistor R11a The switch control signal S11 is input to the gate. The Pch MOS transistor PT1b has a drain connected to the source of the Pch MOS transistor PT1c, a resistor Rb11b is provided between the back gate and the high potential side power supply V _DD , and a switch control signal S11 is input to the gate via the resistor R11b. The Pch MOS transistor PT1c has a drain connected to the ground terminal _{P VS,} resistance Rb11c is provided between the back gate and the high potential side power supply _{V DD,} the switch control signal S11 is input to the gate through a resistor R11c.

Here, when the switch control signal S11 is at “High” level (2.5 V), the Nch MOS transistors NT1a to NT1c as through FETs are “ON”, and the Pch MOS transistors PT1a to PT1c as shunt FETs are “OFF”. Thus, the common RF terminal P _RFCOM and the RF terminal P _RF1 are “active”. On the other hand, when the switch control signal S11 is at “Low” level (−2.5 V), the Nch MOS transistors NT1a to NT1c as through FETs are “OFF”, and the Pch MOS transistors PT1a to PT1c as shunt FETs are “ON”. Then, the RF terminal P _RF1 becomes the ground potential V _S , and the area between the common RF terminal P _RFCOM and the RF terminal P _RF1 is “OFF”.

The Nch MOS transistor NT2c has a drain connected to the common RF terminal _PRFCOM , a source connected to the drain of the Nch MOS transistor NT2b, a resistor Rb2c provided between the back gate and the ground potential V _S , via the resistor R2c. A switch control signal S12 is input to the gate. Nch MOS transistor NT2b has a source connected to the drain of the Nch MOS transistor NT2a, resistance Rb2b is provided between the back gate ground potential _{V S,} the switch control signal S12 is input to the gate through a resistor R2b. Nch MOS transistor NT2a has a source connected to the RF terminal _{P RF2,} resistance Rb2a is provided between the back gate ground potential _{V S,} the switch control signal S12 is input to the gate via a resistor R2a.

Pch MOS transistor PT2a has a source connected to the RF terminal _{P RF2,} a drain connected to the source of the Pch MOS transistor PT2b, resistance Rb12a is provided between the back gate and the high potential side power supply _{V DD,} via a resistor R12a The switch control signal S12 is input to the gate. The Pch MOS transistor PT2b has a drain connected to the source of the Pch MOS transistor PT2c, a resistor Rb12b is provided between the back gate and the high potential side power supply _VDD , and a switch control signal S12 is input to the gate through the resistor R12b. The Pch MOS transistor PT2c has a drain connected to the ground terminal _{P VS,} resistance Rb12c is provided between the back gate and the high potential side power supply _{V DD,} the switch control signal S12 is input to the gate through a resistor R12c.

Here, when the switch control signal S12 is at “High” level (2.5V), the Nch MOS transistors NT2a to NT2c as through FETs are “ON”, and the Pch MOS transistors PT2a to PT2c as shunt FETs are “OFF”. Thus, the portion between the common RF terminal P _RFCOM and the RF terminal P _RF2 becomes “active”. On the other hand, when the switch control signal S12 is at the “Low” level (−2.5 V), the Nch MOS transistors NT2a to NT2c as through FETs are “OFF”, and the Pch MOS transistors PT2a to PT2c as shunt FETs are “ON”. Then, the RF terminal P _RF2 becomes the ground potential V _S , and the area between the common RF terminal P _RFCOM and the RF terminal P _RF2 is “OFF”.

As described above, the semiconductor switching circuit of this embodiment, SPDT (internal circuit) 2c, based on the switch control signals S11 and S12 output from the control circuit, the common RF terminal _{P RFCOM} and RF terminals _{P RF1} and A radio frequency (RF) signal is propagated by activating between any one of RF terminals of _RF2 . An Nch MOS transistor is used for the through FET, and a Pch MOS transistor is used for the shunt FET. The SPDT (internal circuit unit) 2c is provided with three shunt FETs arranged in parallel with a pair of parallel arranged through FETs, and each gate is provided with a resistor having a high resistance value. . Resistor is provided having a high resistance value between the back gate and the ground potential V _S of the through FET. A resistor having a high resistance value is provided between the back gate of the shunt FET and the high potential side power source V _DD .

  For this reason, the number of switch control signals for controlling switch switching can be suppressed as compared with the conventional case, and the configuration of the control circuit for generating the switch control signals can be simplified. In addition, when one through control FET turns on the through FET, the paired shunt FETs turn off simultaneously. By one switch control signal, when the through FET is “OFF”, the paired shunt FETs are simultaneously “ON”. Therefore, there is no possibility of malfunction due to timing shift. Further, since the resistors having high resistance values are provided at the gates of the three through FETs and the shunt FETs arranged in parallel, the transistor when the power level of the radio frequency (RF) signal is larger than that of the first embodiment. The effective breakdown voltage can be suppressed from decreasing.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in the embodiment, the present invention is applied to a high-frequency analog switch, but can be applied to a switch for switching an internal digital signal generated in a semiconductor integrated circuit. In the first and second embodiments, the SP6T switch circuit is used. In the third embodiment, the SPDT switch circuit is used. However, the present invention is not limited to this. SPnT (one pole and nth throw) ) And mPnT (m poles and n throws) switch circuits. In the third embodiment, three through FETs and three shunt FETs are formed in parallel, but four or more may be formed in parallel.

The present invention can be configured as described in the following supplementary notes.
(Supplementary note 1) n (where n is an integer of 2 or more) parallel provided between the common terminal and the signal terminal, the gate is connected to the first resistor, and the Nth insulated gate field effect transistor N FETs are arranged in parallel between the common terminal and the ground terminal, the gate is connected to a second resistor, and the gate is connected to the through FET through the second resistor and the second resistor. A shunt FET group composed of Pch insulated gate field effect transistors, a gate of the through FET group via the first resistor, and a gate of the shunt FET group via the second resistor. When the switch control signal is output and the signal level of the switch control signal is “High”, the shunt FET group is turned “OFF” and the through FET group is turned “ON”. When the signal level of the switch control signal is “Low” between the common terminal and the signal terminal, the through FET group is turned off, and the shunt FET group is turned on. A semiconductor switch circuit comprising a common terminal and a terminal for turning “OFF” between the signal terminals.

(Supplementary note 2) The semiconductor switch circuit according to supplementary note 1, wherein the through FET and the shunt FET are enhancement mode transistors.

1 is a block diagram showing a configuration of a high frequency switch according to Embodiment 1 of the present invention. The figure which shows the relationship of RF terminal connected with a common RF terminal with the control signal which concerns on Example 1 of this invention. 1 is a circuit diagram showing an internal circuit part of a high-frequency switch according to Embodiment 1 of the present invention. 1 is a block diagram showing a configuration of a conventional high frequency switch according to Embodiment 1 of the present invention. The figure which shows the relationship of RF terminal connected with a common RF terminal with a control signal in the conventional high frequency switch which concerns on Example 1 of this invention. 1 is a circuit diagram showing an internal circuit portion of a conventional high-frequency switch according to Embodiment 1 of the present invention. The circuit diagram which shows the internal circuit part of the high frequency switch which concerns on Example 2 of this invention. The circuit diagram which shows the internal circuit part of the high frequency switch which concerns on Example 3 of this invention.

Explanation of symbols

1, 1a Control circuit 2, 2a, 2b SP6T (internal circuit section)
2c SPDT (internal circuit part)
3 Driver 10, 10a High frequency switch (SP6T)
30 Semiconductor Integrated Circuit Devices NT1 to NT6, NT1A to NT6A, NT1B to NT6B, NT1a to NT1c, NT2a to NT2c, NT11 to NT16 Nch MOS Transistors P _{RF1 to} P _RF6 RF Terminal P _RFCOM Common RF Terminals PT1 to PT6, PT1A to PT6A PT1B to PT6B, PT1a to PT1c, PT2a to PT2c Pch MOS transistor P _VDD High potential side power supply terminal P _VSS Low potential side power supply terminals R1 to R6, R1A to R6A, R1B to R6B, R1a to R1c, R2a to R2c, R11 ~ R16, R11A ~ R16A, R11B ~ R16B, R11a ~ R11c, R12a ~ R12c, R21, R31 ~ R36, Rb1a ~ Rb1c, Rb2a ~ Rb2c, Rb11a ~ Rb11c, Rb12a ~ Rb12c Resistors S11 to S16, S11a to S16a, S110, S111, S120, S121, S130, S131, S140, S141, S150, S151, S160, S161 Switch control signals S _{V1 to} S _V3 Control signal V _DD High potential side power source V _S Ground potential V _SS Low potential side power supply

Claims (5)

Through FET composed of Nch insulated gate field effect transistor,
A shunt FET composed of a Pch insulated gate field effect transistor whose gate is connected to the gate of the through FET;
When a switch control signal is output to the gates of the through FET and the shunt FET, and the signal level of the switch control signal is “High”, the through FET is turned “ON”, the shunt FET is turned “OFF”, and When the signal level of the switch control signal is “Low”, a terminal for turning off the through FET and turning on the shunt FET;
A semiconductor switch circuit comprising: A through FET provided between the common terminal and the signal terminal and configured by an Nch insulated gate field effect transistor;
A shunt FET comprising a Pch insulated gate field effect transistor provided between the common terminal and the ground terminal and having a gate connected to the gate of the through FET;
When a switch control signal is output to the gates of the through FET and the shunt FET, and the signal level of the switch control signal is “High”, the shunt FET is turned “OFF” and the through FET is turned “ON”. When the common terminal and the signal terminal are activated, and the signal level of the switch control signal is “Low”, the through FET is turned “OFF”, the shunt FET is turned “ON”, and the common terminal and the signal are turned on. A terminal that turns OFF between the terminals,
A semiconductor switch circuit comprising:   The gate of the through FET is connected to a first resistor, the gate of the shunt FET is connected to a second resistor, and the switch control signal is input to the gate of the through FET through the first resistor, 3. The semiconductor switch circuit according to claim 1, wherein the switch control signal is input to a gate of the shunt FET through the second resistor. A through FET that is provided between the common terminal and the signal terminal, the back gate is connected to the source, the gate is connected to the first resistor, and the N-channel insulated gate field effect transistor;
Provided between the common terminal and the ground terminal, a back gate is connected to a source, a gate is connected to a second resistor, and a gate is connected to the through FET via the second resistor and the first resistor. A shunt FET composed of a Pch insulated gate field effect transistor,
When a switch control signal is output to the gate of the through FET via the first resistor and the gate of the shunt FET via the second resistor, and the signal level of the switch control signal is “High”, When the shunt FET is turned “OFF”, the through FET is turned “ON” to activate between the common terminal and the signal terminal, and when the signal level of the switch control signal is “Low”, the through FET is turned “ A terminal for turning off the shunt FET and turning off the common terminal and the signal terminal;
A semiconductor switch circuit comprising: A through FET provided between the common terminal and the signal terminal, having a gate connected to the first resistor, a second resistor provided between the back gate and the ground potential, and comprising an Nch insulated gate field effect transistor When,
Provided between the common terminal and the ground terminal, the gate is connected to a third resistor, the gate is connected to the gate of the through FET via the third resistor and the first resistor, and the back A shunt FET provided with a fourth resistor between the gate and the high-potential-side power supply and configured by a Pch insulated gate field effect transistor;
When a switch control signal is output to the gate of the through FET via the first resistor and the gate of the shunt FET via the third resistor, and the signal level of the switch control signal is “High”, When the shunt FET is turned “OFF”, the through FET is turned “ON” to activate between the common terminal and the signal terminal, and when the signal level of the switch control signal is “Low”, the through FET is turned “ A terminal for turning off the shunt FET and turning off the common terminal and the signal terminal;
A semiconductor switch circuit comprising:

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