JP2008010491A - Nonvolatile memory with single gate and its operating method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile memory with a single gate realizing the purpose of reducing current consumption and its operating method. <P>SOLUTION: The nonvolatile memory has a transistor and a capacitive structure embedded in a semiconductor base. The transistor includes a first conductive gate, a first dielectric layer and a plurality of first ion-doped regions. The capacitive structure includes a second conductive gate, a second dielectric layer, and a second ion-doped region. The first and second conductive gates are electrically connected to form a single floating gate serving as a memory cell. The memory cell with a single gate performs operation such as writing, related erasure, reading or the like by reverse biasing. In addition, when operation of an isolated well region takes place, an inverted layer is generated by applying positive/negative voltage to a drain electrode, a gate electrode, and a silicon base or a well region, to have absolute voltage dropped and to reduce an area of a booster circuit. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a non-volatile memory and an operation method thereof, and more particularly, to a single-gate nonvolatile memory that performs writing and erasing with low voltage and low current consumption and an operation method thereof.

Complementary Metal Oxide Semiconductor (CMOS) process technology is an application specific integrated circuit (application specific integrated circuit).
circuit, ASIC). With the development of computer information products today, electrically erasable programmable read only memory (EEPROM) has a non-volatile memory function for electrically writing and erasing data, and after the power is turned off, Since data is not lost, it is widely applied to electronic products.

The non-volatile memory is programmable and stores the charge, thereby changing the voltage of the gate electrode of the transistor of the memory, or without storing the charge, the voltage of the gate electrode of the transistor of the original memory Save. The erase operation removes all charges stored in the non-volatile memory and returns all non-volatile memories to the voltage of the gate electrodes of the transistors of the original memory. Therefore, in the conventional nonvolatile memory structure, since the operation voltage generally exceeds 10 volts, not only the cost increases due to the boost area, but also the purpose of performing the operation after boosting by consuming a large amount of current. In addition, manufacturing a non-volatile memory with advanced process technology requires a number of processes, which increases manufacturing difficulty and costs, especially in embedded products. In some cases, therefore, existing advanced process technology tends to develop in the direction of lower voltages.

The main object of the present invention is to use a single floating gate structure in order to solve the above problems, and to apply an effective voltage to the source electrode and to apply a back bias to the transistor base at the time of programming. This creates a slightly wider depleted source electrode-base interface, and improves the efficiency of current flow to the floating gate, greatly reducing the current demand for programmed single-gate non-volatile memory Provided is a single gate non-volatile memory and a method of operating the same.

Another object of the present invention is to increase the voltage of the drain electrode and apply a fine voltage to the gate electrode, thereby increasing the FN tunnel current and performing erasing, thereby enabling high-speed erasing. Provided are a single-gate nonvolatile memory capable of obtaining an effect and a method for operating the same.

Still another object of the present invention is to provide a single gate which can achieve the effect of ultra-low operating voltage, low operating current and high reliability by positive / negative pressure, and can reduce the volume of the entire nonvolatile memory. A nonvolatile memory and a method for operating the same are provided.

In order to achieve the above object, the present invention embeds a transistor and a capacitor structure in a semiconductor base, and the transistor is stacked on the surface of the first dielectric layer. The first dielectric layer is formed on the semiconductor base or in an isolation well. A first conductive gate located on both sides and having two highly conductive first ion-doped regions on both sides for forming a source electrode and a drain electrode; A sandwich-like top plate-dielectric layer-top plate structure, including a second ion doped region, a second dielectric layer and a second conductive gate, and a second conductive gate of a capacitive structure; A single-gate nonvolatile memory in which a first conductive gate of a transistor is isolated and electrically connected, and forms a single floating gate of the nonvolatile memory, and an operation method thereofAmong them, the semiconductor base or the isolation well is P-type and the first ion-doped region and the second ion-doped region are N-type, or the semiconductor base is N-type and the first ion-doped region and the second ion-doped region are second-type. The ion doped region is P-type.

The low-voltage operation method of the single-gate nonvolatile memory is a programming method by applying a voltage to the source electrode or applying a back-bias to the transistor base (or the voltage of the source electrode when writing). Is faster than the base voltage), and the gate electrode voltage is increased (or, when erasing, the gate electrode voltage is greater than the source electrode voltage), the fast erase method increases the FN tunnel current. Yes, or using a negative pressure device to achieve ultra-low operating voltage and low operating current. A method of performing programming and erasing operations with different structural changes on a single-gate nonvolatile memory device by the method of the present invention is included in the scope of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the objects, technical contents, features, and effects of the present invention will be more clearly understood by describing the drawings in detail with specific examples.

FIG. 1 is a sectional view of a single gate nonvolatile memory structure according to a first embodiment of the present invention.

The single-gate nonvolatile memory structure 100 includes an NMOS transistor (NMOSFET) 110 and an N-type capacitance structure 120 in a P-type semiconductor base 130, and the NMOS transistor 110 is located on the surface of the P-type semiconductor base 130. Of the first dielectric layer 111, the first conductive gate 112 stacked on the first dielectric layer 111, and the channel 115 between the source electrode 113 and the drain electrode 114 located in the P-type semiconductor base 130. Are formed, and each of the N-type capacitor structure 120 includes a second ion located in the P-type semiconductor base 130. A doped region 121; a second dielectric layer 122 located on a side surface of the second ion doped region 121; and a second dielectric layer A second conductive gate 123 to be stacked on the 22, is contained, the upper - dielectric layer - forming the capacitor structure of the side bottom plate. The first conductive gate 112 of the NMOS transistor 110 and the second conductive gate 123 on the upper side of the N-type capacitor structure 120 are electrically connected, and are isolated by a separator 138 to be a single floating gate (floating). gate) 140 is formed. The first ion doped region and the second ion doped region 121 are N-type ion doped regions.

The single gate nonvolatile memory structure 100 is a structure having four end points, and the four end points are a source electrode, a drain electrode, a control gate electrode, and a base connection structure, respectively, as shown in FIG. 2A. , Base voltage Vsub, source electrode voltage Vs, drain electrode voltage Vd, and control gate electrode voltage Vc are applied to base 130, source electrode 113, drain electrode 114, and second ion doped region 121, respectively. 2B is an equivalent circuit thereof. The conditions in the low voltage operation process of the single gate nonvolatile memory structure 100 are as follows.
When writing
a, Vsub is connected to ground (= 0).
b, Vd>Vs> 0 and Vc>Vs> 0.
When erasing
a, Vsub is connected to ground (= 0).
b, Vd>Vc> Vs ≧ 0.

FIG. 3 is a sectional view of a single gate nonvolatile memory structure according to a second embodiment of the present invention.

The single-gate nonvolatile memory structure 200 includes a PMOS transistor 210 and an N-type capacitor structure 220 in a P-type semiconductor base 230, and the first ion-doped region of the PMOS transistor 210 is a P-type ion-doped region and an N-type. The second ion doped region 221 of the capacitor structure 220 is an N-type ion doped region, and an N-type well 216 is further provided below the first ion doped region, so that the first conductive gate 212 of the PMOS transistor 210 is provided. And the second conductive gate 223 located on the upper side of the N-type capacitor structure 220 are electrically connected to each other and are isolated by a separator 238 to form a single floating gate 240 structure.

In a low voltage operation process for the single gate nonvolatile memory structure 200, a base voltage Vsub and an N type well voltage Vnwell are applied to the base 230, the N type well 216, the source electrode 213, the drain electrode 214, and the second ion doped region 221, respectively. The source electrode voltage Vs, the drain electrode voltage Vd, and the control gate electrode voltage Vc are applied, and the conditions are as follows.
When writing
a, Vsub is connected to ground (= 0).
b, Vnwell ≧ Vs>Vd> 0 and Vc>Vd> 0.

FIG. 4 is a conceptual diagram of the erase structure of FIG. 3. In order to prevent generation of a positive junction bias between the N-type well of the PMOS transistor and the P-type semiconductor base, the N-type well voltage Vnwell is In order to prevent the PMOS transistor from opening, it is necessary to make the control gate electrode voltage Vc sufficiently large in order to prevent the PMOS transistor from being opened. By increasing the voltage Vd of the drain electrode until it becomes equal to the well voltage Vnwell and increasing the voltage Vd of the drain electrode to be equal to the base voltage Vsub, the charge is erased by the single floating gate.
When erasing
a, Vsub is connected to ground (= 0), Vc> 0.
b, Vnwell ≧ Vs> Vd ≧ 0.

FIG. 5 is a sectional view of a single gate nonvolatile memory structure according to a third embodiment of the present invention.

The single-gate nonvolatile memory structure 300 includes an NMOS transistor 310, an N-type capacitance structure 320, and a P-type well 316 in an N-type semiconductor base 330. The NMOS transistor 310 and the N-type capacitance structure 320 include the P-type well 317. The first conductive gate 312 of the NMOS transistor 310 and the second conductive gate 323 on the upper portion of the N-type capacitor structure 320 are electrically connected to each other and are isolated by the separator 338. The structure of the single floating gate 340 is formed.

In the process of erasing and writing to the single-gate nonvolatile memory structure 300, the N-type semiconductor base 330, the P-type well 316, the source electrode 313, the drain electrode 314, and the second ion-doped region 321 respectively. The base voltage Vsub, the P-type well voltage Vpwell, the source electrode voltage Vs, the drain electrode voltage Vd, and the control gate electrode voltage Vc are applied, and the conditions in the low voltage operation process are as follows.
When writing
a, Vsub is connected to the power supply and Vpwell = 0.
b, Vd>Vs> 0 and Vc>Vs> 0.
When erasing
a, Vsub is connected to the power supply and Vpwell = 0.
b, Vd>Vc> Vs ≧ 0.

Alternatively, it is programmed with base back-bias.
When writing
a, Vsub is connected to the power supply and Vpwell> 0.
b, Vd>Vs>Vpwell> 0 and Vc>Vs>Vpwell> 0.
When erasing
a, Vsub is connected to the power source, and Vpwell is connected to the ground (= 0).
b, Vd>Vc> Vs ≧ 0.

The single gate nonvolatile memory structure 100 of FIG. 1 above is fabricated on a P-type silicon wafer, and the isolation structure 138 is completed by a standard isolation module process to form a basic isolation structure 138 and then an N-type capacitance. The structure 110 and the channel 115 of the NMOS transistor 120 are formed by ion implantation, and after the dielectric layers of the first conductive gate 112 and the second conductive electrode 123 are grown, polysilicon is formed by deposition, and Then, patterning is performed by photolithography etching to form a single floating gate 140 from polycrystalline silicon, and ions are implanted to form electrodes such as a source electrode 113 and a drain electrode 114 of the NMOS transistor 110 and a control gate electrode. After metallization, the fabrication of single gate nonvolatile memory structure 100 is completed.

By the same process, the single gate nonvolatile memory structure 200 of FIG. 3 is formed by different patterning for the ion implantation region of the N-type well 216 and the implantation region of the source electrode-gate electrode, and the single gate nonvolatile memory structure of FIG. The non-volatile memory structure 300 is completed on the N-type silicon wafer by the same process and different patterning for the P-type well 317 and the source electrode-gate electrode implantation region. This indicates the manufacturing flow of CMOS.

In the present invention, when programming, a voltage is applied to the source electrode of the single gate nonvolatile memory structure, and the source electrode voltage generates a reverse bias at the junction between the source electrode and the base. The potential between the source electrode and the drain electrode decreases until the channel carrier can move from the source electrode to the drain electrode. The reverse bias between the source electrode and the base is more depleted.
junction region), thus creating a higher concentration of carrier density near the channel surface, and the higher carrier density near the channel surface improves the current effect of the gate electrode and is required for programming Total current is reduced. Therefore, the reliability, programming interference and programming speed are greatly improved, and the current efficiency of the gate electrode is improved several hundred times by the conventional technique not using the source electrode voltage.

Further, the present invention is used for erasing by increasing the FN tunnel current by increasing the drain electrode voltage and applying a fine voltage to the gate electrode. An effect is obtained.

FIG. 7 is a sectional view of a single gate nonvolatile memory structure according to a fourth embodiment of the present invention.

The single gate nonvolatile memory structure 400 includes an isolation well, and the present invention can further reduce the work absolute voltage and current due to positive and negative pressures. The single gate nonvolatile memory structure 400 is a structure having six end points, and the six end points are a source electrode, a drain electrode, a control gate electrode, a P-type well, and an N-type well, respectively, as shown in FIG. 8A. And the base voltage Vsub and the source electrode on the P-type semiconductor base 430, the source electrode 413, the drain electrode 414, the P-type well 417, the N-type well 416, and the second ion-doped region 421, respectively. A voltage Vs, a drain electrode voltage Vd, a P-type well voltage Vpwell, an N-type well voltage Vnwell, and a control gate electrode voltage Vc are applied, and FIG. 8B is an equivalent circuit thereof. The conditions in the low voltage operation process of the single gate nonvolatile memory structure 400 are as follows.
When writing
a, Vsub is connected to ground (= 0), Vpwell is negative pressure, and Vnwell is positive pressure.
b, Vs> Vpwell, Vs <Vd, and Vc> Vs.
When erasing
a, Vsub is connected to ground (= 0), Vpwell is negative pressure, and Vnwell is positive pressure.
b, Vs ≧ Vpwell, Vs <Vd, and Vc> Vs.

The structure of FIG. 7 above is fabricated on a P-type silicon wafer, and the isolation structure 438 is completed by a standard isolation module process to form a basic isolation structure 438 and then an N-type well 416 and a P-type well. 417 and the channel 415 of the NMOS transistor 410 are formed by ion implantation, and after the dielectric layers of the first conductive gate 412 and the second conductive gate 423 are grown, the polycrystalline silicon is formed by deposition. Patterning is performed by photolithography etching to form a single floating gate 440 from polycrystalline silicon, and ions are implanted to form electrodes such as a source electrode 413 and a drain electrode 414 of the NMOS transistor 410 and a control gate electrode. After metallization, fabrication of the single gate nonvolatile memory structure 400 is completed.

Therefore, according to the method of operating a single gate nonvolatile memory according to the present invention, the current demand for programmed single gate nonvolatile memory elements is greatly reduced. In the single gate nonvolatile memory device, when erasing, the gate electrode voltage is higher than the drain electrode voltage and the transistor base voltage, so that the erasing speed is accelerated.

Further, in the fifth embodiment according to the present invention, by applying a negative voltage to the P-type well, the absolute voltage of the drain electrode and the gate electrode becomes small (5 V or less) and low when writing and erasing. The operation effect of low voltage consumption current is obtained.

FIG. 9 is a sectional view of a single gate nonvolatile memory structure according to a fifth embodiment of the present invention.

The single-gate nonvolatile memory structure 500 includes an NMOS transistor 510 and an N-type capacitance structure 520 in a P-type well 517. The P-type well 517 is provided on an N-type semiconductor base 530. The first conductive gate 512 of the NMOS transistor 510 and the second conductive gate 523 on the upper part of the N-type capacitor structure 520 are electrically connected and are isolated by the separator 538, and the single floating gate 540 A structure is formed.

In the erasing process and the writing process, the N-type semiconductor base 530, the source electrode 513, the drain electrode 514, the P-type well 517, and the second ion-doped region 521 are over the single-gate nonvolatile memory structure 500 of FIG. A base voltage Vsub, a source electrode voltage Vs, a drain electrode voltage Vd, a P-type well voltage Vpwell, and a control gate electrode voltage Vc are applied to each of them, and the conditions in the low voltage operation process are as follows. .
When writing
a, Vsub are connected to the power source, and Vpwell is negative pressure.
b, Vs> Vpwell, and Vs <Vd, Vc> Vs.
When erasing
a, Vsub are connected to the power source, and Vpwell is negative pressure.
b, Vs ≧ Vpwell, and Vs <Vd, Vc> Vs.

The above is only for the purpose of explaining the features of the present invention by way of examples. The present invention is not limited thereby, and various modifications can be made based on the contents of the present invention by those skilled in the art. However, all such equivalent changes and modifications are included in the scope of the claims of the present invention.

1 is a cross-sectional view of a single gate nonvolatile memory structure according to a first embodiment of the present invention. The structure conceptual diagram of the four end points of 1st Example concerning this invention. An equivalent circuit of the structure of FIG. 2A. Sectional drawing of the non-volatile memory structure of the single gate which is the 2nd Example concerning this invention. Sectional conceptual diagram of the erase structure of the second embodiment according to the present invention. Sectional drawing of the non-volatile memory structure of the single gate which is the 3rd Example concerning this invention. Sectional conceptual diagram of the erase structure of the third embodiment according to the present invention. Sectional drawing of the non-volatile memory structure of the single gate which is the 4th Example concerning this invention. The conceptual diagram of the structure of the six end points of the fourth embodiment according to the present invention. The equivalent circuit of the structure of FIG. 8A. Sectional drawing of the non-volatile memory structure of the single gate which is the 5th Example concerning this invention.

Explanation of symbols

100 single gate nonvolatile memory structure 110 NMOS transistor 111 first dielectric layer 112 first conductive gate 113 source electrode 114 drain electrode 115 channel 120 N-type capacitance structure 121 second ion doped region 122 second dielectric layer 123 second Two conductive gates 130 P-type semiconductor base 138 Separator 140 Single floating gate 200 Single-gate nonvolatile memory structure 210 PMOS transistor 212 First conductive gate 213 Source electrode 214 Drain electrode 216 N-type well 220 N-type capacitance structure 221 Second Ion doped region 223 Second conductive gate 230 P-type semiconductor base 238 Separator 240 Single floating gate 300 Single gate nonvolatile memory structure 310 NMOS transistor 312 One conductive gate 313 Source electrode 314 Drain electrode 317 P-type well 320 N-type capacitance structure 321 Second ion-doped region 323 Second conductive gate 330 N-type semiconductor base 338 Separator 340 Single floating gate 400 Single gate nonvolatile memory Structure 410 NMOS transistor 412 First conductive gate 413 Source electrode 414 Drain electrode 415 Channel 416 N-type well 417 P-type well 420 N-type capacitive structure 421 Second ion-doped region 423 Second conductive gate 430 P-type semiconductor base 438 Separator 440 Single floating gate 500 Single gate nonvolatile memory structure 510 NMOS transistor 512 First conductive gate 513 Source electrode 514 Drain electrode 517 P-type well 520 N-type capacitance structure Structure 521 Second ion doped region 523 Second conductive gate 530 N-type semiconductor base 538 Separator 540 Single floating gate

Claims (17)

A semiconductor base, a first dielectric layer, a first conductive gate, and a plurality of first ion-doped regions are included, the first dielectric layer being located on the surface of the semiconductor base, and the first conductive layer A transistor having a gate deposited above the first dielectric layer, the first ion-doped region being located on both sides of the first conductive gate, and forming a source electrode and a drain electrode, respectively;
A second dielectric layer, a second conductive gate, and a second ion doped region are contained, the second dielectric layer is located on the surface of the semiconductor base, and the second conductive gate is the second conductive gate. The second ion-doped region is located on one side of the second dielectric layer, and the first conductive gate and the second conductive gate are isolated and electrically Capacitively connected and single floating gate,
A single-gate nonvolatile memory characterized by comprising:   2. The single gate nonvolatile memory according to claim 1, wherein the semiconductor base is a P-type semiconductor base or an N-type semiconductor base.   The first ion doped region and the second ion doped region are doped with a first type of ions, the semiconductor base is doped with a second type of ions, and the first type of ions and The single-gate nonvolatile memory according to claim 1, wherein the single-type nonvolatile memory is different from the second type of ions.   The single-gate nonvolatile memory according to claim 3, wherein the semiconductor base is a P-type semiconductor base, and the first ion-doped region and the second ion-doped region are N-type doped regions. memory.   4. The single gate nonvolatile semiconductor device according to claim 3, wherein the semiconductor base is an N-type semiconductor base, and the first ion-doped region and the second ion-doped region are P-type doped regions. Sex memory.   Furthermore, there is a third ion-doped region provided in the semiconductor base and located below the first ion-doped region, and the second ion-doped region in the third ion-doped region. The single gate nonvolatile memory according to claim 1, wherein ions of the same type as the region are doped.   The single-gate nonvolatile memory according to claim 6, wherein the third ion-doped region extends to a position below the second ion-doped region.   Furthermore, there is an isolation well provided in the semiconductor base and positioned below the third ion-doped region, and the first type ions are doped in the isolation well and the second ion-doped region. 8. The second ion is doped in the third ion doped region and the semiconductor base, and the first type ion and the second type ion are different from each other. Single-gate nonvolatile memory as described in 1.   7. The single-gate nonvolatile memory according to claim 6, wherein the semiconductor base is an N-type semiconductor base, and the second ion-doped region and the third ion-doped region are P-type doped regions. Sex memory.   7. The single-gate nonvolatile memory according to claim 6, wherein the semiconductor base is a P-type semiconductor base, and the second ion-doped region and the third ion-doped region are N-type doped regions. Sex memory. The nonvolatile memory includes a P-type semiconductor base, a transistor, and a capacitor structure. The transistor and the capacitor structure are provided in the P-type semiconductor base, and the transistor includes a first conductive gate and a plurality of first transistors. An ion doped region, and the first ion doped region is located on both sides of the first conductive gate to form a source electrode and a drain electrode, respectively. An ion-doped region and a second conductive gate are included, and the first conductive gate and the second conductive gate are electrically connected to form a single floating gate. An operation method,
A base voltage Vsub, a source electrode voltage Vs, a drain electrode voltage Vd, and a control gate electrode voltage Vc are applied to the P-type semiconductor base, the source electrode, the drain electrode, and the second ion-doped region, respectively. Also, when writing, Vsub is ground,
Vd>Vs> 0,
Vc>Vs> 0,
When erasing, Vsub is ground,
Vd>Vc> Vs ≧ 0
A method for operating a single-gate nonvolatile memory, characterized in that: The nonvolatile memory includes a P-type semiconductor base, a transistor, an N-type well, and a capacitor structure. The transistor and the capacitor structure are provided in the P-type semiconductor base, and the transistor includes a first conductive gate and a plurality of conductive gates. And the first ion doped region is located on both sides of the first conductive gate to form a source electrode and a drain electrode, respectively. The N-type well is provided below the ion-doped region, the second ion-doped region and the second conductive gate are contained in the capacitor structure, and the first conductive gate and the second conductive gate are included. A method for operating a single gate nonvolatile memory in which a gate is electrically connected to form a single floating gate,
On the P-type semiconductor base, the N-type well, the source electrode, the drain electrode, and the second ion-doped region, a base voltage Vsub, an N-type well voltage Vnwell, a source electrode voltage Vs, and a drain electrode voltage, respectively. When Vd and control gate electrode voltage Vc are applied and when writing, Vsub is ground,
Vnwell ≧ Vs>Vd> 0,
Vc>Vd> 0,
When erasing, Vsub is ground,
Vc> 0,
Vnwell ≧ Vs> Vd ≧ 0,
A method for operating a single-gate nonvolatile memory, characterized in that: The nonvolatile memory includes an N-type semiconductor base, a transistor, a P-type well, and a capacitor structure, the P-type well is provided on the N-type semiconductor base, and the transistor and the capacitor structure are connected to the P-type. The first conductive gate and the plurality of first ion doped regions are included in the transistor, and the first ion doped region is provided on both sides of the first conductive gate. Each of which forms a source electrode and a drain electrode, the capacitor structure includes a second ion-doped region and a second conductive gate, and the first conductive gate and the second conductive gate. A method for operating a single gate nonvolatile memory in which a gate is electrically connected to form a single floating gate,
On the N-type semiconductor base, the P-type well, the source electrode, the drain electrode, and the second ion-doped region, a base voltage Vsub, a P-type well voltage Vpwell, a source electrode voltage Vs, and a drain electrode voltage, respectively. When Vd and control gate electrode voltage Vc are applied and writing is performed, Vsub is connected to the power source,
Vd>Vs> Vpwell,
Vc>Vs> Vpwell,
When erasing, Vsub is connected to the power supply,
Vc> Vs ≧ Vpwell,
A method for operating a single-gate nonvolatile memory, wherein Vd> Vs ≧ Vpwell (see the third and fifth embodiments) is satisfied.   14. The method of operating a single gate nonvolatile memory according to claim 13, wherein the write condition satisfies Vpwell ≧ 0.   14. The method of operating a single gate nonvolatile memory according to claim 13, wherein the erasing condition satisfies Vpwell ≧ 0.   16. The method of operating a single gate nonvolatile memory according to claim 15, wherein the erasing condition satisfies Vd> Vc> Vs ≧ 0. The nonvolatile memory includes a P-type semiconductor base, a transistor, an N-type well, a capacitor structure, and a P-type well. The N-type well is provided on the P-type semiconductor base, and the P-type well is Provided on an N-type well, the transistor and the capacitor structure are disposed on a surface of the P-type well, the transistor including a first conductive gate and a plurality of first ion-doped regions; In addition, the first ion doped region is located on both sides of the first conductive gate to form a source electrode and a drain electrode, respectively, and the second ion doped region and the second conductive region are formed in the capacitor structure. And a single-gate nonvolatile memory operating method in which the first conductive gate and the second conductive gate are electrically connected to form a single floating gate. There is,
On the P-type semiconductor base, the source electrode, the drain electrode, the P-type well, the N-type well, and the second ion-doped region, respectively, a base voltage Vsub, a source electrode voltage Vs, and a drain electrode voltage Vd P-type well voltage Vpwell, N-type well voltage Vnwell and control gate electrode voltage Vc are applied, and
When writing
Vc>Vs> Vpwell,
Vd>Vs> Vpwell,
Vsub is ground,
Vnwell ≧ 0,
When erasing
Vc> Vs ≧ Vpwell,
Vd> Vs ≧ Vpwell,
Vsub is grounded
Vnwell ≧ 0,
A method for operating a single-gate nonvolatile memory, characterized in that: