JP2008010064A - Data coding circuit, data recorder, and pi/po arithmetic processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data coding circuit which accelerates processing by reducing the number of times of memory access for ECC processing. <P>SOLUTION: Sector data is scrambled by a scramble arithmetic circuit 105, thereafter written in a memory 101, and input to a PI arithmetic circuit 106 and a PO arithmetic circuit 107. The PI arithmetic circuit 106 carries out PI coding arithmetic processing to the sector data of one line each, writes the obtained PI code in a memory 101, and inputs it in the PO arithmetic circuit 107 simultaneously. The PO arithmetic circuit 107 reads a PO code stored in a buffer 108 already, sets a syndrome arithmetic formula for calculating the PO code from the PO code, input sector data and a PI code, calculates a PO code of each column, and writes it back in the buffer 108. When processing for an IECC block is finished, the PO code in the buffer 108 is written in the memory 101. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a data encoding circuit, a data recording apparatus, and a PI / PO arithmetic processing method, and particularly generates and adds an error correction code by product encoding processing in a row direction (PI direction) and a column direction (PO direction). It is suitable for use.

  In the fields of communication, computer, broadcasting, video media, etc., error correction codes are generally used to improve data reliability and to increase recording density in a recording system. In particular, recently, with the improvement of data processing capability, error correction codes having a high correction capability have been used.

  Even in a DVD (Digital Versatile Disc) playback device that provides high-quality video, an error correction code called a Reed-Solomon (RS) product code having a high correction capability is used, and an error generated in a transmission system can be corrected. ing.

  The product code is a combination of error correction codes in different vertical and horizontal directions. The inner code PI (Parity Inner) code added in the horizontal direction of the information data block, and a block consisting of the information data block and the PI code It is composed of an outer code PO (Parity Outer) code added in the vertical direction. A block formed by adding these PI code and PO code to an information data block is an ECC block.

  FIG. 12 shows the data structure of an ECC block applied to the DVD recording apparatus. As shown in the figure, the ECC block is composed of data of 208 rows × 181 columns, and a PO code and a PI code are added to the 192nd to 208th rows and the 172nd to 181th columns, respectively. Of these, the PI code is added to the sector data of each row, and the PO code is added to the sector data and PI code of each column.

  FIG. 13 is a diagram showing the flow of processing from when data is supplied from the host to the data encoding circuit until it is recorded on the disk. Here, processing is generally performed according to the following procedure.

  (1) Data is written into the memory from the host side (see FIG. 13A).

  (2) Data is read from the memory, and header and EDC (Error Detection Code) addition processing is performed (see FIG. 13B). Further, scramble processing is performed on the data to which the header and EDC are added (see FIG. 13C), and the scrambled data is written back to the memory.

  (3) The PI code is calculated by the ECC circuit and written in the memory (see FIG. 13D). At this time, a read and a write occur once for each row in the memory.

  (4) The PO code is calculated by the ECC circuit and written in the memory (see FIG. 13E). At this time, a read and a write occur once for each column in the memory.

  (5) Data is read from the memory for each row and output to the modulation circuit (see FIG. 13F). The modulation circuit modulates the input data to generate a recording signal, and sequentially outputs it to the recording system. The recording system performs a writing operation on the disc in accordance with the input recording signal.

For example, a processing method described in Patent Document 1 below is known as an ECC encoding process required for a DVD recording apparatus, that is, a process for generating and adding a PI code and PO code to information data. ing.
JP 2002-93058 A

  In DVD recording devices and next-generation DVD recording devices that are currently being commercialized, like existing CD recording devices, it is desired to cope with so-called “high-speed recording” in which recording is performed on a disk at high speed. . In order to realize such “high-speed recording” on the apparatus side, it is necessary to speed up the ECC encoding process performed during the writing process. In this case, in particular, the problem is how to reduce the number of accesses to the memory (generally D-RAM or SDRAM) which is a bottleneck for speeding up.

  The present invention has been made in view of such a situation, and a data encoding circuit, a data recording apparatus, and a PI / PO that can increase the processing speed by reducing the number of memory accesses during ECC processing. It is an object to provide an arithmetic processing method.

  According to the first aspect of the present invention, in the data encoding circuit, a scramble operation unit that scrambles data input from the host, and a row direction error correction that generates a row direction error correction code from the scrambled data. Generated by a code calculation unit, a column-direction error correction code calculation unit that generates a column-direction error correction code from the scrambled data and the row-direction error correction code, and the column-direction error correction code calculation unit A buffer for storing the column-direction error correction code, and a memory for storing the scrambled data, the row-direction error correction code and the column-direction error correction code, and the column-direction error correction code calculation The unit receives the scrambled data from the scramble calculation unit, or from the error correction code calculation unit in the row direction. In response to the input of the error correction code in the row direction, the error correction code in the column direction stored in the buffer is read, and the read error correction code in the column direction and the input data or the row direction An error correction code in the column direction is newly generated from the error correction code of the column and written back to the buffer, and the error correction code in the column direction corresponding to the error correction unit is calculated by the calculation process by the error correction code calculation unit in the column direction. After being stored in the buffer, the error correction code in the column direction is read from the buffer and stored in the memory.

  According to the present invention, access to the memory during ECC encoding processing includes (1) writing scrambled data, (2) writing PI code (error correction code in the row direction), and (3) PO code (column Direction error correction code). Therefore, compared with the above-described conventional technique, the number of memory accesses during the ECC process can be remarkably reduced, and the speed of the encoding process can be increased.

  According to a second aspect of the present invention, in the data encoding circuit according to the first aspect, in the memory, the data, the error correction code in the row direction, and the column direction are sequentially stored in the memory in accordance with the reading order to the modulation circuit. The error correction code storage area is set, and the column-direction error correction code stored in the buffer is stored in the corresponding column-direction error correction code storage area on the memory, respectively. To do.

  According to the present invention, when data is read from the memory and transferred to the recording system, the data is read out from the memory one line at a time in a monotonous manner from the start address to the final address of the mapping area and output to the recording system. Therefore, according to the present invention, in addition to the effect of the invention of claim 1, it is possible to achieve an effect that the access control to the memory at the time of data reading can be simplified.

  According to a third aspect of the present invention, in the data encoding circuit according to the first or second aspect, the buffer includes a first buffer and a second buffer, and the arithmetic processing in the error correction code arithmetic unit in the column direction The buffer used sometimes is switched between the first buffer and the second buffer for each error correction unit, and the error correction in the column direction stored in one of the two buffers is performed. The code is read out during a period in which the other buffer is used during the calculation process in the error correction code calculation unit in the column direction, and is stored in the memory.

  According to the present invention, the writing process of the PO code (column direction error correction code) to the memory is performed in the PO encoding process period for the next ECC block (error correction unit). Therefore, the time required for the encoding process for each ECC block can be reduced by the amount that the PO code writing process for the memory is not performed. Therefore, according to the present invention, smooth data transfer control from the host to the data encoding circuit can be achieved.

  According to a fourth aspect of the present invention, in the data encoding circuit, a scramble operation unit that scrambles data input from a host, and a row direction error correction that generates a row direction error correction code from the scrambled data. Generated by a code calculation unit, a column-direction error correction code calculation unit that generates a column-direction error correction code from the scrambled data and the row-direction error correction code, and the column-direction error correction code calculation unit A buffer for storing the error correction code in the column direction, a memory for storing the scrambled data and the error correction code in the row direction, and the error correction code calculation unit in the column direction includes the scramble calculation unit The scrambled data is input from the above, or the error correction code in the row direction is input from the error correction code calculation unit in the row direction. The column-direction error correction code stored in the buffer is read in response to the input, and a column is newly created from the read column-direction error correction code and the input data or row-direction error correction code. An error correction code in the direction is generated and written back to the buffer. After the error correction code in the column direction corresponding to the error correction unit is stored in the buffer in the calculation process by the error correction code calculation unit in the column direction, The data and the error correction code in the row direction are output from the memory to the modulation circuit one row at a time, and the column direction is output row by row from the buffer at the output timing of the error correction code in the column direction between the outputs. The error correction code is read out and output to the modulation circuit.

  According to the present invention, access to the memory during the ECC encoding process is suppressed to (1) writing scrambled data and (2) writing PI code (error correction code in the row direction). Therefore, compared with the first aspect of the invention, the number of memory accesses during the ECC process can be further reduced, and the speed of the encoding process can be increased.

  In addition, according to the present invention, since the PO code (column-direction error correction code) is not written to the memory, the storage area of the memory is increased by the storage area of the PO code as compared to the invention of claim 1 above. Can be reduced, and the size of the memory can be reduced.

  According to a fifth aspect of the present invention, in the data encoding circuit, a scramble operation unit that scrambles data input from a host, a row direction error correction code is generated from the scrambled data, and the scramble A PI / PO operation unit that generates a column direction error correction code from the processed data and the row direction error correction code, and a row direction error correction code generated by the PI / PO operation unit A PI buffer that is stored together with the data corresponding to the error correction code, a PO buffer that stores the column-direction error correction code generated by the PI / PO calculation unit, the scrambled data, and the row-direction data A memory for storing an error correction code and an error correction code in a column direction, and the PI / PO operation unit performs error correction in the column direction In the arithmetic operation of the signal, the data and the row-direction error correction code are read from the PI buffer, the column-direction error correction code stored in the PO buffer is read, and the read data and An error correction code in the column direction is newly generated from the error correction code in the row direction and the error correction code in the column direction and written back to the buffer, and the PI / PO operation unit calculates the error correction code in the column direction. Is performed, the data and the row-direction error correction code are read from the PI buffer and stored in the memory, and the PI / PO operation unit calculates the column-direction error correction code. After the error correction code in the column direction for the error correction unit is stored in the PO buffer, the error correction code in the column direction is read from the PO buffer, Characterized in that it is stored in the serial memory.

  According to the present invention, access to the memory at the time of ECC encoding processing includes (1) writing scrambled data and PI code (error correction code in the row direction) (transfer from PI buffer to memory), and (2 ) It is suppressed to write PO code (error correction code in the column direction). Therefore, compared with the above-described conventional technique, the number of memory accesses during the ECC process can be remarkably reduced, and the speed of the encoding process can be increased.

  In addition, according to the present invention, since the PI code and PO code arithmetic processing is performed in common with the PI / PO arithmetic processing unit, the circuit scale can be reduced and the power consumption in the data encoding circuit can be reduced. be able to.

  According to a sixth aspect of the present invention, in the data encoding circuit according to the fifth aspect, in the memory, the data, the error correction code in the row direction, and the column direction are sequentially stored in the memory in accordance with the reading order to the modulation circuit. The error correction code storage area is set, and the column-direction error correction code stored in the PO buffer is stored in the corresponding column-direction error correction code storage area on the memory, respectively. Features.

  According to the present invention, in addition to the effect of the invention of claim 5, as in the case of claim 2, the effect of simplifying the access control to the memory at the time of data reading can be achieved.

  According to a seventh aspect of the present invention, in the data encoding circuit according to the fifth or sixth aspect, the PO buffer includes a first buffer and a second buffer, and the column direction in the PI / PO operation circuit The buffer used in the error correction code calculation process is switched between the first buffer and the second buffer for each error correction unit, and stored in one of these two buffers. Further, the error correction code in the column direction is read out and stored in the memory during a period in which the other buffer is used during arithmetic processing in the PO arithmetic circuit.

  According to the present invention, the time required for the encoding process for each ECC block (error correction unit) can be reduced as in the third aspect of the invention, and therefore, data transfer control from the host to the data encoding circuit is possible. Can be facilitated.

  According to an eighth aspect of the present invention, in the data encoding circuit, a scramble operation unit that scrambles the data input from the host, and an error correction code in the row direction and an error correction code in the column direction from the scrambled data. A PI / PO operation unit to be generated; a PI buffer for storing the error correction code in the row direction generated by the PI / PO operation unit together with the data corresponding to the error correction code in the row direction; and the PI / PO A PO buffer for storing a column-direction error correction code generated by the calculation unit; and a memory for storing the scrambled data and the row-direction error correction code, wherein the PI / PO calculation unit includes: During the calculation process of the error correction code in the column direction, the data and the error correction code in the row direction are read from the PI buffer, The column-direction error correction code stored in the PO buffer is read, and a new column-direction error correction code is generated from the read data, row-direction error correction code, and column-direction error correction code. When data is written back to the buffer and the column / direction error correction code is processed by the PI / PO operation unit, the data and the row direction error correction code are read from the PI buffer. After the error correction code corresponding to the error correction unit is stored in the PO buffer and is stored in the buffer for the error correction code in the column direction by the PI / PO operation unit. The data and the row-direction error correction code are output to the modulation circuit row by row, and at the output timing of the column-direction error correction code between the outputs, the PO Error correction code of the column line by line from the buffer is read out, characterized in that it is output to the modulation circuit.

  According to the present invention, access to the memory during the ECC encoding process is suppressed by (1) writing of scrambled data and PI code (error correction code in the row direction) (transfer from the PI buffer to the memory). Therefore, compared with the above-described conventional technique, the number of memory accesses during the ECC process can be remarkably reduced, and the speed of the encoding process can be increased.

  In addition, according to the present invention, since the PI code and PO code (column-direction error correction code) calculation processing is performed in common with the PI / PO calculation processing unit, the circuit scale can be reduced, and the data code Power consumption in the circuit can be suppressed.

  Further, according to the present invention, since the PO code is not written to the memory, the memory area of the memory can be reduced by the storage area of the PO code as compared with the invention of claim 1 above, and the size of the memory can be reduced. Can be reduced.

  A ninth aspect of the present invention is a data recording apparatus comprising the data encoding circuit according to any one of the first to eighth aspects.

  According to a tenth aspect of the present invention, in the PI / PO calculation processing method, an error correction code in a row direction is generated from input data, the generated error correction code in the row direction is written in a memory, and an error correction code in the column direction is calculated. A PI operation step, a PO operation step of generating the column-direction error correction code from the input data and the row-direction error correction code, and writing the generated column-direction error correction code in a buffer; and error correction A PO writing step of reading the column-direction error correction code from the buffer and writing it into the memory after the unit-wise error correction code for a unit is stored in the buffer, The column direction error correction code is stored in a buffer, and the data or the row direction error correction code is input in response to the input. The column-direction error correction code stored in the buffer is read, and a new column-direction error correction code is generated from the read column-direction error correction code and the input data or row-direction error correction code. And writing back to the buffer.

  According to the present invention, the number of memory accesses during PI / PO calculation processing can be remarkably suppressed.

  In addition, invention of Claim 1 is embodied by Example 1 in embodiment shown below. Moreover, the invention of claim 2 is embodied by Example 2 in the following embodiments. Moreover, the invention of claim 3 is embodied by Example 4 in the following embodiments. Further, the invention of claim 4 is embodied by Example 3 in the following embodiments. Moreover, the invention of claim 5 is embodied by Example 5 in the following embodiments. The invention of claim 6 is embodied by combining the configuration of the second embodiment with the configuration of the fifth embodiment in the following embodiment. The invention of claim 7 is embodied by combining the configuration of the fourth embodiment with the configuration of the fifth embodiment in the following embodiment. Furthermore, the invention of claim 8 is embodied by combining the configuration of the third embodiment with the configuration of the fifth embodiment in the following embodiment.

  However, the following embodiment is merely an exemplary form for realizing the present invention, and the meaning of the term of the present invention or each constituent element is limited to that described in the following embodiment. Is not to be done.

  As described above, according to the present invention, it is possible to reduce the number of memory accesses during ECC processing, thereby speeding up data encoding processing.

  Other effects and meanings of the present invention will become more apparent from the following description of embodiments. However, the features of the present invention are not limited by the following embodiments.

  Embodiments of the present invention will be described below with reference to the drawings. This embodiment shows a configuration example when the present invention is applied to a DVD recording apparatus.

  FIG. 1 shows a configuration of a disk recording apparatus according to the embodiment.

  In the figure, 101 is a memory constituted by SDRAM or the like, 102 is an ID addition circuit for adding an ID to data, 103 is an error detection code added to the ID added by the ID addition circuit 102 and added. This is an IED arithmetic circuit. The ID is a logical address of each sector. The ID and IED constitute a part of the header shown in FIG.

  Reference numeral 104 denotes an EDC arithmetic circuit that calculates and adds an error detection code to the data in each sector, 105 denotes a scramble arithmetic circuit that scrambles the data in each sector, and 106 denotes a PI for the scrambled data. A PI operation circuit 107 that calculates and adds an error correction code (PI code) in the direction (row direction), 107 generates an error correction code (PO code) in the PO direction (column direction) for the scrambled data and the PI code. A PO operation circuit 108 for operation / addition is a buffer for storing an operation processing result (PO code) in the PO operation circuit 107.

  Reference numeral 200 denotes a modulation circuit that performs predetermined modulation on the data read from the memory 101 to generate a recording signal. Reference numeral 300 denotes an optical pickup that records data on the disk based on the recording signal input from the modulation circuit 200. is there.

  In this embodiment, data is supplied from the host to the ID adding circuit 102 in units of sectors. This data is input to the scramble arithmetic circuit 105 after the header and EDC are added by the IED arithmetic circuit 103 and the EDC arithmetic circuit 104.

  The scramble arithmetic circuit 105 performs scramble processing on the input data and writes it to the memory 101. At the same time, the scrambled data is input to the PI operation circuit 106 and the PO operation circuit 107, respectively.

  The PI operation circuit 106 performs an error correction code operation (PI code operation) on the input data line by line, and writes the obtained PI code to the memory 101 so as to be added to the data of that line. . At the same time, the PI code of each row is sequentially input to the PO operation circuit 107.

  The PO operation circuit 107 sets a syndrome operation expression for calculating a PO code from the data for one sector input from the scramble operation circuit 105 and the PI code input from the PI operation circuit 106, as will be described later. Based on this arithmetic expression, the PO code of each column is calculated. Then, the calculated PO code is written in the buffer 108.

  FIG. 2 is a diagram illustrating a processing operation in the PO arithmetic circuit 107.

  After the data transfer is started from the host, when the first sector of data and the corresponding PI code are input to the PO operation circuit 107 from the scramble operation circuit 105 and the PI operation circuit 106 one by one ( The PO calculation circuit 107 sets a syndrome calculation formula for calculating a PO code based on these data, and an error correction code calculation (PO code) based on this calculation formula. (Calculation) is executed (see (b) in the figure). Then, the PO code (PO code in the middle of calculation) obtained by this calculation is written in the buffer 108 (see FIG. 5C).

  Thereafter, when the next row of data and the corresponding PI code are input from the scramble arithmetic circuit 105 and the PI arithmetic circuit 106 to the PO arithmetic circuit 107 (see FIG. 4D), the PO arithmetic circuit 107 The PO code already written in the buffer 108 is read from the buffer 108, and a syndrome arithmetic expression for calculating the PO code is set again from the read PO code and the input data and PI code for one row. . Based on this arithmetic expression, error correction code calculation (PO code calculation) is executed using the data and PI code input this time and the PO code read from the buffer 108 (FIG. e)), and the PO code (PO code in the middle of calculation) obtained by this calculation is written back to the buffer 108 (see (f) in the figure).

  Further, when the data for the next line and the PI code corresponding thereto are input to the PO operation circuit 107, the PO operation circuit 107 is already written in the buffer 108 as described above. The code is read from the buffer 108, and a syndrome calculation formula for calculating the PO code is set again from the read PO code, the input data for one row, and the PI code. Based on this arithmetic expression, an error correction code calculation (PO code calculation) is performed using the data and PI code input this time and the PO code read from the buffer 108. The obtained PO code (PO code in the middle of calculation) is written back to the buffer 108.

  Similarly, the PO operation circuit 107 reads and writes the PO code to the buffer 108 and calculates the error correction code (PO) until the last row of data for one ECC block and the corresponding PI code are input. Sign operation). Then, when the PO code based on the data of all the ECC blocks and the PI code is written in the buffer 108, the PO code stored in the buffer 108 is read and written in the corresponding area in the memory 101 as it is. It is. As a result, data for one ECC block is mapped in the memory 101.

  As shown in the figure, the size of the buffer 108 is the same as the PO code for one ECC.

  Next, the processing operation of the data encoding circuit 100 will be described with reference to FIG.

  When data for one sector is input from the host to the scramble operation circuit 105 via the ID addition circuit 102, the IED operation circuit 103, and the EDC operation circuit 104 (S101), the input data is scrambled. Applied (S102), and the scrambled data is written in the corresponding area of the memory 101 (S103). At the same time, the scrambled data is input from the scramble arithmetic circuit 105 to the PI arithmetic circuit 106 and the PO arithmetic circuit 107, respectively (S104, 105).

  In response to this input, the PI operation circuit 106 executes error correction code calculation (PI code calculation) for each row of data for one sector (S106), and converts the obtained PI code into data of each row. In addition, the data is written in the corresponding area of the memory 101 (S107). At the same time, the PI operation circuit 106 sequentially inputs the PI code of each row to the PO operation circuit 107 (S108).

  On the other hand, when the scrambled data is input from the scramble arithmetic circuit 105 to the PO arithmetic circuit 107 in S105, the PO arithmetic circuit 107 is already written in the buffer 108 as described with reference to FIG. The current PO code is read from the buffer 108 (S109), and a syndrome arithmetic expression for calculating the PO code is set from the read PO code and the input data for one row. Then, the PO operation circuit 107 executes an error correction code operation (PO code operation) using the data for one row input this time and the PO code read from the buffer 108 based on this operation expression, A PO code is obtained (S110).

  Furthermore, when the PI code of each row is input from the PI operation circuit 106 to the PO operation circuit 107 in S108, the PO operation circuit 107 has already been written in the buffer 108 as when the scrambled data is input. The PO code is read from the buffer 108 (S109), and a syndrome calculation formula for calculating the PO code is set from the read PO code and the PI code inputted this time. Then, the PO operation circuit 107 executes error correction code operation (PO code operation) using the PI code input this time and the PO code read from the buffer 108 based on this operation expression, Obtain (S110).

  The PO codes obtained in this way are sequentially written in the buffer 108 (S111). These processes are repeated until the processes for all the rows in the sector are completed.

  When the processing for all the rows in the sector is completed, it is determined whether the calculation processing of the PO code and the writing processing to the buffer have been executed up to the last sector data constituting one ECC block and its PI code (S112).

  If the determination in S112 is NO, the process returns to S101, and the scramble process for the next sector constituting one ECC block and the calculation process of the PI code and the PO code are executed. As a result, the scrambled data for one sector and the corresponding PI code are written into the memory 101, and the PO code from the first sector to the sector is stored in the buffer 108.

  When the processing from S101 to S111 is executed up to the sector data of the last row constituting one ECC block and its PI code (S112: YES), the PO code for one ECC block stored in the buffer 108 is read, It is written as it is into the corresponding area in the memory 101 (S113). As a result, sector data, PI code, and PO code for one ECC block are mapped in the memory 101, and the encoding process for the ECC block ends.

  The data for one ECC block mapped in the memory 101 in this way is read line by line to the modulation circuit 200 and subjected to predetermined modulation. Then, the recording signal generated by this modulation processing is supplied to the optical pickup 300, and data recording on the disc is performed.

According to the present embodiment, memory access when mapping data for one ECC block to the memory 101 is suppressed to the following three steps.
(1) Writing of scramble data generated by the scramble calculation circuit 105,
(2) writing of the PI code generated by the PI operation circuit 106, and
(3) Write of PO code stored in buffer 108

  Therefore, according to the present invention, the number of memory accesses during the ECC encoding process can be greatly reduced as compared with the case of the above-described prior art, thereby speeding up the data encoding process. .

  In this embodiment, the data mapping method for the memory 101 is improved.

  FIG. 4A shows a state in which sector data, PI code, and PO code are mapped to a memory while maintaining the ECC block data structure.

  In this case, at the time of data recording, data and PI code are read line by line from the head of sector 1 (read 1 in the figure) and output to modulation circuit 200. When all the rows in sector 1 have been read, the PO code corresponding to sector 1 is then read out (read 2 in the figure). When this reading is completed, the process returns to sector 2 and sector 2 The data and the PI code are read line by line from the top of the line. Hereinafter, similarly, the data of each sector and the PI code and PO code are alternately read up to the end of one ECC block and output to the modulation circuit 200.

  As described above, according to the mapping method of FIG. 4A, it is necessary to read data alternately from the sector area and the PO code area at the time of data recording, which causes a problem that access control to the memory 101 becomes complicated. The present embodiment avoids this problem.

  FIG. 4B shows a data mapping method in this embodiment.

  In this mapping method, an area (PO area) for mapping the PO code corresponding to sector m is secured between the mapping area of sector m (m = 1, 2,..., 16) and the mapping area of sector m + 1. Is done. When the PO code for one ECC block is stored in the buffer 108 by the processing of FIG. 3, the PO code corresponding to each sector is read from the buffer 108 and written to the corresponding PO area on the memory 100. It is.

  According to this mapping method, at the time of data recording, data may be read out one line at a time from the first address to the last address of the mapping area and output to the modulation circuit 200. Therefore, according to the present embodiment, access control to the memory 101 at the time of data reading can be simplified as compared with the mapping method of FIG.

  The present embodiment is intended to further reduce the access frequency to the memory 101 compared to the first embodiment. In other words, in the first embodiment, the PO code stored in the buffer 108 is once written in the memory 101, and then the PO code is read from the memory 101 and output to the modulation circuit 200. As shown in the configuration example 5, the PO code stored in the buffer 108 is directly output to the modulation circuit 200 without being written in the memory 101.

  FIG. 6 is a processing flow when data is output to the modulation circuit 200.

  When the processing is started, 1 is set to the variable K (S201). First, data and PI codes for one row are read out sequentially from the head of the sector 1 and output to the modulation circuit 200 (S202). When this output processing is completed for sector 1 (S203: YES), the PO code corresponding to sector 1 is read from buffer 108 and output to modulation circuit 200 (S204).

  When the PO code is read in this way, 1 is added to the variable K (S206), and one row of data and the PI code are sequentially read from the head of the sector 2 and output to the modulation circuit 200 ( S202). When this output processing is completed for sector 2 (S203: YES), the PO code corresponding to sector 2 is read from buffer 108 and output to modulation circuit 200 (S204).

  Thereafter, the same processing is executed up to the sector 16, and data, PI code, and PO code are alternately output from the memory 101 and the buffer 108 to the modulation circuit 200 (S205). When the process for the sector 16 is completed (S205: YES), the process for the ECC block is terminated.

  According to the present embodiment, since the PO code is not written from the buffer 108 to the memory 101, the memory access at the time of writing and the memory access at the time of reading the PO code from the memory 101 are compared with the first embodiment. Reduced. Therefore, according to the present embodiment, compared with the first embodiment, the access frequency to the memory 101 can be further reduced, and the data encoding process can be speeded up.

  Further, according to the present embodiment, since the PO code is not written in the memory 101, the storage area of the memory can be reduced by the storage area of the PO code as compared with the first embodiment. The size can be reduced.

  This embodiment is intended to shorten the time required for encoding processing of data for one ECC block as compared with the first embodiment.

  FIG. 7 shows the configuration of this embodiment. In the present embodiment, one buffer for storing the PO code is added as compared with the first embodiment. In the present embodiment, the buffer used in the PO encoding process is switched between the buffer A 110 and the buffer B 111 for each ECC block.

  FIG. 8 shows the usage state of the buffer A110 and the buffer B111 during the PO encoding process. In the figure, “block” means an ECC block.

  During the encoding process for the block n, the buffer A110 is used as a PO code writing / reading buffer. When the encoding process for the block n is completed, the buffer used during the encoding process is switched from the buffer A110 to the buffer B111. During the encoding process for the next block n + 1, writing / reading of the PO code to / from the buffer B110 is performed. Executed.

  The PO code (PO code for block n) stored in the buffer A 110 is read from the buffer A 110 and written to the memory 101 while the PO encoding process is being performed on the block n + 1. When the encoding process for the block n + 1 is completed, the buffer used during the encoding process is switched again from the buffer B111 to the buffer A110. During the encoding process for the next block n + 2, the PO code is written into the buffer A110. / Reading is executed.

  Thus, according to the present embodiment, the PO code writing process for the memory 101 is performed during the PO encoding process period for the next block, not during the encoding process for the block. Therefore, the time required for the encoding process for each block can be reduced by the amount that the PO code writing process for the memory 101 is not performed. Therefore, according to the present embodiment, it is possible to facilitate data transfer control from the host to the data encoding circuit 100.

  In this embodiment, the data mapping method shown in the second embodiment can be applied. In this way, as described in the second embodiment, memory access control at the time of data reading with respect to the modulation circuit 200 can be simplified.

  This embodiment is intended to reduce the circuit scale and reduce the power consumption compared to the first embodiment.

  FIG. 9 shows the configuration of this embodiment. In the present embodiment, compared to the first embodiment, a buffer (PI buffer 121) for storing data for one row after scramble and the corresponding PI code is added. Further, the PI / PO arithmetic processing circuit 120 is configured to be shared by the PI code and PO code arithmetic processing.

  FIG. 10 shows a processing flow during the encoding process in the present embodiment.

  When data for one sector is input from the host to the scramble operation circuit 105 via the ID addition circuit 102, the IED operation circuit 103, and the EDC operation circuit 104 (S301), the input data is scrambled. The data for one row after the scramble processing is input to the PI / PO arithmetic circuit 120 (S303). Receiving this, the PI / PO operation circuit 120 executes the operation of the PI code (S304), and writes the obtained PI code together with the data for one row in the PI buffer 121 (S305).

  Next, the PI / PO code calculation circuit 120 reads the data and PI code from the PI buffer 121 (S306), and further reads the PO code already stored in the PO buffer 307 from the PO buffer 307. As described with reference to FIG. 2, the PO code calculation is executed (S308). That is, a syndrome calculation formula for calculating the PO code is set from the read PO code, data for one row, and the PI code, and the PO code calculation is executed based on the calculation formula. The PI / PO code calculation circuit 120 writes the PO code calculated thereby back to the PO buffer (S309).

  Thus, when the calculation process of the PO code is performed, the data and PI code stored in the PI buffer 121 are written into the memory 101 (S310). If the processing by the PI / PO arithmetic circuit 120 has not been performed for the data of all the rows in the sector (S311: NO), the processing returns to S303, and the processing for the data of the next row in the sector is executed. .

  This processing is repeated until the processing by the PI / PO arithmetic circuit 120 is performed for the data of all the rows in the sector (S311). When the process for the sector is completed (S311: YES), the process returns to S301 via S311 and the process for the next sector is executed.

  The processing from S301 to S312 is repeatedly executed until the processing for all sectors constituting one ECC block is completed (S312). When the processing for all sectors constituting one ECC block is completed (S312: YES), the PO code stored in the PO code buffer 122 is read and written to the memory 101.

  According to the present embodiment, the calculation processing of the PI code and the PO code is performed by sharing the PI / PO calculation processing circuit 120, so that the calculation processing is individually performed for the PI code and the PO code as in the first embodiment. Compared with the case where a circuit is provided, the circuit scale can be reduced and power consumption can be suppressed.

  In this embodiment, the data mapping method shown in the second embodiment can be applied. In this way, as described in the second embodiment, memory access control at the time of data reading with respect to the modulation circuit 200 can be simplified.

  Also in this embodiment, as shown in the third embodiment, the PO code stored in the PO buffer 122 can be directly output to the modulation circuit 200. In this way, as described in the third embodiment, the access frequency to the memory 101 can be reduced, and the size of the memory 101 can be reduced.

  Further, in this embodiment, as shown in the fourth embodiment, the PO buffer 122 can be constituted by two buffers. In this way, as described in the fourth embodiment, the time required for the encoding process for each block can be shortened, thereby facilitating the data transfer control from the host to the data encoding circuit 100. it can.

  The embodiments of the present invention have been described with reference to various examples. However, the present invention is not limited to these examples. In addition to these examples, various embodiments of the present invention can be envisaged.

  For example, as shown in FIG. 11, buffers 130 and 131 are interposed between the scramble arithmetic circuit 105, the PI arithmetic circuit 106, and the PO arithmetic circuit 107. After data is temporarily stored in these buffers 130 and 131, the data is stored as needed. It is also possible to supply to the PI operation circuit 106 and the PO operation circuit 107.

  In the above embodiment, the configuration example and the processing operation when the present invention is applied to the DVD recording apparatus are illustrated, but the present invention can also be applied to the HDDVD recording apparatus.

  In addition, the embodiments of the present invention can be variously modified within the scope of the invention described in the claims.

1 is a diagram illustrating a configuration of a disk recording apparatus according to a first embodiment. FIG. 6 is a diagram for explaining the processing operation of the PO arithmetic circuit according to the first embodiment. Process Flowchart of Data Encoding Circuit According to Embodiment 1 FIG. 6 is a diagram for explaining a data mapping method according to the second embodiment. FIG. 10 is a diagram illustrating a configuration of a disk recording apparatus according to a third embodiment. Flowchart for supplying data to the modulation circuit according to the third embodiment. The figure which shows the structure of the disc recording device based on Example 4. FIG. FIG. 6 is a diagram for explaining how to use the buffers A and B according to the fourth embodiment. FIG. 10 is a diagram illustrating a configuration of a disk recording device according to a fifth embodiment. Process Flowchart of Data Encoding Circuit According to Embodiment 5 The figure which shows the example of a change of the disk recording device which concerns on embodiment The figure which shows the data structure of the ECC block in a DVD recording device The figure which shows the flow of a general process until an ECC block is comprised.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Data encoding circuit 101 Memory 105 Scramble arithmetic circuit 106 PI arithmetic circuit 107 PO arithmetic circuit 110 Buffer A (1st buffer)
111 Buffer B (second buffer)
121 PI buffer 122 PO buffer

Claims (10)

A scramble operation unit that scrambles data input from the host;
A row direction error correction code calculation unit for generating a row direction error correction code from the scrambled data; and
A column-direction error correction code calculation unit that generates a column-direction error correction code from the scrambled data and the row-direction error correction code;
A buffer for storing a column-direction error correction code generated by the column-direction error correction code calculation unit;
A memory for storing the scrambled data and the error correction code in the row direction and the error correction code in the column direction;
The column-direction error correction code calculation unit receives the scrambled data from the scramble calculation unit, or receives the row-direction error correction code from the row-direction error correction code calculation unit. In response, the error correction code in the column direction stored in the buffer is read, and the error correction code in the column direction is newly calculated from the read error correction code in the column direction and the input data or the error correction code in the row direction. And write back to the buffer,
After the error correction code in the column direction for the error correction unit is stored in the buffer in the calculation process by the error correction code calculation unit in the column direction, the error correction code in the column direction is read from the buffer, Stored in memory,
A data encoding circuit characterized by the above. The data encoding circuit according to claim 1, wherein
In the memory, storage areas for the data, the error correction code in the row direction, and the error correction code in the column direction are set in order from the top address according to the reading order to the modulation circuit, and the column stored in the buffer The direction error correction code is respectively stored in the storage area of the corresponding column direction error correction code on the memory.
A data encoding circuit characterized by the above. The data encoding circuit according to claim 1 or 2,
The buffer is composed of a first buffer and a second buffer, and a buffer used at the time of calculation processing in the error correction code calculation unit in the column direction is the first buffer and the buffer for each error correction unit. Switched between the second buffer,
The error correction code in the column direction stored in one of the two buffers is read during a period in which the other buffer is used during the calculation process in the error correction code calculation unit in the column direction. Stored in memory,
A data encoding circuit characterized by the above. A scramble operation unit that scrambles data input from the host;
A row direction error correction code calculation unit for generating a row direction error correction code from the scrambled data; and
A column-direction error correction code calculation unit that generates a column-direction error correction code from the scrambled data and the row-direction error correction code;
A buffer for storing a column-direction error correction code generated by the column-direction error correction code calculation unit;
A memory for storing the scrambled data and the error correction code in the row direction;
The column-direction error correction code calculation unit receives the scrambled data from the scramble calculation unit, or receives the row-direction error correction code from the row-direction error correction code calculation unit. In response, the error correction code in the column direction stored in the buffer is read, and the error correction code in the column direction is newly calculated from the read error correction code in the column direction and the input data or the error correction code in the row direction. And write back to the buffer,
After the column-direction error correction code corresponding to the error correction unit is stored in the buffer in the calculation process by the column-direction error correction code calculation unit, the data and the row-direction error correction code from the memory one row at a time Are output to the modulation circuit, and at the output timing of the error correction code in the column direction between the outputs, the error correction code in the column direction is read from the buffer one row at a time and output to the modulation circuit. The
A data encoding circuit characterized by the above. A scramble operation unit that scrambles data input from the host;
A PI / PO arithmetic unit that generates a row direction error correction code from the scrambled data, and generates a column direction error correction code from the scrambled data and the row direction error correction code;
A PI buffer for storing a row-direction error correction code generated by the PI / PO operation unit together with the data corresponding to the row-direction error correction code;
A PO buffer for storing a column-direction error correction code generated by the PI / PO operation unit;
A memory for storing the scrambled data and the error correction code in the row direction and the error correction code in the column direction;
The PI / PO operation unit reads the data and the error correction code in the row direction from the PI buffer and stores the error correction code in the PO direction in the column direction during the calculation process of the error correction code in the column direction. Read a column direction error correction code, generate a new column direction error correction code from the read data and row direction error correction code and the column direction error correction code, and write back to the buffer,
When the PI / PO operation unit performs the error correction code processing in the column direction, the data and the error correction code in the row direction are read from the PI buffer and stored in the memory.
After the column-direction error correction code for the error correction unit is stored in the PO buffer in the column-direction error correction code calculation processing by the PI / PO operation unit, the column-direction error is output from the PO buffer. A correction code is read and stored in the memory;
A data encoding circuit characterized by the above. The data encoding circuit according to claim 5, wherein
In the memory, storage areas for the data, the error correction code in the row direction, and the error correction code in the column direction are set sequentially from the top address according to the reading order to the modulation circuit, and stored in the PO buffer. The column-direction error correction codes are respectively stored in storage regions of corresponding column-direction error correction codes on the memory.
A data encoding circuit characterized by the above. The data encoding circuit according to claim 5 or 6,
The PO buffer is composed of a first buffer and a second buffer, and a buffer used when calculating the error correction code in the column direction in the PI / PO operation circuit is provided for each error correction unit. Switched between the first buffer and the second buffer;
The error correction code in the column direction stored in one of these two buffers is read and stored in the memory during a period in which the other buffer is used during arithmetic processing in the PO arithmetic circuit. ,
A data encoding circuit characterized by the above. A scramble operation unit that scrambles data input from the host;
A PI / PO operation unit for generating an error correction code in a row direction and an error correction code in a column direction from the scrambled data;
A PI buffer for storing a row-direction error correction code generated by the PI / PO operation unit together with the data corresponding to the row-direction error correction code;
A PO buffer for storing a column-direction error correction code generated by the PI / PO operation unit;
A memory for storing the scrambled data and the error correction code in the row direction;
The PI / PO operation unit reads the data and the error correction code in the row direction from the PI buffer and stores the error correction code in the PO direction in the column direction during the calculation process of the error correction code in the column direction. Read a column direction error correction code, generate a new column direction error correction code from the read data and row direction error correction code and the column direction error correction code, and write back to the buffer,
When the PI / PO operation unit performs the error correction code processing in the column direction, the data and the error correction code in the row direction are read from the PI buffer and stored in the memory.
After the column-direction error correction code corresponding to the error correction unit is stored in the PO buffer in the column-direction error correction code calculation processing by the PI / PO operation unit, the data and the data are stored one line at a time from the memory. An error correction code in the row direction is output to the modulation circuit, and the error correction code in the column direction is read from the PO buffer one row at a time at the output timing of the error correction code in the column direction between the outputs. And output to the modulation circuit,
A data encoding circuit characterized by the above.   A data recording apparatus comprising the data encoding circuit according to any one of claims 1 to 8. A PI calculation step of generating an error correction code in a row direction from input data, writing the generated error correction code in the row direction in a memory, and serving for calculation of an error correction code in a column direction;
A PO operation step of generating an error correction code in the column direction from the input data and the error correction code in the row direction, and writing the generated error correction code in the column direction into a buffer;
A PO writing step of reading the error correction code in the column direction from the buffer and writing it in the memory after the error correction code in the column direction for the error correction unit is stored in the buffer;
The PO operation step stores the generated error correction code in the column direction in the buffer, and the column stored in the buffer in response to the input of the data or the error correction code in the row direction. A direction error correction code is read out, a column direction error correction code is newly generated from the read column direction error correction code and the input data or row direction error correction code, and written back to the buffer.
A PI / PO calculation processing method characterized by the above.

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