JP2004348824A - ECC encoding method and ECC encoding device - Google Patents

Abstract

An ECC encoding method and apparatus for adding an ECC for correcting an error in digital data to recorded digital data, in which ECC generation and addition are performed at high speed.
A first step of calculating a first parity of one row in a horizontal direction with respect to data having a horizontal and vertical block structure by a first calculation circuit and adding the same in a horizontal direction, and performing the first step for each row. While the first step is performed, the second parity of one column in the vertical direction is calculated by the second calculation circuit for the data to which the first parity is added, and the second step is performed for each column. Is provided.
[Selection diagram] Fig. 1

Description

これはα^０〜α^９までの連続する１０個の成分が根となる符号系列を生成するための式である。ＰＩパリティを付加するには、この生成多項式で１７２バイトからなる情報多項式を割り、その余りを情報多項式に付加すればよい。
【００４４】
このような付加処理を回路的に行なうには、図５に示すような構成を有するＰＩパリティ生成回路（第１の計算回路）を用いることができる。このＰＩパリティ生成回路は、シフトレジスタによる除算回路を表しており、図中のＤがシフトレジスタ５４、…５７を、×α^ｎがガロア体の乗算回路５１、…５３（ガロア乗算器）を、それぞれを示している。符号５８、５９、６０等は排他的論理和を求める演算回路（排他的論理和ゲート）である。なお、図５に示す構成による各部の演算やレジスト操作は、８ビット（１バイト）をひとつのデータ単位として行なう。
【００４５】
動作としては、まず、ＳＷａを閉じてＳＷｂを１側に倒し、入力端子から情報データＨ_ｘ（ｘ＝０〜１７１）を順にシフトレジスタ５４、…５７に入力していく。また、同時に出力端子（ＳＷｂの共通端側）から入力データをそのまま出力させていく。１７２バイト全てのデータを入力および出力し終えたら、ＳＷａを開放してＳＷｂを２側に倒し、シフトレジスタ５４、…５７内に生成されたパリティデータ１０バイトをさらに出力端子より順次出力していく。これによりパリティ付データＩ_ｘ（０〜１８１）が生成される。
【００４６】
１８２バイトの出力データは、ＲＡＭ制御部２０６を通過してＲＡＭ２０７に順次格納されていき、この動作を１９２回繰り返すことによって図６に示すようなＰＯパリティなしのＥＣＣブロック（１８２バイト×１９２行）が生成される。なお、メモリとしてのＲＡＭ２０７には大容量で安価なＤ−ＲＡＭを用いるのが通常は得策である。
【００４７】
また一方、この１８２バイト×１９２行の出力データはＲＡＭ２０７への格納と並行してＰＯパリティ生成回路２０４にも転送されており、ＰＯパリティ生成回路２０４では、ＰＯ系列の１８２列におけるパリティ計算をリアルタイムで行なっている。ここでＰＯパリティの生成方法について説明する。
【００４８】
ＰＯパリティの生成多項式はＰＩと同様に以下のような式で表すことができる。

【００４９】
これは、α^０〜α^１５までの連続する１６個の成分が根となる符号系列を生成するための式であることを表している。ＰＯパリティ計算の原理自体はＰＩパリティの場合とほぼ同様であるが、ＰＯパリティ生成回路２０４の構成は、ＰＩパリティ生成回路２０３と同様とするわけにはいかない。これは、ＰＩ系列がＥＣＣブロックの行方向、つまりデータストリーム方向の系列であり、１０バイトのＰＩパリティ生成のために必要な情報データ１７２バイトが連続で転送されるのに対し、ＰＯ系列はＥＣＣブロックの列方向の系列であるので必要な情報データが連続では転送されないためである。
【００５０】
すなわち、ＰＩパリティ生成回路２０３は連続する１７２バイトからＰＩパリティを計算すればよいのに対し、ＰＯパリティ１６バイトを生成するために必要な情報データ１９２バイトは、受信データ１８２バイトごとに１バイトしか得られない。さらに、他の１８１バイトは各々異なったＰＯ列の情報データである。そこで、ＰＯパリティ生成回路２０４は、入力データＪ_ｘ（１８２バイト×１９２行）を用いて１８２列分のＰＯパリティ計算を、入力１バイトごとに随時切り替えながら計算するように構成する。
【００５１】
ここで、ＰＯパリティ生成回路２０４の構成および動作について図７、図８を参照して説明する。図７は、図１中に示すＰＯパリティ生成回路２０４の構成および動作をやや詳細に説明するブロック図である。図８は、図７に示すＰＯパリティ生成回路などの動作フローを示す流れ図である。図７において、図１中に示した構成要素と同一のものには同一符号を付してある。
【００５２】
入力データＪ_ｘ（１８２バイト×１９２行）は、１バイト単位でＰＯパリティ生成コントローラ７０１とＰＯパリティ計算回路７０２（第２の計算回路）に転送される。ＰＯパリティ生成コントローラ７０１は、１８２バイトカウンタを有し、入力された情報データがどのＰＯ列であるか認識してＰＯパリティ計算回路７０２とＰＯパリティ用バッファ２０５の入出力とをコントロールしている。ここでＰＯパリティ用バッファ２０５の入出力のコントロールは、インターフェース７０３を介してなされる。
【００５３】
ＰＯパリティ計算回路７０２は、内部にＤ_０〜Ｄ_１５の１６個のレジスタとガロア乗算器とを有し、図７中のＰＯパリティ計算回路７０２下に示した表のように除算計算を行なっている（図８のステップ８０１）。この除算計算は、図５に示したＰＩパリティ回路と同様の構成原理によるものである。図７中の表において、Ｄ_ｎａが計算後のＤ_ｎの値である（ｎ＝０〜１５）。
【００５４】
計算すべきＰＯ列は１バイトごとに切り替わるため、上記１６個のレジスタの内部データも１バイトごとにＰＯパリティ用バッファ２０５に退避させる必要がある（ステップ８０４）。そして、１８２バイト後に同一ＰＯ列の情報データが転送されてきたら、上記バッファ２０５より途中結果を読み出し（ステップ８０２）、内部のレジスタＤ_０〜Ｄ_１５へデータを移行させ、再度ＰＯパリティ計算を行う（ステップ８０３）。この動作を１９２回繰り返すことで（ステップ８０５のＹ）、ＰＯ系列の１列のＰＯパリティ計算が完成する。
【００５５】
さらに同様の計算を残り１８１のＰＯ列に対しても連続で行なっており、入力データＪ_ｘ（１８２バイト×１９２行）が全て入力された時点で、全てのＰＯ列におけるＰＯパリティ計算が終了し、パリティデータはＰＯパリティ用バッファ２０５に格納された状態となる。これと同時にＪ_ｘのＲＡＭ２０７への格納も終了している。すなわち、この時点で、図３に示すＥＣＣブロックのうち情報データおよびＰＩパリティの部分がＲＡＭ２０７に格納され、ＰＯパリティの部分がＰＯパリティ用バッファ２０５に格納された状態となる。
【００５６】
なお、図３に示すＥＣＣブロックはＤＶＤ規格であり、そのＰＯ方向の誤り訂正符号は、符号長２０８バイト、情報長１９２バイト、最小距離１７であり、ＰＩ方向の誤り訂正符号は、符号長１８２バイト、情報長１７２バイト、最小距離１１である。
【００５７】
続いて、ＥＣＣエンコード処理が終了したＥＣＣブロックデータに対してＰＯパリティインターリーブ用セレクタ２１１によりインターリーブ処理を施し、これを変調回路２０８に転送する。インターリーブ処理は、ＰＩパリティ付セクタデータ２１８４バイト（１８２バイト×１２行）ごとにＰＯパリティ部のＰＩ方向データ１８２バイトを付加していく処理で、１６セクタ分行なう。この実施形態においては、ＲＡＭ制御部２０６からの出力であるＰＩパリティ付セクタデータ２１８４バイトと、ＰＯパリティ用バッファ２０５からの出力１８２バイトをインターリーブ用セレクタ２１１で１６セクタごとに切り替えて行なう。
【００５８】
以上の処理で、図２における処理手順３０６までが終了する。すなわち、上記１６セクタに対応して１６の記録フレームが生成される。
【００５９】
なお、インターリーブ処理の別の形態として、ＰＯパリティ用バッファ２０５内に完成されたＰＯパリティデータを一度ＲＡＭ制御部２０６を介してＲＡＭ２０７内へインターリーブ処理を施すように格納してもよい。この場合には、ＲＡＭ２０７の容量は、ＰＯパリティデータをも格納できるような大きさにしておく。これにより、ＲＡＭ２０７に格納されたデータは、ＰＯパリティインターリーブ用セレクタ２１１を介することなく変調回路２０８へ出力することができる。ただし、上記セレクタ２１１を用いる場合よりもＲＡＭ２０７へのアクセス回数は増える。
【００６０】
インターリーブの後、図２における処理手順３０７までの処理として、変調回路２０８において、転送されたデータに対して同期コード（ＥＣＣブロックひとつを２６の同期フレームにする）を付加し、ＤＶＤの変調規則である８／１６変調処理を行い、記録補償回路２０９へ転送する。記録補償回路２０９では、変調回路２０８からのバイナリ変調データ信号に記録補償を施す。ＰＵＨ２１０では、記録補償されたバイナリ変調データ信号に基づきレーザードライバを駆動させ、記録対応ディスク２１２上に記録マークを形成していく。
【００６１】
以上のように、本実施形態におけるＥＣＣエンコード装置では、ＰＩパリティ生成計算およびＰＯパリティ生成計算を、ＥＣＣ用データのＲＡＭ２０７へのデータ格納処理と並行して行なうことで、パリティ計算のためのＲＡＭ２０７からの情報データ読み出し／書き込み処理が全く省かれる。これにより、高倍速化を容易に可能とするＥＣＣエンコード処理が実現できる。
【００６２】
次に、本発明の別の実施形態に係るＥＣＣエンコード装置について図９を参照して説明する。図９は、本発明の別の実施形態に係るＥＣＣエンコード装置を記録型ＤＶＤ装置に適用した場合の記録系構成を示すブロック図である。図９において、すでに説明した構成要素と同一のものには同一符号を付してある。以下ではその部分の重複を避けて説明する。
【００６３】
この実施形態では、ＰＩパリティの生成と並行するＰＯパリティの生成に少なくとも「ＰＯシンドローム生成回路」および「ＥＣＣデコード回路」を用いる。これらの回路自体は、入出力される信号という観点では、ＤＶＤ装置の再生回路で一般的に用いられているものと同一の機能である。さらに、「ＰＯシンドローム生成回路」を「ＰＯシンドローム用バッファ」と組み合わせることにより、ＲＡＭ２０７へのデータ格納と並行して「ＰＯシンドローム生成回路」を動作させ、パリティ計算のためのＲＡＭ２０７へアクセスを省略できるようにしたものである。
【００６４】
図９に示すように、この記録型ＤＶＤ装置は、すでに説明した構成要素のほか、ＰＯシンドローム生成回路９０４、ＰＯシンドローム用バッファ９０５、ＥＣＣデコード回路９０６を有し、これらが図１に示した実施形態のＰＯパリティ生成回路２０４およびＰＯパリティ用バッファ２０５の代わりに設けられる。
【００６５】
ＰＯシンドローム生成回路９０４は、ＰＩパリティ生成回路２０３の出力のＲＡＭ２０７への格納と並行して、所定の手順によりＰＯシンドロームを生成するものである。並行してＰＯシンドロームを生成するので、ＲＡＭ２０７に３４９４４バイト（１８２バイト×１９２行）のデータ格納が完了した時点で、ＰＯシンドロームが生成される。ＰＯシンドロームは、３４９４４バイトの縦方向１９２バイト（仮想的に加えた適当な１６バイトを含めて２０８バイト）に対して１６バイトずつ生成され、ひとつのＥＣＣブロックについて１６行×１８２＝２９１２バイトのデータサイズになる。
【００６６】
ＰＯシンドローム用バッファ９０５は、ＲＡＭ２０７へのデータ格納と並行して、ＰＯシンドローム生成回路９０４がＰＯシンドロームを上記のように生成するために必要なバッファとして機能するメモリである。そのサイズはちょうど上記の１６行×１８２＝２９１２バイトである。すなわち、ＰＯシンドローム生成回路２０４は、ＰＯシンドローム用バッファ９０５をワークエリアとして用い、ＰＩパリティ生成回路２０３の出力のＲＡＭ２０７への３４９４４バイトのデータ格納が完了した時点で格納されたデータが、ＰＯシンドロームとなるようにデータを出し入れしながら計算を行なう。
【００６７】
ＥＣＣデコード回路９０６は、ＰＯシンドローム用バッファ９０５に格納されたＰＯシンドロームに基づきイレージャ訂正を行なうものである。このイレージャ訂正により、ＰＯシンドロームの生成時に適当に加えたデータの領域にＰＯパリティ（１６行×１８２＝２９１２バイト）が生成される。生成されたＰＯパリティは、ＰＯシンドローム用バッファ９０５に上書き格納される。上書き格納されたＰＯパリティは、その後ＰＯシンドローム用バッファ９０５からＰＯパリティインターリーブ用セレクタ２１１に導かれる。
【００６８】
図１０は、図９中に示すＰＯシンドローム生成回路９０４の構成および動作をやや詳細に説明するブロック図である。図１１は、図１０中に示すＰＯシンドローム計算回路１００２の具体的な構成例を示す図である。図１２は、図１０に示すＰＯシンドローム生成回路などの動作フローを示す流れ図である。
【００６９】
以下、図９とともに、図１０ないし図１２をも必要に応じて参照し、本実施形態に係るＥＣＣエンコード装置の動作説明を行なう。
【００７０】
図９において、ＰＩパリティ生成回路２０３の１８２バイト×１９２行の出力データはＲＡＭ２０７への格納と並行してＰＯシンドローム生成回路９０４にも転送されており、ＰＯシンドローム生成回路９０４では、ＰＯ系列の１８２列におけるシンドローム計算を１バイトごとに切り替えてリアルタイムで行なっている。ＰＯ系列の１データ列におけるシンドロームＳ_０〜Ｓ_１５は以下に示す式で計算することができる。ただし、Ｉ_ｘ（ｘ＝０〜２０７）はここではＰＯ系列の符号データ列２０８バイトを表す。
Ｓ_０＝Ｉ_０＋Ｉ_１＋…＋Ｉ_２０６＋Ｉ_２０７
Ｓ_２＝Ｉ_０α^２０７＋Ｉ_１α^２０６＋…＋Ｉ_２０６α＋Ｉ_２０７
・
・
・
Ｓ_１５＝Ｉ_０α^{１５×２０７}＋Ｉ_１α^{１５×２０６}＋…＋Ｉ_２０６α^１５＋Ｉ_２０７
【００７１】
また、これらの計算式でもわかるようにシンドロームを計算するためには２０８バイトの符号データ列が必要であり、入力されてくる１９２バイトでは１６バイト分足りない。不足分の１６バイトのデータは後のＥＣＣデコード処理によって訂正されると結果としてＰＯパリティになるので当初は任意のデータで構わない。ここでは、これを０データで埋めることにより計算処理の効率的を図る。
【００７２】
不足分の１６バイトを０データとして処理するためのＰＯシンドローム計算回路１００２（第２の計算回路：図１０を参照）を図１１を用いて説明する。図１１において、破線で囲まれた部分は、シンドロームを生成するため再生回路で通常用いられている周知の部分である。
【００７３】
すなわち、フリップフロップ（レジスタＤ_ｘ 、ｘ＝０〜１５）１１２〜１１８それぞれの出力をガロア乗算器１１５〜１１９に導き（ただしフリップフロップ１１２についてはガロア乗算器は「１」に相当）、ガロア乗算器１１５〜１１９等の出力を排他的論理和ゲート１１１〜１１７の一方の入力とする。排他的論理和ゲート１１１〜１１７の他方の入力側には入力データＩ_ｘが共通に入力され、排他的論理和ゲート１１１〜１１７の出力がフリップフロップ（レジスタＤ_ｘ）１１２〜１１８それぞれの入力とされる。なお、図１１に示す構成による各部の演算や動作は、８ビット（１バイト）をデータ単位として行なう。
【００７４】
図１１中、破線で囲まれた、フリップフロップ（レジスタＤ_ｘ）１１２〜１１８とガロア乗算器１１５〜１１９と排他的論理和ゲート１１１〜１１７とからそれぞれがなる各回路に１９２バイトの入力データを順次入力すると、フリップフロップ（レジスタＤ_ｘ）１１２〜１１８にはこの１９２バイトによるシンドローム計算途中結果が以下の式Ｓ_０ａ〜Ｓ_１５ａのように生成される。
Ｓ_０ａ＝Ｉ_０＋Ｉ_１＋…＋Ｉ_１９０＋Ｉ_１９１
Ｓ_２ａ＝Ｉ_０α^１９１＋Ｉ_１α^１９０＋…＋Ｉ_１９０α＋Ｉ_１９１
・
・
・
Ｓ_１５ａ＝Ｉ_０α^{１５×１９１}＋Ｉ_１α^{１５×１９０}＋…＋Ｉ_１９０α^１５＋Ｉ_１９１
【００７５】
この式と上述のシンドローム計算式とを比較し、さらにＩ_１９２〜Ｉ_２０７が０とすると、シンドローム計算を成立させるためには各々のシンドローム計算途中結果に対してα^１６×ｍ（ｍ＝０〜１５：シンドローム番号）を乗じればよいことがわかる。このため、図１１に示す回路（ＰＯシンドローム計算回路１００２）においては、１９２クロック経過後にＳＷ０〜ＳＷ１５を閉じることで、シンドローム計算を完了させるようガロア乗算器１１６、…、１２０が置かれる仕組みとなっている。
【００７６】
このような演算を行うＰＯシンドローム計算回路１００２であるが、先に説明した実施形態と同じようにＰＯシンドローム生成回路９０４全体としてはＰＯ１８２列のシンドローム計算を１バイトごとに切り替えて演算していかなければならない。このため、レジスタＤ_０〜Ｄ_１５の内容をＰＯシンドローム用バッファ９０５に退避させながら実施する。
【００７７】
図１０は、図９中に示すＰＯシンドローム生成回路９０４の構成および動作をやや詳細に説明するブロック図である。図１０中には、ＰＯシンドローム生成回路９０４に対応する部分のほかに、ＰＯシンドローム用バッファ９０５、ＥＣＣデコード回路９０６も示している。
【００７８】
入力データＪ_ｘ（１８２バイト×１９２行）が１バイト単位でＰＯシンドローム生成コントローラ１００１とＰＯシンドローム計算回路１００２に転送される（図１２のステップ１２０１）。ＰＯシンドローム生成コントローラ１００１は１８２バイトカウンタを有し、入力された情報データがどのＰＯ列であるか認識してＰＯシンドローム計算回路１００２とＰＯシンドローム用バッファ９０５の入出力をコントロールしている。ここでＰＯシンドローム用バッファ９０５の入出力のコントロールは、インターフェース１００３を介してなされる。
【００７９】
また、計算すべきＰＯ列は１バイトごとに切り替わるため、１６個のレジスタＤ_ｘ（ｘ＝０〜１５）の内部データも１バイトごとにＰＯシンドローム用バッファ９０５に退避させる必要がある（ステップ１２０４）。そして、１８２バイト後に同一ＰＯ列の情報データが転送されてきたら、上記バッファ９０５より途中結果を読み出し（ステップ１２０２）、内部のレジスタＤ_ｘ（ｘ＝０〜１５）へデータを移行させ、再度ＰＯシンドローム計算を行う（ステップ１２０３）。この動作を１９２回繰り返し、最後に前述した図１１のＳＷ０〜ＳＷ１５を閉じることにより、ＰＯ系列の１列のＰＯシンドローム計算が完成する（ステップ１２０５のＹ）。
【００８０】
さらに、同様の計算を残りの１８１のＰＯ列に対しても連続で行なっており、入力データＪ_ｘ（１８２バイト×１９２行）が全て入力された時点で、全てのＰＯ列におけるＰＯシンドローム計算が終了し、シンドロームデータはＰＯシンドローム用バッファ９０５に格納された状態となる。これと同時にＪ_ｘのＲＡＭ２０７への格納も終了している。
【００８１】
続いて、作成されたＰＯシンドロームをバッファ９０５から読み出してＥＣＣデコード回路９０６に転送し（ステップ１２０６）、ＥＣＣデコード回路９０６によるエラー訂正処理を行なう（ステップ１２０７）。言い換えると上記処理（ＰＯシンドローム計算回路１００２での処理）では０データとして埋めた１６バイトを、生成すべきＰＯパリティ１６バイトに変換する。なお、ＥＣＣデコード回路９０６は、周知のようにシンドローム修正回路、ユークリッド計算回路、チェーンサーチ回路などを有するものである。
【００８２】
上記エラー訂正処理については、通常、ＰＯ系列の訂正能力が８バイトまでであり、８バイトを超えるエラーは訂正することはできないが、エラーの位置情報（イレージャポインタ）を用いれば１６バイトまでのエラー訂正処理が可能である。これを消失訂正（イレージャ訂正）と一般的にはいう。この実施形態においては、生成すべきＰＯパリティの位置が符号列の末尾１６バイトと確定しているため、エラー位置からイレージャポインタを生成しておけば訂正処理、つまりＰＯパリティ生成が可能である。
【００８３】
より具体的には、ＰＯシンドローム用バッファ９０５より、所望のシンドロームデータをＥＣＣデコードコントローラ１００４によって選択して、ＥＣＣデコード回路９０６へ送る。そして、ＥＣＣデコード回路９０６ではイレージャポインタによりシンドローム修正処理を行った後、チェーンサーチ処理によりエラー位置におけるエラーパターン（つまりはＰＯパリティ）を算出する。
【００８４】
次に、ＥＣＣデコードコントローラ１００４は、算出したＰＯパリティを、エラー位置に基づいてＰＯシンドローム用バッファ９０５上の呼び出してきたシンドローム領域に上書きしていく（ステップ１２０８）。この処理を全ＰＯ系列において実行することによりＰＯシンドローム用バッファ９０５には全ＰＯ系列のパリティデータが完成する。ＰＯシンドローム用バッファ９０５内に完成されたＰＯパリティデータは、先の実施形態におけるＰＯパリティ用バッファ２０５内に完成されるＰＯパリティデータと同様にその後の処理に用いられる。
【００８５】
なお、ここでの説明では、生成されたＰＯパリティをシンドローム用バッファ９０５に書き込む場合について述べたが、ＲＡＭ制御部２０６を介してＲＡＭ２０７を書き込んでも構わない。この場合には、ＲＡＭ２０７の容量は、ＰＯパリティデータをも格納できるような大きさにしておく。ＲＡＭへの書き込みの際、ＰＯパリティのインターリーブ処理を施すように格納してもよい。
【００８６】
以上説明のようにこの実施形態におけるＥＣＣエンコード装置では、ＰＩパリティ生成計算とＰＯシンドローム計算を、ＥＣＣ用データＲＡＭ２０７へのデータ格納処理と並行して行い、さらにＰＯパリティ生成のためのＥＣＣデコード処理に関してもＲＡＭ２０７へのアクセスが省かれる。これにより、高倍速化を容易に可能とするＥＣＣエンコード処理が実現できる。
【００８７】
また、ＰＯシンドローム回路９０４やＥＣＣデコード回路９０６、ＰＯシンドローム用バッファ９０５は、再生系の回路として用いることもできる。したがって、記録再生系全体として回路規模を削減するのにも効果がある。
【００８８】
また、上記実施形態では、ＰＯパリティの方を、シンドローム生成回路を用いてＥＣＣデコード回路により生成したが、ＰＩパリティに関しても同様にシンドローム生成回路およびＥＣＣデコード回路を用いて生成することができる。この場合には別途ＰＩシンドローム用バッファを設け、また、ＰＩパリティ部のシンドローム計算およびＥＣＣデコード回路によるＰＩパリティ計算の処理手順が追加される。このため処理速度では上記各実施形態に劣るものの、再生系回路との更なる兼用を行なうことで回路規模の削減を図ることができる。
【００８９】
【発明の効果】
以上詳述したように、本発明によれば、横方向の第１のパリティの発生・付加と、縦方向の第２のパリティの発生・付加のための処理とが並行的になされる。よって、第１のパリティを付加してデータを一旦メモリに格納する、格納されたデータにアクセスして第２のパリティの発生・付加を行なう、という２段階の処理の必要がないので、ＥＣＣ生成・付加を高速に行なうことが可能になる。
【図面の簡単な説明】
【図１】本発明の一実施形態に係るＥＣＣエンコード装置を記録型ＤＶＤ装置に適用した場合の記録系構成を示すブロック図。
【図２】図１に示す記録系構成によりなされる処理手順を機能的に説明する機能ブロック図。
【図３】ひとつのＥＣＣブロックの構成を示す図。
【図４】図３に示すＥＣＣブロックにおけるＰＩおよびＰＯパリティを除いた部分（情報データ部分）を構成する単位であるセクタ（１６セクタで図３に示す情報データになる）の内部構成を示す図。
【図５】図１中に示すＰＩパリティ生成回路２０３の具体的な構成例を示す図。
【図６】図１中に示すＲＡＭ２０７に格納されるデータの構成を示す図。
【図７】図１中に示すＰＯパリティ生成回路２０４の構成および動作をやや詳細に説明するブロック図。
【図８】図７に示すＰＯパリティ生成回路などの動作フローを示す流れ図。
【図９】本発明の別の実施形態に係るＥＣＣエンコード装置を記録型ＤＶＤ装置に適用した場合の記録系構成を示すブロック図。
【図１０】図９中に示すＰＯシンドローム生成回路９０４の構成および動作をやや詳細に説明するブロック図。
【図１１】図１０中に示すＰＯシンドローム計算回路１００２の具体的な構成例を示す図。
【図１２】図１０に示すＰＯシンドローム生成回路などの動作フローを示す流れ図。
【符号の説明】
５１、５２、５３…ガロア乗算器 ５４、５５、５６、５７…シフトレジスタ５８、５９、６０…排他的論理和ゲート １１１、１１３、１１７…排他的論理和ゲート １１２、１１４、１１８…レジスタ １１５、１１９…ガロア乗算器 １１６、１２０…ガロア乗算器 ２０１…ホスト ２０２…（ＩＥ＋ＩＥＤ＋ＲＳＶ）付加回路・スクランブル回路・ＥＤＣ付加回路 ２０３…ＰＩパリティ生成回路 ２０４…ＰＯパリティ生成回路 ２０５…ＰＯパリティ用バッファ２０６…ＲＡＭ制御部 ２０７…ＲＡＭ ２０８…変調回路 ２０９…記録補償回路 ２１０…ピックアップヘッド ２１１…ＰＯパリティインターリーブ用セレクタ ２１２…記録対応ディスク ７０１…ＰＯパリティ生成コントローラ７０２…ＰＯパリティ計算回路 ７０３…インターフェース ９０４…ＰＯシンドローム生成回路 ９０５…ＰＯシンドローム用バッファ ９０６…ＥＣＣデコード回路 １００１…ＰＯシンドローム生成コントローラ １００２…ＰＯシンドローム計算回路 １００３…インターフェース １００４…ＥＣＣデコードコントローラ[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an ECC encoding method and apparatus for adding an error correction code (ECC) for correcting errors in digital data to recorded digital data, and more particularly to an ECC encoding method suitable for performing high-speed ECC addition. The present invention relates to an encoding method and apparatus.
[0002]
[Prior art]
2. Description of the Related Art In digital fields such as communication, computers, broadcasting, and video media, error correction codes are generally used for improving data reliability and increasing recording density in a recording system. In particular, recently, an error correction code having a high correction capability has been used with an improvement in data processing capability.
[0003]
Even in a DVD (digital versatile disc) reproducing apparatus that provides high-quality video, an error correction code called a Reed-Solomon (RS) product code having a high correction capability is used, and an error generated in a transmission system can be corrected. ing. The product code is a combination of error correction codes in different vertical and horizontal directions, and is a block composed of a PI (parity inner) parity of an inner code added in the horizontal direction of a block of information data, and information data and PI parity. And a PO (parity outer) parity of an outer code added in the vertical direction of the data. The block composed of the information data, the PI parity, and the PO parity thus configured is an ECC block.
[0004]
As a configuration and an example of an error correction process at the time of reproducing a DVD performed using such an ECC block, there is a method described in Patent Document 1 below. An example of an ECC encoding process required in a remarkable recording type DVD device that has recently become widespread, that is, a parity generation processing method of generating and adding a PI and a PO parity to information data is described in Patent Document 2 below. There is.
[0005]
[Patent Document 1]
JP-A-2002-74861
[Patent Document 2]
JP 2001-319431 A
[0006]
[Problems to be solved by the invention]
The recordable DVD devices as described above have begun to spread mainly for AV (audio visual) applications. In particular, recently, a hybrid DVD recorder, which is a combination of a hard disk drive (HDD) with high accessibility and a large capacity, and a recordable DVD specialized for storage / removable use, has been gaining popularity.
[0007]
One of the features of the DVD is that it has a large storage capacity as compared with a CD (compact disc), but on the other hand, because of its large capacity, the data can be read at the same speed (for example, in the case of video, the speed of normal reproduction). In the case of recording by using, an enormous amount of time is required for the writing process. That is, in the DVD recorder, the user waits a long time for dubbing the video data recorded on the HDD to the DVD.
[0008]
For this reason, there is a demand for a recordable DVD device that is compatible with "high-speed recording" for recording data on a disk at a high speed, like a record-type CD device that is currently mainstream. In order to cope with such “high-speed recording” on the device side, it is necessary to speed up the ECC encoding process performed at the time of the writing process. For example, an ECC data buffer (which is a bottleneck in speeding up) is required. A problem is how to reduce the number of accesses to a D-RAM (dynamic-random access memory) in general.
[0009]
SUMMARY OF THE INVENTION The present invention has been made in consideration of the above situation, and an ECC encoding method and apparatus for adding an ECC for correcting an error in digital data to recorded digital data, in which ECC generation and addition are performed at high speed. It is an object to provide a possible ECC encoding method and device.
[0010]
[Means for Solving the Problems]
In order to solve the above problem, an ECC encoding method according to the present invention calculates a first parity of one row in a horizontal direction with respect to data having a horizontal and vertical block structure by a first calculation circuit and adds the first parity in a horizontal direction, A first step of performing this for each row, and during the first step, the second parity of one column in the vertical direction for the data to which the first parity is added is calculated by a second calculation circuit. And a second step of calculating and performing this for each column.
[0011]
In another ECC encoding method according to the present invention, a first parity of one row in a horizontal direction is calculated by a first calculation circuit for data having a horizontal and a vertical block structure, and the first parity is added in a horizontal direction. A first step to be performed, respectively, and while the first step is performed, a syndrome in one column in the vertical direction is calculated by the second calculation circuit for the data to which the first parity is added, and this is calculated by each column. , And a third step of generating a second vertical parity from the calculated syndrome.
[0012]
That is, in each method, the process for generating and adding the first parity in the horizontal direction and the process for generating and adding the second parity in the vertical direction are performed in parallel. Therefore, there is no need for a temporally cascaded two-stage process of adding the first parity and temporarily storing the data in the memory, and accessing the stored data to generate and add the second parity. . Memory access required for cascaded processing in terms of time is a major cause of lowering processing speed. Therefore, according to the present invention, it is possible to generate and add ECC at high speed.
[0013]
In the latter method, a syndrome is calculated to calculate the second parity, and the second parity is generated from the syndrome obtained by the calculation. Syndrome calculation is indispensable in a reproducing circuit (ECC decoding circuit), and in an apparatus requiring recording and reproducing, the effect of reducing the scale is obtained by using the circuit in common, and the consistency is good.
[0014]
Further, the ECC encoding device according to the present invention calculates a first parity in one row in the horizontal direction for data having a horizontal and vertical block structure, adds the first parity in the horizontal direction, and performs the first parity generation circuit for each row. And while calculating the first parity for each row, calculate a second parity in one column in the vertical direction for the data to which the first parity is added, and perform the calculation for each column. And two parity generating circuits.
[0015]
Further, another ECC encoding apparatus according to the present invention calculates a first parity of one row in the horizontal direction for data having a horizontal and vertical block structure, adds the first parity in the horizontal direction, and performs a parity generation circuit for each of the rows. A syndrome generation circuit that calculates a vertical column of syndromes for the data to which the first parity is added while performing the calculation of the first parity for each of the rows, A circuit for generating a second parity in the vertical direction from the calculated syndrome.
[0016]
These devices are provided with a hardware configuration for executing each of the above methods.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
As an embodiment of the ECC encoding method according to the present invention, in the second step, a memory having a correspondence for each horizontal address of the data to which the first parity is added is used as a buffer, and the buffer and the second memory are used. It is convenient to carry out the results while going back and forth between the two calculation circuits. This is because the second calculation circuit performs parity calculation (or syndrome calculation) on data in the vertical direction. That is, since the data in the vertical direction can be obtained only in a discrete manner, a predetermined calculation is performed by using a memory managed by the addresses in the horizontal direction as a buffer and putting data in and out of the buffer.
[0018]
Further, as an embodiment, the method may further include a step of sequentially storing the data to which the first parity is added in a memory. It is temporarily stored in the memory.
[0019]
Here, as an embodiment, the method may further include a step of storing the second parity calculated in the second step in the memory so as to interleave the data stored in the memory. It may be. The temporary storage memory is used for the second parity interleave processing.
[0020]
Alternatively, as an embodiment, the method may further include a step of interleaving the calculated second parity while reading the data to which the first parity is added, stored in the memory, from the memory. . The second parity interleaving is performed in parallel with the sequential output of data from the temporarily stored memory. According to this, access to the memory does not increase, which is more convenient for speeding up.
[0021]
Further, as an embodiment, the first step is to generate a syndrome of one row in the horizontal direction with respect to the data of the horizontal and vertical block structure, and calculate the first parity in the horizontal direction from the generated syndrome. It may be added in the horizontal direction, and this may be performed for each row. This utilizes the calculation of the syndrome to generate the first parity.
[0022]
Further, as an embodiment of the ECC encoding apparatus according to the present invention, the ECC encoding apparatus further includes a memory having a correspondence for each horizontal address of the data to which the first parity is added, and the second parity generation circuit includes: It is convenient to use the memory as a buffer and calculate the second parity while reciprocating the intermediate result with the buffer.
[0023]
Further, as an embodiment, a memory for storing data to which the first parity is added may be further provided.
[0024]
Here, as an embodiment, a selector for interleaving the calculated second parity while reading the data stored in the memory from the memory may be further provided.
[0025]
Further, as an embodiment, the information processing apparatus further includes a memory having a correspondence for each horizontal address of the data to which the first parity is added, wherein the syndrome generation circuit uses the memory as a buffer and communicates with the buffer. It is convenient to calculate the syndrome while reciprocating the intermediate result.
[0026]
Further, as an embodiment, the parity generation circuit generates a syndrome of one row in the horizontal direction with respect to the data of the horizontal and vertical block structure, calculates the first parity in the horizontal direction from the generated syndrome, and calculates the horizontal parity. Alternatively, this may be performed for each row.
[0027]
The embodiment as the ECC encoding apparatus described above includes hardware for realizing the embodiment as the ECC encoding method.
[0028]
Based on the above, embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a recording system configuration when an ECC encoding device according to an embodiment of the present invention is applied to a recordable DVD device. As shown in FIG. 1, this recording type DVD device has a host system 201, an (ID + IED + RSV) addition circuit / scramble circuit / EDC addition circuit 202, a PI parity generation circuit 203, a PO parity generation circuit 204, and a PO parity. It has a buffer 205, a RAM control unit 206, a RAM 207, a modulation circuit 208, a recording compensation circuit 209, a pickup head (PUH) 210, a PO parity interleave selector 211, and a recording compatible disk 212.
[0029]
The host 201 supplies user data to be recorded to the (ID + IED + RSV) addition circuit / scramble circuit / EDC addition circuit 202 in a byte width (8 bits width). Here, ID is identification data, IED is ID error detection code, RSV is reserved, and EDC is error detection code.
[0030]
The (ID + IED + RSV) addition circuit / scramble circuit / EDC addition circuit 202 adds ID, IED, and RSV to the head of a certain group of the supplied user data, performs scramble processing on the group of user data, and Then, EDC is added to the tail. The data subjected to this series of processing becomes 2064 bytes (172 bytes × 12 rows: called a sector; see FIG. 4 described later) from the ID to the EDC, and is supplied to the PI parity generation circuit 203 sequentially along the rows. You.
[0031]
The PI parity generation circuit 203 generates and adds a 10-byte PI parity as a first parity of 10 bytes for every 172 bytes of supplied data according to a predetermined procedure. The data (182 bytes) to which the 10-byte PI parity is added is stored in the RAM 207 via the RAM control unit 206. When such storage in the RAM 207 is repeated 192 times (12 rows × 16 times), one unit (ECC block without PO parity) is obtained. Accordingly, the RAM 207 has a capacity of at least 34944 bytes (182 bytes (182 columns) × 192 rows) (see FIG. 6 described later).
[0032]
The data to which the 10-byte PI parity is added is also supplied to the PO parity generation circuit 204. The PO parity generation circuit 204 generates a PO parity as a second parity by a predetermined procedure in parallel with storing the output of the PI parity generation circuit 203 in the RAM 207. Since the PO parity is generated in parallel, when the storage of 34944 bytes of data in the RAM 207 is completed, the PO parity to be added to these data is also generated. The PO parity is generated in units of 16 bytes for 192 bytes in the vertical direction of 34944 bytes (182 × 192), and has a data size of 16 rows × 182 = 2912 bytes corresponding to the one unit.
[0033]
The PO parity buffer 205 is a memory that functions as a buffer necessary for the PO parity generation circuit 204 to generate the PO parity. Its capacity is exactly 16 rows × 182 = 2912 bytes as described above. That is, the PO parity generation circuit 204 uses the PO parity buffer 205 as a work area, and when the data of 34944 bytes of the output of the PI parity generation circuit 203 has been stored in the RAM 207 is completed, the data stored is the PO parity. The calculation is performed while taking data in and out. The generated PO parity is thereafter guided from the PO parity buffer 205 to the PO parity interleave selector 211.
[0034]
The RAM control unit 206 performs address control for writing and reading data to and from the RAM 207, writes predetermined data to a predetermined address, and reads predetermined data from a predetermined address. Writing is performed from the PI parity generation circuit 203 to the RAM 207 as a memory, and reading is performed from the RAM 207 to the PO parity interleave selector 211. The RAM 207 basically stores 34944 bytes (182 bytes × 192 rows) of data as described above.
[0035]
The PO parity interleave selector 211 is connected from the PO parity buffer 205 and from the RAM 207 via the RAM control unit 206, and adds one row of PO parity to every 182 bytes of horizontal 182 bytes stored in the RAM 207. Output (interleaved). Such interleaving of PO parity is defined as a standard. The data to which the PO parity is added is supplied to the modulation circuit 208.
[0036]
The modulation circuit 208 performs 8/16 conversion (conversion from 8 bits to 16 bits) defined as a DVD recording standard on the supplied data, and outputs the data as binary data (1 bit width). It is. The output data is supplied to the recording compensation circuit 209. The recording compensation circuit 209 performs a recording compensation process on the supplied binary data signal in order to compensate for a physical transmission characteristic generated by recording / reproducing on the recording-compatible disk 212. The recording-compensated binary data signal is supplied to the PUH 210.
[0037]
The PUH 210 drives a laser driver in accordance with the supplied binary data signal, and records the signal on the recording-compatible disk 212 using a laser beam. The recording compatible disk 212 is a removable medium on which binary data is written by the PUH 210.
[0038]
FIG. 2 is a functional block diagram functionally illustrating a processing procedure performed by the recording system configuration shown in FIG. FIG. 3 is a diagram showing a configuration of one ECC block. FIG. 4 is a sector (unit of information data shown in FIG. 3 in 16 sectors) constituting a portion (information data portion having a horizontal and vertical block structure) in the ECC block shown in FIG. 3 excluding PI and PO parities. FIG. 3 is a diagram showing an internal configuration of the device.
[0039]
FIG. 5 is a diagram showing a specific configuration example of the PI parity generation circuit 203 shown in FIG. FIG. 6 is a diagram showing a configuration of data stored in RAM 207 shown in FIG. FIG. 7 is a block diagram for explaining the configuration and operation of the PO parity generation circuit 204 shown in FIG. 1 in some detail. FIG. 8 is a flowchart showing an operation flow of the PO parity generation circuit and the like shown in FIG.
[0040]
Hereinafter, the operation of the ECC encoding device according to the present embodiment will be described with reference to FIGS.
[0041]
In FIG. 1, user data transferred from the host 201 is first input to the (ID + IED + RSV) addition circuit / scramble circuit / EDC addition circuit 202. The circuit 202 operates in units of 2048 bytes of user data, converts the user data into the sector data configuration of 2064 bytes shown in FIG. 4, and outputs the converted data. However, only the scramble processing is performed only on the main data shown in the figure corresponding to the user data. In the circuit 202, the processing steps 300 to 304 shown in FIG.
[0042]
On the other hand, the output data unit of the circuit 202 is 1/12 of the operation data unit instead of the 2064 byte unit, and is a 172 byte unit corresponding to one row of the sector shown in FIG. The 172 bytes of data are sequentially transferred to the PI parity generation circuit 203. The PI parity generation circuit 203 calculates 10 bytes of parity data in the PI direction from the 172 bytes of data and adds it to the end to generate a codeword of 182 bytes.
[0043]
Here, a method of generating the PI parity will be described. A primitive polynomial in Galois field in the DVD standard is defined by the following equation.
P (x) = x⁸+ X⁴+ X³+ X²+1
Further, the generating polynomial of the PI parity is as follows.

This is α⁰~ Α⁹This is an equation for generating a code sequence in which ten consecutive components up to are the root. To add a PI parity, an information polynomial of 172 bytes may be divided by the generator polynomial, and the remainder may be added to the information polynomial.
[0044]
In order to perform such additional processing in a circuit, a PI parity generation circuit (first calculation circuit) having a configuration as shown in FIG. 5 can be used. This PI parity generation circuit represents a division circuit using a shift register, and D in the figure represents shift registers 54,.ⁿIndicate Galois field multiplication circuits 51,... 53 (Galois multipliers). Reference numerals 58, 59, 60, etc., are operation circuits (exclusive OR gates) for obtaining exclusive OR. The calculation and registration operation of each unit by the configuration shown in FIG. 5 are performed using 8 bits (1 byte) as one data unit.
[0045]
As an operation, first, SWa is closed, SWb is tilted to 1 side, and information data H is input from an input terminal._x(X = 0 to 171) are sequentially input to the shift registers 54,. At the same time, the input data is output directly from the output terminal (the common terminal side of SWb). When input and output of all 172 bytes of data are completed, SWa is released and SWb is tilted to the second side, and 10 bytes of parity data generated in the shift registers 54,. . As a result, the parity-added data I_x(0-181) are generated.
[0046]
The output data of 182 bytes passes through the RAM control unit 206 and is sequentially stored in the RAM 207. By repeating this operation 192 times, an ECC block without PO parity (182 bytes × 192 rows) as shown in FIG. Is generated. It is usually advisable to use a large-capacity and inexpensive D-RAM as the RAM 207 as a memory.
[0047]
On the other hand, the output data of 182 bytes × 192 rows is also transferred to the PO parity generation circuit 204 in parallel with the storage in the RAM 207, and the PO parity generation circuit 204 performs the parity calculation in the 182 columns of the PO sequence in real time. It is done in. Here, a method of generating the PO parity will be described.
[0048]
The PO parity generator polynomial can be represented by the following equation, similarly to PI.

[0049]
This is α⁰~ Α^Fifteen16 is an equation for generating a root code sequence. Although the principle of the PO parity calculation itself is almost the same as that of the PI parity, the configuration of the PO parity generation circuit 204 cannot be the same as that of the PI parity generation circuit 203. This is because a PI sequence is a sequence in the row direction of an ECC block, that is, a data stream direction, and 172 bytes of information data required for generating a 10-byte PI parity are continuously transferred, whereas a PO sequence is an ECC block. This is because necessary information data is not transferred continuously since the sequence is in the column direction of the block.
[0050]
That is, the PI parity generation circuit 203 only needs to calculate the PI parity from 172 consecutive bytes, whereas the 192 bytes of information data necessary to generate 16 bytes of PO parity are only 1 byte for every 182 bytes of received data. I can't get it. Further, the other 181 bytes are information data of different PO columns. Therefore, the PO parity generation circuit 204 determines that the input data J_xUsing (182 bytes × 192 rows), the configuration is such that the PO parity calculation for 182 columns is performed while being switched as needed for each input byte.
[0051]
Here, the configuration and operation of the PO parity generation circuit 204 will be described with reference to FIGS. FIG. 7 is a block diagram for explaining the configuration and operation of the PO parity generation circuit 204 shown in FIG. 1 in some detail. FIG. 8 is a flowchart showing an operation flow of the PO parity generation circuit and the like shown in FIG. 7, the same components as those shown in FIG. 1 are denoted by the same reference numerals.
[0052]
Input data J_x(182 bytes × 192 rows) are transferred to the PO parity generation controller 701 and the PO parity calculation circuit 702 (second calculation circuit) in byte units. The PO parity generation controller 701 has a 182 byte counter, and controls the PO parity calculation circuit 702 and the input / output of the PO parity buffer 205 by recognizing which PO column the input information data is. Here, input / output of the PO parity buffer 205 is controlled via the interface 703.
[0053]
The PO parity calculation circuit 702 has D₀~ D_Fifteen7 and a Galois multiplier, and performs the division calculation as shown in the table below the PO parity calculation circuit 702 in FIG. 7 (step 801 in FIG. 8). This division calculation is based on the same configuration principle as that of the PI parity circuit shown in FIG. In the table in FIG._na is the calculated D_n(N = 0 to 15).
[0054]
Since the PO column to be calculated is switched every byte, the internal data of the 16 registers also need to be saved in the PO parity buffer 205 byte by byte (step 804). When the information data of the same PO column is transferred 182 bytes later, the intermediate result is read from the buffer 205 (step 802), and the internal register D₀~ D_FifteenThen, the PO parity calculation is performed again (step 803). By repeating this operation 192 times (Y in step 805), the PO parity calculation for one column of the PO sequence is completed.
[0055]
Further, the same calculation is continuously performed for the remaining 181 PO columns._xWhen all (182 bytes x 192 rows) are input, the PO parity calculation for all PO columns is completed, and the parity data is stored in the PO parity buffer 205. At the same time J_xHas been completed in the RAM 207. That is, at this point, the information data and the PI parity portion of the ECC block shown in FIG. 3 are stored in the RAM 207, and the PO parity portion is stored in the PO parity buffer 205.
[0056]
The ECC block shown in FIG. 3 conforms to the DVD standard. The error correction code in the PO direction has a code length of 208 bytes, the information length is 192 bytes, and the minimum distance is 17. Byte, information length 172 bytes, minimum distance 11
[0057]
Subsequently, the ECC block data on which the ECC encoding process has been completed is subjected to an interleaving process by the PO parity interleaving selector 211 and transferred to the modulation circuit 208. The interleaving process is a process of adding 182 bytes of PI direction data of the PO parity section to every 2184 bytes (182 bytes × 12 rows) of sector data with PI parity, and is performed for 16 sectors. In this embodiment, 2184 bytes of sector data with PI parity output from the RAM control unit 206 and 182 bytes output from the buffer 205 for PO parity are switched by the interleave selector 211 every 16 sectors.
[0058]
With the above processing, the processing up to the processing procedure 306 in FIG. 2 ends. That is, 16 recording frames are generated corresponding to the 16 sectors.
[0059]
As another form of the interleave processing, the completed PO parity data may be stored in the PO parity buffer 205 once in the RAM 207 via the RAM control unit 206 so as to be subjected to the interleave processing. In this case, the capacity of the RAM 207 is set to be large enough to store the PO parity data. Thereby, the data stored in the RAM 207 can be output to the modulation circuit 208 without passing through the PO parity interleave selector 211. However, the number of accesses to the RAM 207 is increased as compared with the case where the selector 211 is used.
[0060]
After the interleaving, as processing up to the processing procedure 307 in FIG. 2, the modulation circuit 208 adds a synchronization code (one ECC block to 26 synchronization frames) to the transferred data, and complies with the modulation rule of DVD. A certain 8/16 modulation process is performed, and transferred to the recording compensation circuit 209. The recording compensation circuit 209 performs recording compensation on the binary modulated data signal from the modulation circuit 208. In the PUH 210, a laser driver is driven based on the binary modulated data signal whose recording has been compensated, and a recording mark is formed on the recording-compatible disk 212.
[0061]
As described above, in the ECC encoding device according to the present embodiment, the PI parity generation calculation and the PO parity generation calculation are performed in parallel with the data storage processing of the ECC data in the RAM 207, so that the parity calculation RAM 207 The information data read / write processing is completely omitted. As a result, an ECC encoding process capable of easily achieving a high speed can be realized.
[0062]
Next, an ECC encoding device according to another embodiment of the present invention will be described with reference to FIG. FIG. 9 is a block diagram showing a recording system configuration when an ECC encoding device according to another embodiment of the present invention is applied to a recordable DVD device. In FIG. 9, the same components as those already described are denoted by the same reference numerals. In the following, description will be made while avoiding duplication of such portions.
[0063]
In this embodiment, at least a “PO syndrome generation circuit” and an “ECC decode circuit” are used to generate a PO parity in parallel with the generation of a PI parity. These circuits themselves have the same functions as those generally used in the reproduction circuit of the DVD device in terms of input / output signals. Furthermore, by combining the “PO syndrome generation circuit” with the “PO syndrome buffer”, the “PO syndrome generation circuit” can be operated in parallel with the data storage in the RAM 207, and the access to the RAM 207 for parity calculation can be omitted. It is like that.
[0064]
As shown in FIG. 9, this recordable DVD device has a PO syndrome generation circuit 904, a PO syndrome buffer 905, and an ECC decode circuit 906, in addition to the components already described, and these are implemented by the embodiment shown in FIG. It is provided instead of the PO parity generation circuit 204 and the PO parity buffer 205 of the embodiment.
[0065]
The PO syndrome generation circuit 904 generates a PO syndrome by a predetermined procedure in parallel with storing the output of the PI parity generation circuit 203 in the RAM 207. Since the PO syndrome is generated in parallel, the PO syndrome is generated when storage of 34944 bytes (182 bytes × 192 lines) of data in the RAM 207 is completed. The PO syndrome is generated in units of 16 bytes for 34944 bytes in a vertical direction of 192 bytes (208 bytes including an appropriate 16 bytes virtually added), and one ECC block has 16 rows × 182 = 2912 bytes of data. Size.
[0066]
The PO syndrome buffer 905 is a memory that functions as a buffer necessary for the PO syndrome generation circuit 904 to generate the PO syndrome as described above, in parallel with storing data in the RAM 207. Its size is exactly 16 rows × 182 = 2912 bytes as described above. That is, the PO syndrome generation circuit 204 uses the PO syndrome buffer 905 as a work area, and stores the 34944-byte data in the RAM 207 of the output of the PI parity generation circuit 203 as the PO syndrome. The calculation is performed while taking data in and out.
[0067]
The ECC decode circuit 906 performs erasure correction based on the PO syndrome stored in the PO syndrome buffer 905. By this erasure correction, a PO parity (16 rows × 182 = 2912 bytes) is generated in an area of data appropriately added at the time of generating the PO syndrome. The generated PO parity is overwritten and stored in the PO syndrome buffer 905. The overwritten and stored PO parity is thereafter guided from the PO syndrome buffer 905 to the PO parity interleave selector 211.
[0068]
FIG. 10 is a block diagram for explaining the configuration and operation of the PO syndrome generation circuit 904 shown in FIG. 9 in some detail. FIG. 11 is a diagram showing a specific configuration example of the PO syndrome calculation circuit 1002 shown in FIG. FIG. 12 is a flowchart showing an operation flow of the PO syndrome generation circuit and the like shown in FIG.
[0069]
Hereinafter, the operation of the ECC encoding apparatus according to the present embodiment will be described with reference to FIGS.
[0070]
In FIG. 9, the output data of 182 bytes × 192 rows of the PI parity generation circuit 203 is also transferred to the PO syndrome generation circuit 904 in parallel with the storage in the RAM 207. The syndrome calculation in the column is switched in units of one byte and is performed in real time. Syndrome S in one PO series data string₀~ S_FifteenCan be calculated by the following equation. Where I_xHere, (x = 0 to 207) represents 208 bytes of the PO series code data string.
S₀= I₀+ I₁+ ... + I₂₀₆+ I₂₀₇
S₂= I₀α²⁰⁷+ I₁α²⁰⁶+ ... + I₂₀₆α + I₂₀₇
・
・
・
S_Fifteen= I₀α^15x207+ I₁α^15x206+ ... + I₂₀₆α^Fifteen+ I₂₀₇
[0071]
Also, as can be seen from these formulas, a code data string of 208 bytes is required to calculate the syndrome, and the input 192 bytes are not enough for 16 bytes. Since the insufficient 16-byte data becomes PO parity as a result when it is corrected by the subsequent ECC decoding process, any data may be used at first. Here, the efficiency of the calculation process is achieved by filling this with 0 data.
[0072]
A PO syndrome calculation circuit 1002 (second calculation circuit: see FIG. 10) for processing the insufficient 16 bytes as 0 data will be described with reference to FIG. In FIG. 11, a portion surrounded by a broken line is a well-known portion usually used in a reproducing circuit for generating a syndrome.
[0073]
That is, the flip-flop (register D_x  , X = 0 to 15) The outputs of the respective 112 to 118 are guided to Galois multipliers 115 to 119 (however, the Galois multiplier is equivalent to “1” for the flip-flop 112), and the outputs of the Galois multipliers 115 to 119 are output. One of the inputs of exclusive OR gates 111 to 117. The other input side of the exclusive OR gates 111 to 117 has input data I_xAre commonly input, and the outputs of the exclusive OR gates 111 to 117 are connected to a flip-flop (register D)._x) 112 to 118 are input. The operation and operation of each unit according to the configuration shown in FIG. 11 are performed in units of 8 bits (1 byte).
[0074]
In FIG. 11, a flip-flop (register D_x) 112-118, Galois multipliers 115-119, and exclusive OR gates 111-117. When 192 bytes of input data are sequentially input to each circuit, a flip-flop (register D_x) 112 to 118 show the intermediate result of the syndrome calculation using the 192 bytes in the following equation S:₀a to S_Fifteena.
S₀a = I₀+ I₁+ ... + I₁₉₀+ I₁₉₁
S₂a = I₀α¹⁹¹+ I₁α¹⁹⁰+ ... + I₁₉₀α + I₁₉₁
・
・
・
S_Fifteena = I₀α^15x191+ I₁α^{15 × 190}+ ... + I₁₉₀α^Fifteen+ I₁₉₁
[0075]
This formula is compared with the above-mentioned syndrome calculation formula, and₁₉₂~ I₂₀₇Is 0, in order for the syndrome calculation to be established, α^{16 × m}(M = 0 to 15: syndrome number). Therefore, in the circuit (PO syndrome calculation circuit 1002) shown in FIG. 11, the Galois multipliers 116,..., 120 are placed so that the syndrome calculation is completed by closing SW0 to SW15 after 192 clocks have elapsed. ing.
[0076]
Although the PO syndrome calculation circuit 1002 performs such an operation, the PO syndrome generation circuit 904 as a whole has to switch the PO182 column syndrome calculation for each byte as in the above-described embodiment. Must. Therefore, register D₀~ D_FifteenIs carried out while saving the contents of the data in the PO syndrome buffer 905.
[0077]
FIG. 10 is a block diagram for explaining the configuration and operation of the PO syndrome generation circuit 904 shown in FIG. 9 in some detail. FIG. 10 shows a PO syndrome buffer 905 and an ECC decode circuit 906 in addition to a portion corresponding to the PO syndrome generation circuit 904.
[0078]
Input data J_x(182 bytes × 192 lines) is transferred to the PO syndrome generation controller 1001 and the PO syndrome calculation circuit 1002 in 1-byte units (step 1201 in FIG. 12). The PO syndrome generation controller 1001 has a 182 byte counter, and recognizes which PO column the input information data is, and controls the input / output of the PO syndrome calculation circuit 1002 and the PO syndrome buffer 905. Here, input / output control of the PO syndrome buffer 905 is performed via the interface 1003.
[0079]
Also, since the PO column to be calculated is switched every byte, 16 registers D_xIt is also necessary to save the internal data (x = 0 to 15) in the PO syndrome buffer 905 byte by byte (step 1204). Then, when the information data of the same PO column is transferred after 182 bytes, the intermediate result is read from the buffer 905 (step 1202), and the internal register D_xThe data is transferred to (x = 0 to 15), and the PO syndrome calculation is performed again (step 1203). This operation is repeated 192 times, and finally, by closing SW0 to SW15 in FIG. 11 described above, the PO syndrome calculation of one column of the PO sequence is completed (Y in step 1205).
[0080]
Further, the same calculation is continuously performed for the remaining 181 PO columns._xWhen all (182 bytes x 192 rows) have been input, the PO syndrome calculation for all PO columns is completed, and the syndrome data is stored in the PO syndrome buffer 905. At the same time J_xHas been completed in the RAM 207.
[0081]
Subsequently, the created PO syndrome is read from the buffer 905 and transferred to the ECC decode circuit 906 (step 1206), and error correction is performed by the ECC decode circuit 906 (step 1207). In other words, in the above processing (processing in the PO syndrome calculation circuit 1002), 16 bytes embedded as 0 data are converted into 16 bytes of PO parity to be generated. The ECC decode circuit 906 has a syndrome correction circuit, a Euclidean calculation circuit, a chain search circuit, and the like, as is well known.
[0082]
In the above error correction processing, the correction capability of the PO series is usually up to 8 bytes, and an error exceeding 8 bytes cannot be corrected. However, if error position information (erasure pointer) is used, up to 16 bytes can be used. Error correction processing is possible. This is generally called erasure correction (erasure correction). In this embodiment, since the position of the PO parity to be generated is determined to be the last 16 bytes of the code string, if the erasure pointer is generated from the error position, the correction processing, that is, the PO parity can be generated. is there.
[0083]
More specifically, the desired syndrome data is selected by the ECC decode controller 1004 from the PO syndrome buffer 905 and sent to the ECC decode circuit 906. Then, the ECC decode circuit 906 performs a syndrome correction process using the erasure pointer, and then calculates an error pattern (that is, PO parity) at the error position by a chain search process.
[0084]
Next, the ECC decode controller 1004 overwrites the calculated PO parity in the called syndrome area on the PO syndrome buffer 905 based on the error position (step 1208). By executing this process for all PO sequences, the parity data of all PO sequences is completed in the PO syndrome buffer 905. The PO parity data completed in the PO syndrome buffer 905 is used for subsequent processing in the same manner as the PO parity data completed in the PO parity buffer 205 in the previous embodiment.
[0085]
Note that, in the description here, the case where the generated PO parity is written in the syndrome buffer 905 has been described, but the RAM 207 may be written via the RAM control unit 206. In this case, the capacity of the RAM 207 is set to be large enough to store the PO parity data. At the time of writing to the RAM, the data may be stored so that the PO parity is interleaved.
[0086]
As described above, in the ECC encoding apparatus according to this embodiment, the PI parity generation calculation and the PO syndrome calculation are performed in parallel with the data storage processing in the ECC data RAM 207, and the ECC decoding processing for generating the PO parity is performed. Also, access to the RAM 207 is omitted. As a result, an ECC encoding process capable of easily achieving a high speed can be realized.
[0087]
Further, the PO syndrome circuit 904, the ECC decode circuit 906, and the PO syndrome buffer 905 can also be used as a reproduction system circuit. Therefore, it is also effective in reducing the circuit scale of the entire recording / reproducing system.
[0088]
In the above embodiment, the PO parity is generated by the ECC decoding circuit using the syndrome generation circuit. However, the PI parity can also be generated by using the syndrome generation circuit and the ECC decoding circuit. In this case, a PI syndrome buffer is separately provided, and a processing procedure of the syndrome calculation of the PI parity section and the PI parity calculation by the ECC decoding circuit is added. For this reason, although the processing speed is inferior to those of the above embodiments, the circuit scale can be reduced by further using the reproducing system circuit.
[0089]
【The invention's effect】
As described above in detail, according to the present invention, the process for generating and adding the first parity in the horizontal direction and the process for generating and adding the second parity in the vertical direction are performed in parallel. Therefore, there is no need to perform a two-step process of adding the first parity and temporarily storing the data in the memory, and accessing the stored data to generate and add the second parity.・ Addition can be performed at high speed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a recording system configuration when an ECC encoding device according to an embodiment of the present invention is applied to a recordable DVD device.
FIG. 2 is a functional block diagram functionally explaining a processing procedure performed by the recording system configuration shown in FIG. 1;
FIG. 3 is a diagram showing a configuration of one ECC block.
FIG. 4 is a diagram showing an internal configuration of a sector (information data shown in FIG. 3 in 16 sectors), which is a unit constituting a portion (information data portion) in the ECC block shown in FIG. .
FIG. 5 is a diagram showing a specific configuration example of a PI parity generation circuit 203 shown in FIG. 1;
FIG. 6 is a diagram showing a configuration of data stored in a RAM 207 shown in FIG.
FIG. 7 is a block diagram for explaining the configuration and operation of the PO parity generation circuit 204 shown in FIG. 1 in some detail;
FIG. 8 is a flowchart showing an operation flow of the PO parity generation circuit and the like shown in FIG. 7;
FIG. 9 is a block diagram showing a recording system configuration when an ECC encoding device according to another embodiment of the present invention is applied to a recordable DVD device.
FIG. 10 is a block diagram for explaining the configuration and operation of the PO syndrome generation circuit 904 shown in FIG. 9 in some detail;
11 is a diagram showing a specific configuration example of a PO syndrome calculation circuit 1002 shown in FIG.
FIG. 12 is a flowchart showing an operation flow of the PO syndrome generation circuit and the like shown in FIG. 10;
[Explanation of symbols]
51, 52, 53 ... Galois multipliers 54, 55, 56, 57 ... shift registers 58, 59, 60 ... exclusive OR gates 111, 113, 117 ... exclusive OR gates 112, 114, 118 ... registers 115, 119 Galois multipliers 116, 120 Galois multiplier 201 Host 202 (IE + IED + RSV) addition circuit / scramble circuit / EDC addition circuit 203 PI parity generation circuit 204 PO parity generation circuit 205 PO buffer 206 206 RAM Control unit 207 RAM 208 Modulation circuit 209 Recording compensation circuit 210 Pickup head 211 PO parity interleave selector 212 Recording disk 701 PO parity generation controller 702 PO parity calculation circuit 703 Interface 904 ... PO syndrome generating circuit 905 ... PO syndrome buffer 906 ... ECC decoding circuit 1001 ... PO syndrome generating controller 1002 ... PO syndrome calculation circuit 1003 ... interface 1004 ... ECC decode controller

Claims (15)

A first step of calculating the first parity of one row in the horizontal direction with respect to the data of the horizontal and vertical block structure by the first calculation circuit and adding the parity in the horizontal direction, and performing the same for each row;
While the first step is performed, the second parity of one column in the vertical direction is calculated by the second calculation circuit for the data to which the first parity is added, and the second calculation is performed for each column. An ECC encoding method, comprising the steps of: The second step uses a memory having a correspondence for each horizontal address of the data to which the first parity is added as a buffer, and reciprocates an intermediate result between the buffer and the second calculation circuit. 2. The ECC encoding method according to claim 1, wherein the ECC encoding is performed. 2. The ECC encoding method according to claim 1, further comprising the step of sequentially storing the data to which the first parity is added in a memory. 4. The method according to claim 3, further comprising the step of storing the second parity calculated in the second step in the memory so as to interleave the data stored in the memory. ECC encoding method. 4. The ECC of claim 3, further comprising interleaving the calculated second parity while reading the data with the first parity stored in the memory from the memory. Encoding method. A first step of calculating the first parity of one row in the horizontal direction with respect to the data of the horizontal and vertical block structure by the first calculation circuit and adding the parity in the horizontal direction, and performing the same for each row;
While the first step is performed, the second calculation circuit calculates a syndrome in one column in the vertical direction for the data to which the first parity is added, and performs the calculation for each column. ,
And a third step of generating a second vertical parity from the calculated syndrome. The second step uses a memory having a correspondence for each horizontal address of the data to which the first parity is added as a buffer, and reciprocates an intermediate result between the buffer and the second calculation circuit. 7. The ECC encoding method according to claim 6, wherein the encoding is performed. The first step generates a horizontal one-row syndrome for the data having the horizontal and vertical block structure, calculates the first parity in the horizontal direction from the generated syndrome, and adds the first parity in the horizontal direction; 7. The ECC encoding method according to claim 1, wherein the ECC encoding is performed for each row. A first parity generation circuit that calculates a first parity of one row in the horizontal direction for data having a horizontal and vertical block structure, adds the first parity in the horizontal direction, and performs the same for each row;
While the calculation of the first parity is performed for each row, a second parity of one column in the vertical direction is calculated for the data to which the first parity is added, and the second parity is calculated for each column. An ECC encoding device comprising a parity generation circuit. A memory having a correspondence for each horizontal address of the data to which the first parity is added;
10. The ECC encoding device according to claim 9, wherein the second parity generation circuit uses the memory as a buffer to calculate the second parity while reciprocating an intermediate result with the buffer. The ECC encoding apparatus according to claim 9, further comprising a memory for storing the data to which the first parity is added. 12. The ECC encoding apparatus according to claim 11, further comprising a selector for interleaving the calculated second parity while reading the data stored in the memory from the memory. A parity generation circuit that calculates the first parity of one row in the horizontal direction and adds it in the horizontal direction for the data having the horizontal and vertical block structure, and performs the calculation for each row;
While performing the calculation of the first parity for each of the rows, a syndrome generation circuit that calculates a vertical one column syndrome for the data to which the first parity is added, and performs the calculation for each column,
A circuit for generating a second vertical parity from the calculated syndrome. A memory having a correspondence for each horizontal address of the data to which the first parity is added;
14. The ECC encoding device according to claim 13, wherein the syndrome generation circuit calculates the syndrome while reciprocating an intermediate result with the buffer using the memory as a buffer. The parity generation circuit generates a syndrome in one row in the horizontal direction for the data in the horizontal and vertical block structure, calculates the first parity in the horizontal direction from the generated syndrome, and adds the first parity in the horizontal direction. 14. The ECC encoding device according to claim 9, wherein the ECC encoding is performed for each row.

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