JP2008099311A - Access burst detector correlator pool - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a Node-B capable of handling varying conditions in a flexible manner while efficiently utilizing hardware. <P>SOLUTION: A Node-B has an access burst detector. The access burst detector comprises at least one antenna (28<SB>1</SB>-28<SB>m</SB>) for receiving signals from users and a pool of reconfigurable correlators (36<SB>1</SB>-36<SB>o</SB>). Each correlator correlates an input access burst code at an input code phase with an input antenna output. An antenna controller (30) selectively couples an arbitrary output of the at least one antenna to an input of an arbitrary correlator. A code controller (40) provides an input of each correlator with an access burst code. The code controller (40) controls the input code phase of each controller. A sorter (38) sorts output energy levels of the correlators. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention generally relates to wireless code division multiple access communication systems. Specifically, the present invention relates to detection of access bursts in such systems.

  In wireless communication systems, access bursts are commonly used to access system resources. An example of such a burst is the physical random number proposed for the 3rd generation mobile communication system standardization project (3GPP / third generation partner project) wideband code division multiple access (W-CDMA / wideband code multiple access) communication system. It is a preamble used for access to an access channel (PRACH / physical random access channel) and a physical common packet channel (PCPCH / physical common packet channel).

  To access these channels, the user transmits a preamble or signature (preamble) to the base station. The base station broadcasts usable codes and time slots that can transmit the preamble. The user increases the power level of the transmitted preamble until it is detected by the base station or until the maximum transmission power level is reached. When the base station detects the preamble of a specific user, an acknowledgment (ACK) or negative acknowledgment (NAK) indicating the availability of the channel is transmitted to the user.

FIGS. 1A and 1B show two possible user densities and cell sizes where access burst detection is used. FIG. 1A is a diagram showing a small cell 24A having a high user density, such as an urban area. The base station 20 provides services to user equipment (UE) 22 ₁ to 22 ₁₇ . In order to deal with a large number of users, a number of preamble codes are used to distinguish the users. FIG. 1B shows a large cell 24B with few users. Base station 20 provides services to UEs 22 ₁ to 22 ₃ . Since there are few users, users can be distinguished by several preamble codes. However, the preamble transmission from the user (UE 22 ₃ ) close to the base station is received with significantly less delay than the transmission from the user (UE 22 ₂ ) in the periphery of the cell 24B. Each user synchronizes their transmission with the reception timing of the base station transmission. As a result, the round trip delay in receiving user transmissions in the cell periphery is significantly greater than nearby users. The base station 20 of the cell 24B needs to deal with these delay spreads. Based on cell size and user density, the access burst detector of base station 20 needs to be changed.

In addition, other cell parameters may be different. As shown in FIG. 2A, cell 24 is divided into six sectors 26 ₁ through 26 ₆ . Furthermore the base station 20, by using two antenna elements _{28 11} to _{28 62} per from the sector 26 ₁ to 26 ₆ also uses diversity transmission and reception in each sector from 26 ₁ 26 _6. The preamble transmitted in the cell 24 is first detected by any one of the antenna elements 28 ₁₁ to 28 ₆₂ of any of the sectors 26 ₁ to 26 ₆ . As a result of this configuration, it is desirable for the base station 20 to be able to detect any preamble code of the cell by any of the antenna elements 28 ₁₁ to 28 ₆₂ . In contrast, in FIG. 2B, the cells are not divided into sectors and the base station 20 uses a single omni-directional antenna 28.

  One approach to addressing these fluctuating conditions is to build the hardware to cover the maximum possible round trip delay for every possible access code on every supported antenna. However, it is unlikely that this will be designed for the worst possible combination of these parameters. Larger cells typically use fewer access codes, and smaller cells used to cover a “hot spot area” typically require more codes. Sectorization tends to reduce the number of access codes used. In general, using the worst-case scenario hardware design results in the hardware design being used only to support implementations that do not use a large amount of hardware in some implementations or that are closer to the worse case. Will be.

  Therefore, it would be desirable to have a Node B / base station that can handle these varying conditions in a flexible manner while using hardware efficiently.

  The Node B / base station has an access burst detector. The access burst detector comprises at least one antenna for receiving a signal from a user and a pool of reconfigurable correlators. Each correlator correlates the input access burst code with the input antenna output at the input code phase. The antenna controller selectively couples any output of at least one antenna to the input of any correlator. The code controller provides an access burst code at the input of each correlator. The code controller controls the input code phase of each controller. A classifier / post processor classifies the output energy level of the correlator.

FIG. 3 is a simplified diagram illustrating a preferred base station / Node B access burst detector. Each antenna 28 ₁ to 28 _M of the base station / Node B is coupled to an antenna controller 30. The number M of antennas varies. For a base station / Node B that uses one omni-directional antenna, the number of antennas is one. For sectorized cells that use an antenna array in each sector, the number of antennas may be large. For example, referring to FIG. 2A, a 6-sector cell with 2 antennas per sector would have (12) antennas. Antenna controller 30 effectively controls the coupling of 36 _O and the antenna output from the correlator 36 _1.

For each address code the base station / Node B is used, the controller controls the access code input to 36 _O from the correlators 36 _1. Code phase controller / delay device 34 controls the phase / delay code 36 _O from the correlators 36 ₁ to operate. Each correlator 36 ₁ through 36 _O , such as a matched filter, is configured to correlate a given input code with a given input antenna output at a given code phase / delay. As a result, it is preferably 36 _O from the correlators 36 _1, reconfigurable to correlate any encode any antenna output at any code phase / delay.

₁ from 36 _O correlator 36 effectively forms a reconfigurable correlator pool. The reconfigurability of the correlator pool allows the use of various designs for fluctuating environments. The uniform reconfigurability of each correlator facilitates the implementation of the correlator using a small scalable design that is quite advantageous for use on an application specific integrated circuit (ASIC). For ASICs with clock rates above the chip rate, each reconfigurable correlator can be used to process multiple antenna / code / code phase combinations. For example, for a 48x chip rate clock, each correlator can process 48 antenna / code / code phase combinations.

The output of each correlator 36 ₁ through 36 _O is processed by a classifier / post processor 38. The classifier / post-processor 38 classifies the various code / code phase combinations in order of correlator output energy. Access codes that exceed a predetermined correlation energy threshold are considered to be detected. In response to detecting the access code, a corresponding ACK or NAK is sent to indicate whether the requested resource is available.

FIG. 4 is a diagram showing another configuration of the access burst detector. Similar to the arrangement of FIG. 3, the antenna controller 30 effectively controls the coupling between the output 36 _O from each antenna element output to each correlator 36 _1. The N code generator 40 generates an N code. The series of delay devices 41 ₁ to 41 _O-1 generates a delayed version of the series of codes. A preferred value for each delay is one chip or half chip. As a result, code that is input to the 36 _O from the correlators 36 ₁ is a delayed version of the same code. For example, if each delay is a one-chip delay, the correlator receives a delay code version window through an O-chip window. As a result, the correlator bank can correlate a given code via O-chip delay spread. The output of each correlator 36 ₁ through 36 _O is processed by a classifier / post processor 38.

  In one implementation for preamble detection, the access burst detector of FIG. 4 has 48 code generators (N = 48) and 64 correlators (O = 64) and operates at a chip rate of 48x. The detector can process 48 code / antenna combinations, such as 4 codes via 12 antennas, over a 64 chip cell radius. The cell radius can be doubled to 128 chips by halving the code / antenna combination to 24. Since the delay bank only spans 64 chips, half of the code generator generates code with a delay of 64 chips to serve the entire cell radius.

Due to the flexible correlator bank, the access burst detector is flexible and scalable for various base station / Node B implementations as shown in FIGS. 5A, 5B, and 5C. For an access burst detector ASIC that can handle 3072 code / antenna / delay combinations, one ASIC 44 can process the cell layout of FIG. 5A. In FIG. 5A, there are three sectors in the cell, and two antenna elements 28 ₁₁ to 28 ₃₂ are assigned to each sector. The cell radius is 64 chips. Eight access codes can be used in each sector. The base station 20 processes the cell using one ASIC 44 (8 code × 12 antenna elements × 64 chips = 3072 code / antenna / delay combination).

In FIG. 5B, the radius of the cell is 128 chips. There is no sector in the cell, which is handled by _two antenna elements 28 ₁ and 28 ₂ . A cell can use 12 access codes. The base station 20 uses one ASIC 44 to process the cell (12 code × 2 antenna elements × 128 chips = 3072 code / antenna / delay combination).

In FIG. 5C, the cell is the same size as in FIG. 5A, with a 64 chip radius. However, the cell density is higher and is divided into six sectors. Each sector is served by two antenna elements 28 ₁₁ to 28 ₆₂ . Eight access codes can be used in each sector. The base station 20 processes the cell using _two ASICs 44 ₁ and 442 (8 code × 12 antenna elements × 64 chips = 3072 code / antenna / delay combination). Thus, a modification of software 42 allows the same ASIC 44 to be used for both cells of FIGS. 5A and 5B. To handle the requirements of more advanced FIG 5C, 2 single ASIC 44 ₁ and 44 ₂ are used. Division of the combination of the code / antenna / delay each ASIC 44 ₁ and 44 ₂ is responsible is controlled preferably by software 42.

  FIG. 6 is a diagram illustrating a preferred correlator bank 68 for a 3GPP access burst detector. Correlator bank 66 is coupled to one of antennas 28 by multiplexer (MUX) 46. MUX 66 selects one of the antenna outputs to be used by correlator bank 66. In 3GPP systems, access bursts are transmitted using quadrature phase shift (QPSK) modulation. In-phase sampling device 48 and 4-phase sampling device 50 produce in-phase (I) and 4-phase (Q) samples of the selected antenna output. The sample is processed to generate a composite result by a complex result device 54.

Preferably, 48 access codes are generated by 48 scramble code generators 58. Each access code has 16 signatures according to the 3GPP standard. In the preferred implementation, a 48 × chip rate clock is used. For a given chip period, correlators 56 ₁ to 56 ₂₂ (56) correlate each of the 48 access codes in turn during each clock period.

Each correlator 56 has MUXs 60 ₁ to 60 ₂₂ (60) for effectively mixing one of the access codes and the antenna output. Buffers 62 ₁ to 62 ₂₂ (62) store the mixed result. In order to process the 16 signatures in the access code, the 16 Hadamard signature detectors 64 _1,1 to 64 _22,16 are used to detect the 16 signatures. The preferred number of correlators 56 is 22. Between each correlator 56 is a buffer 66 ₁ through 66 ₂₂ that delays the code by one chip before entering the subsequent correlator 56. As a result, the correlator bank 68 correlates one access code to 16 signatures via a 22 chip delay spread within one clock period.

  Using the implementation of FIG. 6, one correlator bank 68 can process 48 access codes through a chip delay of 22 chips within one chip period. To expand the Node B region, half of the generated code can be a 22-chip delayed version of the other code. As a result, the correlator bank 68 can process 24 access codes through a delay of 44 chips within one chip period. As an alternative, correlator bank 68 can handle multiple antennas within a period by reducing the number of correlated access codes.

  In an alternative implementation, the chip area of bank 56 can be expanded by adding correlator 56 to the correlator bank. The number of codes to be processed can also be changed by changing the generated access code and clock rate.

It is a figure which shows a small cell with a high user density. It is a figure which shows the large sized cell with a low user density. FIG. 2 shows a sectorized cell with a base station using two antenna elements per sector. FIG. 2 shows a non-sectorized cell with a base station with one omni-directional antenna. FIG. 6 is a simplified diagram illustrating one embodiment of an access burst detector. FIG. 6 is a simplified diagram illustrating one embodiment of an access burst detector. FIG. 2 shows a small sectorized cell served by a base station using one ASIC and software. FIG. 2 shows a large non-sectorized cell served by a base station using one ASIC and software. FIG. 2 shows a small cell with six sectors served by a base station using two ASICs and software. FIG. 3 illustrates a preferred 3GPP correlator bank.

Claims (6)

An application specific integrated circuit (ASIC) used as a component in an access burst detector,
At least one application specific integrated circuit (ASIC) having a pool of reconfigurable correlators, wherein each correlator correlates an input access burst code with an input antenna output of at least one antenna at an input code phase. At least one ASIC having an antenna controller for selectively coupling any output of the at least one antenna to an input of any of the correlators. When,
A code controller capable of providing any correlator with any access burst code for providing an access burst code at the input of each correlator;
A code phase controller for controlling the input code phase of each correlator;
A connection for providing a classifier for classifying the output energy level of the correlator,
When an additional ASIC is added at Node B, the ASIC is controlled by software for reconfiguring the selective combination, each additional ASIC having a pool of reconfigurable correlators. Application specific integrated circuit (ASIC). An application specific integrated circuit (ASIC) used in a scalable Node B,
Means for receiving a signal, corresponding to an antenna for receiving a signal from a user;
A pool of reconfigurable correlators, each correlator for correlating an input access burst code with an input antenna output of at least one antenna at an input code phase, wherein at least one ASIC A pool of reconfigurable correlators having an antenna controller for selectively coupling any output of at least one antenna to an input of any of the correlators;
A circuit responsive to software for reconfiguring the selective combination when an additional ASIC is added at the scalable Node B, each additional ASIC having a pool of reconfigurable correlators. And the scalable node B comprises a circuit comprising a classifier for classifying the output energy level of the correlator, and an application specific integrated circuit (ASIC).   The application specific integrated circuit (ASIC) according to claim 1 or 2, wherein the reconfigurable correlator is a reconfigurable matched filter.   4. An application specific integrated circuit (ASIC) according to any one of the preceding claims, wherein a plurality of code generators generate a set of codes with a plurality of different delays.   4. The identification according to claim 1, wherein each ASIC further includes a plurality of code generators, and an access code generated by each code generator is reconfigurable by the software. Application specific integrated circuit (ASIC).   6. The application specific integrated circuit (ASIC) according to claim 5, wherein the code phase of the access code generated by each code generator is reconfigurable by the software.

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