JP2008078898A - Variable attenuation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a variable attenuation circuit strong against variation having linear attenuation control characteristics and excellent noise characteristics on an Si substrate. <P>SOLUTION: The variable attenuation circuit has a signal attenuation part 400 having a MOSFET 411 for variable attenuation in serial with a signal line connecting a signal input terminal 404 with a signal output terminal 405, an attenuation amount control circuit part 401 which controls gate potential of the MOSFET 411 for variable attenuation to adjust an attenuation amount and a source bias circuit part 402 for providing the MOSFET 411 for variable attenuation with a source bias. The source bias circuit part 402 has a MOSFET for bias and source potential of the MOSFET for bias is provided to source potential of the MOSFET for attenuation. In addition, a resistor 424 is added between a back gate and a substrate of the MOSFET 411 for variable attenuation, capacity 403 is added between a gate and an earth terminal and capacity 425 and a switch 426 are added between the source bias circuit part and the earth terminal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a variable attenuation circuit and a high-frequency radio circuit system using the same. In particular, the variable attenuation circuit of the present invention is used for attenuation of high-frequency signals in various wireless communication devices. It realizes linear attenuation control characteristics, improves noise characteristics, and electrical characteristics of elements depending on the manufacturing process and temperature. This is intended to correct the variation of the image.

  In recent years, semiconductor integrated circuits using field-effect transistors have been developed for high-frequency circuits in the communication field. One of the semiconductor integrated circuit blocks is an attenuation circuit that requires attenuation control (gain control).

  FIG. 2 is a circuit diagram showing a configuration of a conventional variable attenuation circuit using a GaAsFET. As shown in FIG. 2, the conventional variable attenuating circuit is attenuated by a signal attenuating unit 260 including a signal attenuating GaAsFET 240 into which a high-frequency signal inputted from a signal input terminal (IN) 231 is inserted in series. Output from the terminal (OUT) 232. The high-frequency signal input from the signal input terminal 231 includes a signal attenuation unit 261 including a signal attenuation GaAsFET 245 inserted between the signal input terminal 231 and the ground terminal (GND) 236, a signal output terminal 232, and a ground terminal. The signal is attenuated by the signal attenuating unit 262 including the signal attenuating GaAsFET 251 inserted between the signal output terminal 232 and the signal attenuating unit 262.

  At this time, the attenuation amount of the signal attenuation GaAsFETs 240, 245, and 251 can be controlled by the attenuation amount control signal input from the attenuation amount control terminal (Vc) 233. A gate bias supply resistor 255 is provided between the attenuation control terminal 233 and the signal attenuation GaAsFET 240, and a drain bias supply resistor 259 is provided between the attenuation control terminal 233 and the signal attenuation GaAsFET 245. A drain bias supply resistor 256 is provided between the attenuation control terminal 233 and the source of the signal attenuation GaAsFET 251.

  A source bias supply resistor 239 is provided between the source bias supply terminal (Vref 1) 234 of the signal attenuation GaAsFET 240 and the source of the signal attenuation GaAsFET 240, and the gate bias supply terminal (Vref 2) 235 of the signal attenuation GaAsFETs 245 and 251 is connected to the signal. A gate bias supply resistor 257 and a gate bias supply resistor 258 are provided between the gates of the attenuation GaAsFETs 245 and 251, respectively.

  In order to reduce the frequency dependence of the pass characteristic of the signal attenuation GaAsFET at the time of high attenuation, a drain bias supply resistor 241 and a source potential supply are provided between the source and drain of the signal attenuation GaAsFET 240, 245, 251 respectively. A resistor 246 and a source potential supply resistor 252 are provided.

  Reference numerals 238, 242, 243, 248, 249, and 254 are DC blocking capacitors, and reference numerals 244, 247, 250, and 253 are input / output matching resistors.

  This variable attenuation circuit connects the attenuation amount control signal supplied from the attenuation amount control terminal 233 to the gate terminal of the signal attenuation GaAsFET 240 inserted in series and the source terminal of the signal attenuation GaAsFETs 245 and 251 inserted in the shunt. This makes it possible to control the three attenuation GaAs FETs 240, 245, and 251 with one type of attenuation control signal.

In addition, as a state of the variable attenuation circuit, not only two states of a low impedance state and a high impedance state but also a continuous state from a low impedance state to a high impedance state can be taken. In general, the variable attenuation circuit is required to have linear control characteristics from a high attenuation state to a low attenuation state. However, by continuously changing the voltage value of the attenuation amount control terminal 233, the signal attenuation GaAsFET 240 is low. The resistance can be controlled to a desired attenuation from the low attenuation state of the signal attenuation GaAsFETs 245 and 251 to the high attenuation state of the signal attenuation GaAsFETs 245 and 251 having the high resistance and the signal attenuation GaAsFETs 245 and 251 from the low attenuation state. Realizes linear control characteristics.
JP 2005-27062 A

  However, in recent years, the scale of wireless circuit systems has been on an increasing trend. Conventionally, a high-frequency variable attenuation circuit configured on a single substrate such as a GaAs substrate is also different from other semiconductor circuits such as an oscillator and a mixer. It has come to be produced on the same Si semiconductor substrate. As a result, it has become necessary to produce a high-frequency variable attenuation circuit on a Si substrate having a lower substrate resistance than a GaAs process or the like.

  In addition, with recent miniaturization and multi-functionalization of wireless circuit systems, the UMTS (Universal Mobile Telecommunication System) communication system with a wide output variable range and the GSM (Global System for Mobile Communications) communication system requiring strict noise characteristics It has become necessary to fabricate a wireless circuit compatible with the multi-communication system.

  When a variable attenuation circuit corresponding to the wireless circuit system as described above is manufactured by the Si semiconductor process, there are the following five problems.

  First, when a high-frequency circuit is manufactured using a Si semiconductor substrate, signal leakage due to the influence of parasitic capacitance is a problem. Also in the variable attenuation circuit, in the high attenuation state, the signal leaks from the drain to the source side through the parasitic capacitance generated between the drain and gate of the signal attenuation MOSFET and between the gate and the source, and the isolation in the high attenuation state is performed. The characteristic is deteriorated and the attenuation control characteristic is deteriorated.

  The second problem is that noise characteristics deteriorate due to noise generated in the control circuit being mixed into the high frequency circuit. Regarding the variable attenuation circuit, noise generated in the control circuit is mixed into the high-frequency signal line through the gate of the signal attenuation MOSFET, and the recent severe noise characteristics corresponding to the multi-communication system are not satisfied.

  Thirdly, in the case of manufacturing with a Si semiconductor substrate, signal leakage due to the low substrate resistance component is a problem. Also in the variable attenuation circuit, in a high attenuation state, a signal leaks to the substrate through the back gate of the signal attenuation MOSFET, and the attenuation control characteristic is deteriorated.

  The fourth point is the influence of variations due to manufacturing processes and temperature fluctuations. As for the variable attenuation circuit, more stringent linearity is required, and there is a problem that the desired linearity is not satisfied with respect to the attenuation control characteristic due to variations in the threshold voltage of the MOSFET for signal attenuation due to the manufacturing process and temperature fluctuation. .

  The fifth point is that when a high-frequency circuit is manufactured using a Si semiconductor substrate, signal leakage due to the influence of resistance is a problem. As for the variable attenuation circuit, it is necessary to add a resistance between the source and the drain in order to supply the source bias and the drain bias and to improve the frequency characteristics. There is a problem in that the attenuation control characteristics deteriorate due to propagation between the drains.

  Accordingly, an object of the present invention is to provide a variable attenuation circuit that has linear attenuation control characteristics and excellent noise characteristics, and that is resistant to variations in MOSFET thresholds due to manufacturing processes and temperature, and a high-frequency radio circuit system using the variable attenuation circuit. It is.

  The variable attenuation circuit of the first invention is a variable attenuation circuit that solves the first, second, third, and fourth points of the above-mentioned problem. The variable attenuation circuit includes a signal attenuation unit having a signal attenuation element inserted in series in a signal path between the signal input unit and the signal output unit, an attenuation amount control circuit unit for controlling the signal attenuation element, A bias circuit unit that applies a bias that corrects the manufacturing process of the signal attenuating element and temperature variations, and a capacitor is provided between the connection part of the signal attenuating element and the attenuation amount control circuit, and a ground terminal. The signal attenuating element is configured to attenuate the high frequency signal with an attenuation amount corresponding to the attenuation amount control signal generated by the attenuation amount control circuit unit.

  In the above configuration, the signal attenuating element is generally an FET, in particular a MOSFET. The attenuation control circuit for controlling the signal attenuating element is connected to the gate terminal of the FET, and the bias circuit is the same as the signal attenuating FET. It is configured using a FET having a manufacturing process / temperature variation variation, and is connected to a source terminal and a drain terminal of the signal attenuation FET via a source bias resistor and a drain bias resistor, and the capacitor is connected to a gate terminal of the signal attenuation FET. Inserted between ground terminals. The well of the signal attenuating FET has a triple well structure, and a high resistance is inserted between the back gate and the substrate.

  According to this configuration, by having a capacitance between the gate terminal and the ground terminal of the signal attenuating FET, the signal-leakage path is blocked through the drain-gate capacitance, the gate-source capacitance, The attenuation characteristic at the time of high isolation can be improved. Further, by adopting the same configuration, it is possible to prevent noise generated in the attenuation amount control circuit unit constituted by resistors and the like from being mixed into the high-frequency signal line through the gate, and to improve noise characteristics. As a result, the first and second problems can be solved.

  In addition, the well of the signal attenuation FET has a triple well structure, and a high resistance is inserted between the back gate and the substrate, so that the signal leakage path to the substrate through the back gate is blocked and the attenuation control characteristic is improved. Can do. As a result, the third problem can be solved.

  Furthermore, the threshold of the signal attenuating FET is provided by applying the source bias of the signal attenuating FET in a bias circuit unit configured using an FET having the same manufacturing process and temperature fluctuation threshold variation as the signal attenuating FET. Value manufacturing process and temperature variations can be corrected. As a result, the fourth problem can be solved. In this case, the bias value generated in the (source) bias circuit section decreases when the threshold voltage of the signal attenuating FET increases due to the manufacturing process and temperature fluctuation, and conversely, the threshold voltage of the signal attenuating FET. It is preferable to control to increase when the value decreases.

  By combining the four points of the improvement effects, it is possible to achieve the blocking of the signal and noise leakage paths and the stabilization of the threshold voltage, and the original performance of the transistor can be utilized. As a result, a linear attenuation control characteristic can be realized in any attenuation state that continuously changes, and a variable attenuation circuit having excellent noise characteristics and resistant to variations can be realized.

  A variable attenuation circuit according to a second aspect of the invention is a variable attenuation circuit that solves the second, third, and fourth points of the above-described problem. The variable attenuation circuit includes a signal attenuation unit having a signal attenuation element inserted into a ground terminal from a signal path between the signal input unit and the signal output unit, and an attenuation amount control circuit unit that controls the signal attenuation element. A bias circuit unit that applies a bias that corrects the manufacturing process of the signal attenuating element and temperature variations, and a capacitor is connected between the connection part of the signal attenuating element and the attenuation control circuit unit, and a ground terminal. The signal attenuating element has a configuration for attenuating the high frequency signal with an attenuation amount corresponding to the attenuation amount control signal generated by the attenuation amount control circuit unit.

  In the above configuration, the signal attenuating element is generally an FET, the attenuation control circuit unit for controlling the signal attenuating element is connected to the source terminal of the FET, and the bias circuit unit is the same manufacturing process as the signal attenuating FET. The signal attenuating FET is configured by using an FET having temperature fluctuation variation, and the capacitor is inserted between the gate terminal of the signal attenuating FET and the ground terminal. The well of the signal attenuating FET has a triple well structure, and a high resistance is inserted between the back gate and the substrate.

  According to this configuration, since the capacitance is provided between the gate terminal and the ground terminal of the signal attenuating FET, noise generated in the gate bias circuit unit configured by a resistor or the like is transmitted through the gate to the high frequency signal line. Can be prevented, and noise characteristics can be improved. As a result, the second problem can be solved.

  In addition, the well of the signal attenuation FET has a triple well structure, and a high resistance is inserted between the back gate and the substrate, so that the signal leakage path to the substrate through the back gate is blocked and the attenuation control characteristic is improved. Can do. As a result, the third problem can be solved.

  Furthermore, the threshold of the signal attenuating FET is provided by applying a gate bias of the signal attenuating FET in a bias circuit unit configured using an FET having the same manufacturing process and temperature fluctuation threshold variation as the signal attenuating FET. Value manufacturing process and temperature variations can be corrected. As a result, the fourth problem can be solved. In this case, the bias value generated in the (gate) bias circuit section increases when the threshold voltage of the signal attenuating FET increases due to the manufacturing process and temperature fluctuation, and conversely, the threshold voltage of the signal attenuating FET. It is preferable to control to decrease when the value decreases.

  By combining the above three improvements, signal and noise leakage paths and threshold voltage stabilization can be achieved, and the original performance of the transistor can be utilized. As a result, a linear attenuation control characteristic can be realized in any attenuation state that continuously changes, and a variable attenuation circuit having excellent noise characteristics and resistant to variations can be realized.

  A variable attenuation circuit according to a third aspect of the present invention is a variable attenuation circuit that solves the first, second, third, fourth, and fifth points of the above problem. The variable attenuation circuit includes a signal attenuation unit having a signal attenuation element inserted in series in a signal path between the signal input unit and the signal output unit, an attenuation amount control circuit unit for controlling the signal attenuation element, A bias circuit unit that applies a bias that corrects the manufacturing process of the signal attenuating element and temperature variations, and a capacitor is provided between the connection part of the signal attenuating element and the attenuation amount control circuit, and a ground terminal. A capacitor and a switch between a connection portion of the signal attenuation element and the bias circuit section and a ground terminal, the signal attenuation element corresponding to the attenuation control signal generated by the attenuation control circuit section The high frequency signal is attenuated by the amount of attenuation.

  In the above configuration, the signal attenuating element is generally preferably an FET, the attenuation control circuit unit for controlling the signal attenuating element is connected to the gate terminal of the FET, and the bias circuit unit is the same manufacturing process as the signal attenuating FET. It is configured by using an FET having a variation in temperature, and is connected to the source terminal and the drain terminal of the signal attenuating FET through a source bias resistor and a drain bias resistor. The capacitance added to the connection part between the signal attenuation element and the attenuation control circuit is inserted between the gate terminal and the ground terminal of the signal attenuation FET and added to the connection part between the signal attenuation element and the bias circuit part. The capacitance thus inserted is inserted between the connection portion of the source bias resistor and the drain bias resistor of the signal attenuating FET and the ground terminal. The well of the signal attenuating FET has a triple well structure, and a high resistance is inserted between the back gate and the substrate.

  According to this configuration, by having a capacitance between the gate terminal and the ground terminal of the signal attenuating FET, the signal-leakage path is blocked through the drain-gate capacitance, the gate-source capacitance, The attenuation characteristic at the time of high isolation can be improved. Further, by adopting the same configuration, it is possible to prevent noise generated in the attenuation amount control circuit unit constituted by resistors and the like from being mixed into the high-frequency signal line through the gate, and to improve noise characteristics. As a result, the first and second problems can be solved.

In addition, the well of the signal attenuation FET has a triple well structure, and a high resistance is inserted between the back gate and the substrate, so that the signal leakage path to the substrate through the back gate is blocked and the attenuation control characteristic is improved. Can do. As a result, the third problem can be solved.
Furthermore, the threshold of the signal attenuating FET is provided by applying the source bias of the signal attenuating FET in a bias circuit unit configured using an FET having the same manufacturing process and temperature fluctuation threshold variation as the signal attenuating FET. Value manufacturing process and temperature variations can be corrected. As a result, the fourth problem can be solved. In this case, the bias value generated in the (source) bias circuit section decreases when the threshold voltage of the signal attenuating FET increases due to the manufacturing process and temperature fluctuation, and conversely, the threshold voltage of the signal attenuating FET. It is preferable to control to increase when the value decreases.

  Furthermore, by having a capacitor and a switch between the source bias resistor and drain bias resistor connection portion of the signal attenuating FET and the ground terminal, the input terminal is changed to the output terminal via the source bias resistor and the drain bias resistor. It is possible to block the signal leakage path and improve the attenuation characteristic at the time of high isolation. As a result, the fifth problem can be solved.

  By combining the improvement effects of the above five points, the signal leakage path can be cut off more than the variable attenuation circuit of the first invention, the leakage path of the circuit equivalent noise of the first invention is cut off, and the threshold voltage is stabilized. This makes it possible to achieve the maximum performance of the original characteristics of the transistor, such as attenuation characteristics and noise characteristics. As a result, a linear attenuation control characteristic can be realized in any attenuation state that continuously changes, and a variable attenuation circuit having excellent noise characteristics and resistant to variations can be realized.

  According to a fourth aspect of the present invention, there is provided a radio transmission apparatus including at least one variable attenuation circuit according to the first, second, or third aspect, at least one oscillator, and at least one high-frequency amplifier, and radio transmission. And at least one antenna connected to the apparatus for transmitting and receiving radio frequencies.

  According to this configuration, the same effects as those of the first, second, or third invention can be obtained.

  Hereinafter, each claim will be described.

  The variable attenuating circuit according to claim 1 includes a signal attenuating unit having a signal attenuating element inserted in series in a signal path between the signal input unit and the signal output unit, and an attenuation amount control signal in the signal attenuating element. Attenuation amount control circuit section for providing a bias, a bias circuit section for applying a bias to the signal attenuation element, a capacitance connected between a connection portion between the signal attenuation element and the attenuation amount control circuit section and a ground terminal And.

  The variable attenuation circuit according to claim 2 is the variable attenuation circuit according to claim 1, wherein the signal attenuating element is an FET, and the attenuation amount control circuit unit applies an attenuation amount control signal to the gate terminal of the FET. The ON resistance of the FET is controlled, the bias circuit unit applies a bias to the source terminal of the FET, and the capacitor is connected between the gate terminal of the FET and the ground terminal.

  The variable attenuation circuit according to claim 3 is a signal attenuator having a signal attenuating FET inserted in series in a signal path between a signal input unit and a signal output unit, and attenuating the gate terminal of the signal attenuating FET. An attenuation amount control circuit unit that provides an amount control signal to control the ON resistance of the signal attenuation FET; and a bias circuit unit that applies a bias to the source terminal of the signal attenuation FET. It has a bias FET that compensates for variations in threshold voltage of the signal attenuating FET.

  5. The variable attenuation circuit according to claim 4, wherein a signal attenuation unit having a signal attenuation FET inserted in series in a signal path between the signal input unit and the signal output unit and the gate terminal of the signal attenuation FET are attenuated. Attenuation amount control circuit unit for supplying an amount control signal to control the ON resistance of the signal attenuation FET, a bias circuit unit for applying a bias to the source terminal of the signal attenuation FET, and a back gate unit of the signal attenuation FET And a resistor connected between the substrates.

  The variable attenuating circuit according to claim 5 is a signal attenuating unit having a signal attenuating FET inserted in series in a signal path between a signal input unit and a signal output unit, and attenuating the gate terminal of the signal attenuating FET. An attenuation amount control circuit unit that provides an amount control signal to control the ON resistance of the signal attenuation FET, a bias circuit unit that applies a bias to the source terminal of the signal attenuation FET, and between the bias circuit unit and the ground terminal It has a connected capacity or capacity and a switch.

  6. The variable attenuation circuit according to claim 6, wherein an FET is inserted and connected in a signal path between the signal input unit and the signal output unit, and the signal applied to the signal input unit is attenuated by a signal applied to the gate terminal of the FET. A signal attenuating unit that controls and outputs the amount, an attenuation amount control circuit unit that applies a signal to the gate terminal to vary the ON resistance value of the FET, and the other end of the resistance element having one end connected to the source terminal of the FET and the ground A first capacitive element is connected between the terminals, and a bias circuit section for applying a DC voltage via the resistance element and a resistor connected between the back gate section of the FET and the ground terminal are provided. The gate terminal and the ground terminal A second capacitor element is connected between them.

The variable attenuation circuit according to claim 7, wherein the signal attenuation unit includes a signal attenuation element inserted between the signal path between the signal input unit and the signal output unit and the ground terminal,
An attenuation control circuit unit for supplying an attenuation control signal to the signal attenuation element;
A bias circuit section for applying a bias to the signal attenuating element;
And a capacitor connected between a connection portion between the signal attenuating element and the bias circuit portion and the ground terminal.

  The variable attenuation circuit according to claim 8 is the variable attenuation circuit according to claim 7, wherein the signal attenuating element is an FET, and the attenuation amount control circuit unit applies an attenuation amount control signal to the drain terminal of the FET. The ON resistance of the FET is controlled, the bias circuit unit applies a bias to the gate terminal of the FET, and the capacitor is connected between the gate terminal of the FET and the ground terminal.

  The variable attenuating circuit according to claim 9 includes a signal attenuating unit having a signal attenuating FET inserted between a signal path between the signal input unit and the signal output unit and a ground terminal, and the signal attenuating FET. The bias circuit includes: an attenuation amount control circuit unit that applies an attenuation amount control signal to the drain terminal to control the ON resistance of the signal attenuation FET; and a bias circuit unit that applies a bias to the gate terminal of the signal attenuation FET. The unit includes a bias FET that compensates for variations in threshold voltage of the signal attenuating FET.

  The variable attenuation circuit according to claim 10 includes a signal attenuation unit having a signal attenuation FET inserted between a signal path between the signal input unit and the signal output unit and a ground terminal, and the signal attenuation FET. Attenuation amount control circuit unit for applying an attenuation amount control signal to the drain terminal to control the ON resistance of the signal attenuation FET, a bias circuit unit for applying a bias to the gate terminal of the signal attenuation FET, and the signal attenuation FET A back gate portion and a resistor connected between the substrate.

  The variable attenuation circuit according to claim 11 is configured such that a first capacitive element and a current path terminal pair of the FET are inserted and connected in series between the signal path between the signal input unit and the signal output unit and the AC ground. A signal attenuating unit for controlling and outputting the attenuation amount of the signal applied to the signal input unit by a signal applied to the connection part between the capacitive element and one end of the current path of the FET, and a signal applied to one end of the FET Attenuation amount control circuit section that varies the ON resistance value, a bias circuit section that applies a DC voltage to the gate terminal of the FET via a resistance element, and a resistor connected between the back gate section of the FET and the ground terminal, A second capacitor element is connected between the gate terminal and the ground terminal.

  The variable attenuation circuit according to claim 12 includes a first signal attenuation unit having a first signal attenuation element inserted in series in a signal path between a signal input unit and a signal output unit, and the first signal attenuation unit. A first attenuation control circuit that applies an attenuation control signal to the signal attenuating element; a first bias circuit that applies a bias to the first signal attenuating element; and the first signal attenuating element; A first capacitor connected between a connection portion to the first attenuation control circuit portion and a ground terminal, and a signal path between the signal input portion and the signal output portion and a ground terminal. A second signal attenuating section having a second signal attenuating element inserted into the second signal attenuating element, a second attenuation amount control circuit section for supplying the attenuation amount control signal to the second signal attenuating element, and the second A second bias circuit section for applying a bias to the signal attenuating element, and the second signal attenuating element And a second capacitor connected between a connection portion between the child second bias circuit section and the ground terminal.

  A variable attenuation circuit according to a thirteenth aspect is the variable attenuation circuit according to the twelfth aspect, wherein the first signal attenuation element includes a first FET, and the first attenuation amount control circuit unit includes the first attenuation amount control circuit unit. An attenuation control signal is supplied to the gate terminal of the FET to control the ON resistance of the first FET, the first bias circuit section applies a bias to the source terminal of the first FET, and the first capacitor Is connected between the gate terminal of the first FET and the ground terminal, the second signal attenuating element comprises a second FET, and the second attenuation control circuit unit An attenuation control signal is supplied to the drain terminal of the FET to control the ON resistance of the second FET, and the second bias circuit unit applies a bias to the gate terminal of the second FET, and the second capacitor Is the gate terminal of the second FET The serial is connected between the ground terminal.

The variable attenuation circuit according to claim 14 includes a first signal attenuation unit having a first signal attenuation FET inserted in series in a signal path between a signal input unit and a signal output unit, and the first signal attenuation unit. A first attenuation amount control circuit for controlling an ON resistance of the first signal attenuation FET by applying an attenuation amount control signal to the gate terminal of the signal attenuation FET; and a source terminal of the first signal attenuation FET And a second signal attenuating FET inserted between a signal path between the signal input unit and the signal output unit and a ground terminal. An attenuating unit; a second attenuating amount control circuit unit that applies an attenuating amount control signal to the drain terminal of the second signal attenuating FET to control the ON resistance of the second signal attenuating FET; Apply a bias to the gate terminal of the signal attenuating FET And a second bias circuit portion, the first bias circuit portion includes a first bias FET to compensate for threshold voltage variation of the first signal attenuating FET,
The second bias circuit section includes a second bias FET that compensates for variations in threshold voltage of the second signal attenuating FET.

  The variable attenuation circuit according to claim 15, wherein the first signal attenuation unit includes a first signal attenuation FET inserted in series in a signal path between the signal input unit and the signal output unit, and the first signal attenuation unit. A first attenuation amount control circuit for controlling an ON resistance of the first signal attenuation FET by applying an attenuation amount control signal to the gate terminal of the signal attenuation FET; and a source terminal of the first signal attenuation FET And a second signal attenuating FET inserted between a signal path between the signal input unit and the signal output unit and a ground terminal. An attenuating unit; a second attenuating amount control circuit unit that applies an attenuating amount control signal to the drain terminal of the second signal attenuating FET to control the ON resistance of the second signal attenuating FET; Apply a bias to the gate terminal of the signal attenuating FET A second bias circuit section; a first resistor connected between the back gate section of the first signal attenuating FET and the substrate; and a connection between the back gate section of the second signal attenuating FET and the substrate. A second resistor.

  The variable attenuating circuit according to claim 16 includes a first signal attenuating unit having a first signal attenuating FET inserted in series in a signal path between a signal input unit and a signal output unit, and the first signal attenuating unit. A first attenuation amount control circuit for controlling an ON resistance of the first signal attenuation FET by applying an attenuation amount control signal to the gate terminal of the signal attenuation FET; and a source terminal of the first signal attenuation FET And a second signal attenuating FET inserted between a signal path between the signal input unit and the signal output unit and a ground terminal. An attenuating unit; a second attenuating amount control circuit unit that applies an attenuating amount control signal to the drain terminal of the second signal attenuating FET to control the ON resistance of the second signal attenuating FET; Apply a bias to the gate terminal of the signal attenuating FET Comprising a second bias circuit portion, and a capacitance or capacitor and a switch connected between the first bias circuit ground terminal.

  The variable attenuation circuit according to claim 17 is the variable attenuation circuit according to claim 16, wherein a first resistor is connected between the back gate portion of the first signal attenuating FET and the ground terminal, and the second signal attenuating circuit is attenuated. A second resistor is connected between the back gate portion of the FET and the ground terminal.

  A high-frequency radio circuit system according to claim 18 includes at least one variable attenuation circuit according to any one of claims 1 to 17, at least one high-frequency amplifier circuit, and at least one oscillator. A wireless transmission device; and an antenna connected to the wireless transmission device for transmitting a radio frequency.

  According to the structure of this invention, there exists an effect similar to the variable attenuation circuit of Claims 1-17.

  According to the variable attenuation circuit and the high-frequency wireless circuit system of the present invention, the isolation characteristic at the time of high attenuation can be obtained by blocking the signal leakage path through the parasitic capacitance generated between the drain and gate and between the gate and source. Can improve. At the same time, it is possible to prevent noise or the like generated in the attenuation amount control circuit unit from entering the signal line via the gate. In addition, since a high resistance is inserted between the back gate and the substrate, a path through which a signal leaks to the substrate through the back gate can be blocked, and the attenuation control characteristic can be improved. Further, it can be made less susceptible to variations in the threshold value of the signal attenuating FET due to manufacturing processes and temperature fluctuations. And by having a capacitor and a switch between the connection point of the source bias resistor and drain bias resistor and the ground terminal, the path through which the signal leaks from the input terminal to the output terminal is cut off via the source bias resistor and drain bias resistor. In addition, the attenuation characteristic at the time of high isolation can be improved. With all the above effects, linear attenuation control characteristics can be realized continuously over a wide range from a high attenuation state to a low attenuation state. As a result, it has become possible to fabricate a variable attenuation circuit compatible with the multi-band / multi-communication method, which has been difficult due to signal leakage, noise, and process variations, by the Si process.

(First embodiment)
The first embodiment of the present invention is a variable attenuation circuit (integrated circuit) corresponding to the first, second, third, and fourth points of the problem. Hereinafter, a description will be given with reference to FIG.

  The variable attenuation circuit according to the first embodiment of the present invention shown in FIG. 1 is an attenuation circuit that attenuates a high-frequency signal input from a signal input terminal 104 and outputs the attenuated signal from a signal output terminal 105. The attenuation amount is an external terminal. A variable attenuation circuit that can be controlled by 106 is assumed. Further, it is assumed that this variable attenuation circuit is manufactured on, for example, a Si semiconductor substrate.

  Specifically, the variable attenuation circuit according to the present invention includes a signal attenuation unit 100 having a signal attenuation MOSFET (signal attenuation element) 111 inserted in series between the signal input terminal 104 and the signal output terminal 105; The signal attenuation MOSFET 111 includes an attenuation amount control circuit unit 101 that controls the ON resistance of the signal attenuation MOSFET 111 and a source bias circuit unit 102 that applies a bias to the source of the signal attenuation MOSFET 111. The signal attenuation MOSFET 111 includes an attenuation amount control circuit unit 101. The high frequency signal is attenuated by an attenuation amount corresponding to the attenuation amount control signal generated in step (1).

  In this variable attenuation circuit, a capacitor 103 is added between the gate of the signal attenuation MOSFET 111 and the ground terminal. There are two major effects of this capacitor 103. The first point is to prevent the noise component generated in the attenuation control circuit unit 101 from entering the high frequency signal line (the line from the signal input terminal 104 to the signal output terminal 105) via the gate of the signal attenuation MOSFET 111. It is. The second point is that the high-frequency signal is prevented from leaking between the signal input terminal 104 and the signal output terminal 105 in a high attenuation state due to the influence of the parasitic capacitance generated between the drain and gate and the gate and source of the signal attenuation MOSFET 111. That is.

  Further, the source bias circuit section 102 of this variable attenuation circuit generates a bias voltage by using the source bias generation MOSFET 117 having the same threshold voltage fluctuation (temperature characteristic) as the signal attenuation MOSFET 111, thereby reducing the signal attenuation. This has the effect of correcting variations in threshold voltage due to the manufacturing process and temperature of the MOSFET 111.

  In addition, the well of the signal attenuation MOSFET 111 of this variable attenuation circuit has a triple well structure, and a high resistance 124 is added between the back gate portion and the substrate. The effect of the high resistance 124 is to prevent signals from leaking to the substrate through the back gate. High resistance means a resistance having a high resistance value.

  The circuit connection of the variable attenuation circuit will be specifically described below.

  First, as the signal attenuating element, for example, an N-channel MOSFET having a triple well structure is suitable. The signal attenuating MOSFET 111 is inserted in series in the signal path between the signal input terminal 104 and the signal output terminal 105 of the high frequency variable attenuating circuit, and a DC is interposed between the signal input terminal 104 and the signal attenuating MOSFET 111. A DC blocking capacitor 112 that blocks components and passes only high-frequency components is inserted, and a DC blocking capacitor 113 is also inserted between the signal attenuation MOSFET 111 and the signal output terminal 105. A high resistance 124 for blocking signal leakage is inserted between the back gate portion of the signal attenuating MOSFET 111 and the substrate.

  Next, the attenuation amount control circuit unit 101 is connected to the gate of the signal attenuation MOSFET 111. The configuration of the attenuation control circuit unit 101 will be described. The attenuation control resistor 115 and the attenuation control resistor 116 are connected in series, the other terminal of the resistor 115 is connected to the gain control terminal (Vc) 106, and the other terminal of the resistor 116 is connected to the ground terminal. It is connected. A resistor 114 having a high resistance value that cuts off the high frequency and allows only DC to pass is connected between the connection portion of the resistor 115 and the resistor 116 and the gate of the signal attenuating MOSFET 111. Further, a capacitor 103 is added between the gate of the signal attenuation MOSFET 111 and the ground terminal.

  The source bias circuit unit 102 connected to the source terminal of the signal attenuation MOSFET 111 will be described. The resistor 120 and the resistor 121 are connected in series, the other terminal of the resistor 120 is connected to the power supply voltage terminal (Vdd) 107, and the other terminal of the resistor 121 is connected to the ground terminal. The gate of the source bias generation MOSFET 117 is connected to the connection portion between the resistor 120 and the resistor 121, and the source bias generation MOSFET 117 has the same manufacturing process and temperature variation variation as the signal attenuation MOSFET 111. A resistor 118 is connected between the drain of the source bias generating MOSFET 117 and the power supply voltage terminal 107, and a resistor 119 is connected between the source of the source bias generating MOSFET 117 and the ground terminal. Also, a resistor 122 having a high resistance value that cuts off the high frequency and passes only DC is connected between the source of the source bias generating MOSFET 117 and the source of the signal attenuating MOSFET 111, and the source of the source bias generating MOSFET 117 and the signal attenuation are connected. A resistor 123 having a high resistance value that cuts off the high frequency and passes only DC is connected between the drain of the MOSFET 111 for use.

  In recent years, wireless communication systems have become multiband and multicommunication systems. Among them, for example, there are multi-communication systems such as a UMTS communication system and a GSM communication system. In the UMTS communication system, the transmission circuit requires a transmission power variable range of 80 dB or more, and high-accuracy transmission power control linearity is required. Further, the GSM communication system requires high noise characteristics. The variable attenuation circuit used in the high-frequency wireless transmission circuit block must satisfy the characteristics of these two communication methods. In that case, high linearity and noise characteristics are required regardless of process variations and temperature fluctuations. A method for satisfying each requirement will be described.

  First, a method for realizing highly accurate linearity regardless of process variations and temperature variations will be described. FIG. 8 is a diagram showing the variation of each voltage value with respect to the temperature of the variable attenuation circuit as shown in FIG. 2, and FIG. 9 is a diagram showing the gain characteristic with respect to the control voltage. In FIG. 8, the horizontal axis represents temperature, and the vertical axis represents voltage value. In FIG. 9, the horizontal axis represents the attenuation control voltage Vc, the vertical axis represents the gain of the variable attenuation circuit, and represents three control characteristics at normal temperature, low temperature, and high temperature.

  8, Vg represents the gate potential of the signal attenuating GaAsFET 240 of FIG. 2, Vref represents the potential applied to the source bias supply terminal 234 of FIG. 2, that is, the source potential of the signal attenuating GaAsFET 240, and Vth 2 represents the threshold voltage Vth of the signal attenuation GaAsFET 240 of FIG. Vg−Vref−Vth is a calculation result calculated using Vg, Vref, and Vth shown in FIG. When Vg−Vref−Vth> 0, the signal attenuating GaAsFET 240 starts to operate, the ON resistance begins to decrease gradually, and the attenuation decreases gradually. This point is point A in FIG. 9, and the voltage at this time is Va. Here, when the temperature rises, the threshold voltage Vth of the signal attenuation GaAsFET 240 increases as the temperature rises. Therefore, in order to set Vg−Vref−Vth = 0, a larger Vg than normal temperature is required, and the voltage value at which the signal attenuating GaAsFET 240 starts to operate increases and increases from Va to Vb. On the other hand, when the temperature decreases, the signal attenuating GaAsFET 240 starts to operate at a smaller Vg and decreases from Va to Vc. As a result, the control characteristics vary greatly depending on the temperature as shown in FIG. 9, and the linearity deteriorates.

  FIG. 10 is a diagram showing the variation of each voltage value with respect to the temperature of the variable attenuation circuit when the source bias circuit unit 102 as shown in FIG. 1 is used, and FIG. 11 shows the gain characteristic with respect to the control voltage at that time. FIG. In FIG. 10, unlike FIG. 8, the configuration is such that Vref decreases as the temperature rises. As a result, Vg−Vref−Vth is always constant regardless of temperature fluctuations even when the temperature increases and the threshold voltage Vth increases, or when the temperature decreases and the threshold voltage Vth decreases. It is possible to draw the same control characteristics as shown in FIG.

  The circuit operation for realizing the variation correction as shown in FIG. 11 will be described using the variable attenuation circuit of FIG. The gate potential of the source bias generation MOSFET 117 of the source bias circuit unit 102 in FIG. 1 is determined by resistance division of the resistor 120 and the resistor 121. Like the signal attenuation MOSFET 111, the source bias generation MOSFET 117 has a characteristic that the threshold voltage increases as the temperature rises. Therefore, the threshold voltage increases as the temperature rises, while the gate potential is constant. Therefore, the source potential decreases and the current flowing through the source bias generation MOSFET 117 decreases. As a result, the source bias potential of the signal attenuating MOSFET 111 is reduced, and the threshold voltage fluctuation can be corrected.

  Next, circuit operation for realizing linear control characteristics will be described using the variable attenuation circuit of FIG. A continuous control voltage from 0 V to the power supply voltage potential is input to the control terminal (Vc) 106 of the attenuation control circuit unit 101 in FIG. This control voltage is divided by the resistors 115 and 116 and input to the gate of the signal attenuating MOSFET 111. The signal attenuating MOSFET 111 is used with a drain-source bias of 0 V. When the gate potential is 0 V, the ON resistance is the largest. As the gate potential increases, the ON resistance gradually decreases, and the gate potential becomes the power supply voltage. Then, the ON resistance is minimized. As the ON resistance changes, the attenuation of the pass characteristic from the signal input terminal 104 to the signal output terminal 105 also varies. Further, any control characteristic can be realized by dividing the voltage between the resistor 115 and the resistor 116.

  However, when a variable attenuation circuit is realized with, for example, a Si substrate, a signal leaks due to the parasitic capacitance generated between the drain and gate of the signal attenuating MOSFET 111 and between the gate and the source, and the ON resistance of the signal attenuating MOSFET 111 The determined amount of attenuation cannot be obtained, and linearity cannot be ensured. In order to eliminate the influence, the capacitor 103 is inserted between the gate of the signal attenuation MOSFET 111 and the ground. By inserting a capacitor, a signal leakage path is interrupted between the drain and gate of the signal attenuating MOSFET 111 and between the gate and source, thereby ensuring linearity.

  Also, as described above, for example, when a variable attenuation circuit is realized with a Si substrate, the impedance between the back gate of the signal attenuation MOSFET 111 and the substrate is low due to the low substrate resistance, and the signal is transmitted to the substrate through this portion. The amount of attenuation determined by the ON resistance of the signal attenuation MOSFET 111 cannot be obtained, and linearity cannot be ensured. In order to eliminate the influence, for example, the MOSFET 111 is manufactured in a triple well structure, and a high resistance is inserted between the back gate of the MOSFET 111 and the substrate, thereby blocking a signal leakage path and ensuring linearity.

  In addition, this variable attenuation circuit has improved noise characteristics due to the addition of the capacitor 103. The attenuation amount control circuit unit 101 is usually composed of a resistor. Therefore, the noise generated by this resistor is mixed through the gate of the signal attenuating MOSFET 111 and is applied to the high frequency signal input from the signal input terminal 104 to deteriorate the noise characteristics. For example, the reception band noise of the GSM communication system, etc. The requirement is not met.

  However, by adding the capacitor 103, the noise generated in the attenuation control circuit unit 101 is cut off by the filter effect of the capacitor 103 and the resistor 114, and the noise characteristic is improved in any state of the continuously changing variable attenuation circuit. Can do.

  As described above, by adding the source bias circuit section 102, the capacitor 103, and the back gate additional high resistance 124 to the variable attenuation circuit having the signal attenuation MOSFET 111, the signal attenuation MOSFET 111 due to variations in manufacturing process and temperature variation can be reduced. Threshold variations can be corrected, and signal leakage in the signal attenuation MOSFET 111 can be eliminated in any attenuation state, thereby improving linearity. Furthermore, noise generated in the attenuation control circuit unit 101 can be reduced, and noise characteristics can be improved. As a result, a variable attenuation circuit compatible with the multi-band multi-communication system can be realized by the Si process, and can be made into one chip with other radio circuit blocks.

  Note that only one or only two of the source bias circuit unit 102, the capacitor 103, and the back gate additional high resistance 124 may be connected. The MOSFET may be a P-channel MOSFET. Further, it is sufficient that the same effect can be exhibited even if the triple well structure is not used.

(Second Embodiment)
The second embodiment of the present invention is a variable attenuation circuit (integrated circuit) corresponding to the first, second, third, and fourth points of the problem. Hereinafter, a description will be given with reference to FIG.

  The variable attenuation circuit according to the second embodiment of the present invention shown in FIG. 3 is an attenuation circuit that attenuates a high-frequency signal input from the signal input terminal 304 and outputs the attenuated signal from the signal output terminal 305. The attenuation amount is an external terminal. A variable attenuation circuit that can be controlled by 306 is assumed. Further, it is assumed that this variable attenuation circuit is manufactured on, for example, a Si semiconductor substrate.

  Specifically, the variable attenuation circuit according to the present invention includes a signal attenuation MOSFET (signal attenuation element) 311 inserted between a signal path between the signal input terminal 304 and the signal output terminal 305 and the ground terminal. The signal attenuating unit 300, the attenuation control circuit unit 301 that controls the ON resistance of the signal attenuating MOSFET 311, and the gate bias circuit unit 302 that applies a bias to the gate of the signal attenuating MOSFET 311. Then, the high frequency signal is attenuated by an attenuation amount corresponding to the attenuation amount control signal generated by the attenuation amount control circuit unit 301.

  In this variable attenuation circuit, a capacitor 303 is added between the gate of the signal attenuation MOSFET 311 and the ground terminal. The effect of the capacitor 303 is to prevent a noise component generated in the gate bias circuit unit 302 from entering the high frequency signal line through the gate of the signal attenuating MOSFET 311.

  Furthermore, the gate bias circuit section 302 of this variable attenuation circuit creates a bias using the gate bias generation MOSFET 318 having the same threshold voltage fluctuation as the signal attenuation MOSFET 311, thereby producing the signal attenuation MOSFET 311 manufacturing process, It has the effect of correcting variations in threshold voltage due to temperature.

  In addition, the well of the signal attenuation MOSFET 311 of this variable attenuation circuit has a triple well structure, and a high resistance 325 is added between the back gate portion and the substrate. The effect of the high resistance 325 is to prevent signals from leaking to the substrate through the back gate.

  The circuit connection of the variable attenuation circuit will be specifically described below.

  First, the signal attenuating element is preferably an N-channel MOSFET having a triple well structure, for example. The signal attenuating MOSFET 311 is inserted between the signal path between the signal input terminal 304 and the signal output terminal 305 of the high frequency variable attenuation circuit and the ground terminal, and between the signal input terminal 304 and the signal attenuating unit 300. Includes a DC blocking capacitor 312 that blocks a DC component and passes only a high-frequency component, and a DC blocking capacitor 313 is also inserted between the signal attenuating unit 300 and the signal output terminal 305. . 314 is an impedance adjusting resistor, and 315 and 316 are DC blocking capacitors. Reference numeral 324 denotes a source bias generating resistor. A high resistance 325 for blocking signal leakage is inserted between the back gate portion of the signal attenuating MOSFET 311 and the substrate.

  Next, an attenuation amount control circuit unit 301 is connected to the drain of the signal attenuation MOSFET 311. The attenuation control circuit unit 301 has a configuration in which a resistor 317 having a high resistance value that blocks only a DC and passes only DC is connected between the gain control terminal (Vc) 306 and the drain of the signal attenuation MOSFET 311. is doing.

  Next, the gate bias circuit unit 302 connected to the gate of the signal attenuation MOSFET 311 will be described. The resistor 319 and the resistor 320 are connected in series, the other terminal of the resistor 319 is connected to the power supply voltage terminal (Vdd) 307, and the other terminal of the resistor 320 is connected to the ground terminal. The gate of the gate bias generation MOSFET 318 is connected to the connection portion between the resistor 319 and the resistor 320, and the gate bias generation MOSFET 318 has the same manufacturing process and temperature variation variation as the signal attenuation MOSFET 311. A resistor 321 is connected between the drain of the gate bias generating MOSFET 318 and the power supply voltage terminal (Vdd) 307, and a resistor 322 is connected between the source of the gate bias generating MOSFET 318 and the ground terminal. . Further, a resistor 323 having a high resistance value that blocks high frequency and allows only DC to pass is connected between the drain of the gate bias generating MOSFET 318 and the gate of the signal attenuating MOSFET 311. Further, a capacitor 303 is added between the gate of the signal attenuation MOSFET 311 and the ground terminal.

  In the second embodiment, a method for realizing highly accurate linearity regardless of process variations and temperature variations will be described. The difference between FIG. 3 and FIG. 1 is whether the attenuation control circuit unit is connected to the gate or the drain. In FIG. 3, the attenuation control circuit unit is connected to the drain. Is connected to the gate.

  FIG. 12 is a diagram showing the variation of each voltage value with respect to the temperature of the variable attenuation circuit as shown in FIG. 3, and FIG. 13 is a diagram showing the gain characteristic with respect to the control voltage at that time. In FIG. 12, Vref represents the gate potential of the signal attenuation MOSFET 311 in FIG. 3, Vc represents the drain potential of the signal attenuation MOSFET 311, and Vth represents the threshold voltage Vth of the signal attenuation MOSFET 311. .

  Vref−Vc−Vth is a calculation result calculated using Vref, Vc, and Vth shown in FIG. When Vref−Vc−Vth> 0, the FET starts to operate, the ON resistance begins to decrease gradually, and the attenuation decreases gradually. In FIG. 12, Vref is decreased as the temperature rises. As a result, Vref−Vc−Vth is always constant regardless of temperature fluctuations even when the temperature increases and the threshold voltage Vth increases, or when the temperature decreases and the threshold voltage Vth decreases. It is possible to draw the same control characteristics as shown in FIG.

  A circuit operation for realizing the variation correction as shown in FIG. 13 will be described using the variable attenuation circuit of FIG. The gate potential of the gate bias generation MOSFET 318 of the gate bias circuit unit 302 in FIG. 3 is determined by resistance division between the resistor 319 and the resistor 320. Since the gate bias generation MOSFET 318 has the characteristic that the threshold voltage increases as the temperature rises, like the signal attenuation MOSFET 311, the threshold voltage increases as the temperature rises, while the gate potential remains constant. Therefore, the source potential decreases and the current flowing through the gate bias generation MOSFET 318 decreases. As a result, the voltage drop due to the bias resistor 321 is also reduced, the drain potential of the gate bias generating MOSFET 318 is increased, the gate bias potential of the signal attenuating MOSFET 311 is increased, and correction of threshold voltage fluctuation can be realized.

  Next, circuit operation for realizing linear control characteristics will be described using the variable attenuation circuit of FIG. A continuous control voltage from 0 V to the power supply voltage potential is input to the control terminal (Vc) 306 of the attenuation control circuit unit 301 in FIG. This control voltage is input to the drain potential of the attenuation control MOSFET 311. The signal attenuating MOSFET 311 is used in a state where the drain-source bias is 0 V, and when the drain potential is the power supply voltage, the ON resistance is the largest. As the drain potential decreases, the ON resistance gradually decreases. Is 0V and the ON resistance is minimized. As the ON resistance changes, the attenuation amount of the pass characteristic from the signal input terminal 304 to the signal output terminal 305 also varies.

  However, when a variable attenuation circuit is realized with, for example, a Si substrate, the impedance between the back gate and the substrate of the signal attenuation MOSFET 111 is low due to the low substrate resistance, and the signal leaks to the substrate through this portion. The attenuation determined by the ON resistance of the MOSFET 311 for attenuation cannot be obtained, and linearity cannot be ensured. In order to eliminate the influence, for example, the MOSFET 311 is manufactured in a triple well structure, and a high resistance is inserted between the back gate of the MOSFET 311 and the substrate, thereby blocking a signal leakage path and ensuring linearity.

  In addition, this variable attenuation circuit has improved noise characteristics due to the addition of the capacitor 303.

  The threshold voltage compensation gate bias circuit unit 302 is generally composed of a resistor and a transistor. Therefore, noise generated by these resistors and transistors is mixed through the gate of the signal attenuating MOSFET 311 and is applied to the high frequency signal input from the signal input terminal 304, thereby deteriorating noise characteristics. For example, the reception band of the GSM communication system It will not meet demands such as noise. By adding the capacitor 303, the noise generated in the threshold voltage compensation gate bias circuit unit 302 is cut off by the filter effect of the capacitor and the resistance, and the noise characteristic is improved in any state of the continuously changing variable attenuation circuit. Can do.

  As described above, by adding the threshold voltage compensation gate bias circuit section 302, the capacitor 303, and the back gate additional high resistance 325 to the variable attenuation circuit having the attenuation control MOSFET 311, a signal caused by variations in the manufacturing process and temperature variation is obtained. It is possible to correct the threshold variation of the attenuating MOSFET 311 and to eliminate signal leakage in the signal attenuating MOSFET 311 in any attenuation state, thereby improving the linearity. Furthermore, noise generated in the threshold voltage compensation gate bias circuit unit 302 can be reduced, and noise characteristics can be improved. As a result, a variable attenuation circuit compatible with the multi-band multi-communication system can be realized by the Si process, and can be made into one chip with other radio circuit blocks.

  Note that the gate bias circuit unit 302, the capacitor 303, and the back gate additional high resistance 325 may be connected to one or only two of them. The MOSFET may be a P-channel MOSFET. Further, it is sufficient that the same effect can be exhibited even if the triple well structure is not used.

(Third embodiment)
The third embodiment of the present invention is a variable attenuation circuit (integrated circuit) corresponding to the first, second, third, fourth, and fifth points of the problem. Hereinafter, a description will be given with reference to FIG.

  The variable attenuation circuit according to the third embodiment of the present invention shown in FIG. 4 is an attenuation circuit that attenuates a high-frequency signal input from the signal input terminal 404 and outputs the attenuated signal from the signal output terminal 405. The attenuation amount is an external terminal. A variable attenuation circuit that can be controlled from 406 is assumed. Further, it is assumed that this variable attenuation circuit is manufactured on, for example, a Si semiconductor substrate.

  Specifically, the variable attenuation circuit according to the present invention includes a signal attenuation unit 400 including a signal attenuation MOSFET (signal attenuation element) 411 inserted in series between the signal input terminal 404 and the signal output terminal 405, The signal attenuation MOSFET 411 includes an attenuation amount control circuit unit 401 that controls the ON resistance, and a source bias circuit unit 402 that applies a bias to the source of the signal attenuation MOSFET 411. The signal attenuation MOSFET 411 includes an attenuation amount control circuit unit 401. The high frequency signal is attenuated by an attenuation amount corresponding to the attenuation amount control signal generated in step (1).

  In the variable attenuation circuit, a capacitor 403 is added between the gate of the signal attenuation MOSFET 411 and the ground terminal. The effect of this capacitor 403 has two major points. The first point is to prevent noise components generated in the attenuation control circuit unit 401 from being mixed into a high-frequency signal line (a line extending from the signal input terminal 404 to the signal output terminal 405) via the gate of the signal attenuation MOSFET 411. It is. The second point is that the high-frequency signal is prevented from leaking between the signal input terminal 404 and the signal output terminal 405 in a high attenuation state due to the influence of the parasitic capacitance generated between the drain and gate of the signal attenuation MOSFET 411 and between the gate and source. That is.

  Further, the source bias circuit unit 402 of this variable attenuation circuit generates a bias voltage by using a source bias generation MOSFET 417 having the same threshold voltage fluctuation (temperature characteristic) as the signal attenuation MOSFET 411, thereby reducing the signal attenuation. This has the effect of correcting variations in threshold voltage due to the manufacturing process and temperature of the MOSFET 411.

  In addition, the well of the signal attenuation MOSFET 411 of this variable attenuation circuit has a triple well structure, and a high resistance 424 is added between the back gate portion and the substrate. The effect of the high resistance 424 is to prevent signals from leaking to the substrate via the back gate.

  Further, in this variable attenuation circuit, a capacitor 425 and a switch 426 are added between a connection portion of a resistor 422 that supplies a source bias to the signal attenuation MOSFET 411 and a resistor 423 that supplies a drain bias and a ground terminal. The effect of the capacitor 425 and the switch 426 is that a high frequency signal is input to the signal input terminal in a high attenuation state via a resistor inserted between the drain and source of the signal attenuation MOSFET 411 to supply the source bias and the drain bias. This is to prevent leakage from 404 to the signal output terminal 405. Dividing the resistor and grounding at high frequency prevents signal leakage. A switch is inserted to eliminate signal leakage in the low attenuation state through which the signal passes so that the capacitance is not visible in the low attenuation state.

  Here, a method of controlling the switch 426 will be described. When the voltage Vc at the gain control terminal 406 is low, the switch 426 is turned on, and when the voltage Vc is high, the switch 426 is turned off. Since the voltage Vc changes continuously, the switch 426 does not accurately turn on or off, but gradually changes from the on state to the off state (continuous on / off operation). The switch 426 is an analog switch, mainly a MOSFET.

  As a control circuit for the switch (MOSFET) 426, for example, by fixing the gate potential of the MOSFET and connecting the source / drain terminal of the MOSFET to the gain control terminal 426 through a resistor, Performs on / off operation.

  The circuit connection of the variable attenuation circuit will be specifically described below.

  First, as the signal attenuating element, for example, an N-channel MOSFET having a triple well structure is suitable. The signal attenuating MOSFET 411 is inserted in series in the signal path between the signal input terminal 404 and the signal output terminal 405 of the high frequency variable attenuating circuit, and the DC between the signal input terminal 404 and the signal attenuating MOSFET 411 is a DC. A DC blocking capacitor 412 that blocks components and passes only high-frequency components is inserted, and a DC blocking capacitor 413 is also inserted between the signal attenuation MOSFET 411 and the signal output terminal 405. A high resistance 424 for blocking signal leakage is inserted between the back gate portion of the signal attenuating MOSFET 411 and the substrate.

  Next, an attenuation control circuit unit 401 is connected to the gate of the signal attenuation MOSFET 411. The configuration of the attenuation control circuit unit 401 will be described. The attenuation control resistor 415 and the attenuation control resistor 416 are connected in series, the other terminal of the resistor 415 is connected to the gain control terminal (Vc) 406, and the other terminal of the resistor 416 is connected to the ground terminal. It is connected. A resistor 414 having a high resistance value that blocks high frequency and passes only DC is connected between a connection portion between the resistor 415 and the resistor 416 and the gate of the signal attenuation MOSFET 411. Further, a capacitor 403 is added between the gate of the signal attenuation MOSFET 411 and the ground terminal.

  The source bias circuit unit 402 connected to the source terminal of the signal attenuation MOSFET 411 will be described. The resistor 420 and the resistor 421 are connected in series, the other terminal of the resistor 420 is connected to the power supply voltage terminal (Vdd) 407, and the other terminal of the resistor 421 is connected to the ground terminal. A gate of a source bias generation MOSFET 417 is connected to a connection portion between the resistor 420 and the resistor 421, and the source bias generation MOSFET 417 has the same manufacturing process and temperature variation variation as the signal attenuation MOSFET 411. A resistor 418 is connected between the drain of the source bias generating MOSFET 417 and the power supply voltage terminal 407, and a resistor 419 is connected between the source of the source bias generating MOSFET 417 and the ground terminal. Also, a resistor 422 having a high resistance value that cuts off the high frequency and passes only DC is connected between the source of the source bias generating MOSFET 417 and the source of the signal attenuating MOSFET 411, and the signal attenuating with the source of the source bias generating MOSFET 417. A resistor 423 having a high resistance value that cuts off the high frequency and passes only DC is connected between the drain of the MOSFET 411 for use. A capacitor 425 and a switch 426 are added between the connection portion of the resistor 422 that supplies the source bias to the signal attenuating MOSFET 411 and the resistor 423 that supplies the drain bias and the ground terminal.

  FIG. 10 is a diagram showing the variation of each voltage value with respect to the temperature of the variable attenuation circuit when the source bias circuit unit 402 as shown in FIG. 1 is used, and FIG. 11 shows the gain characteristic with respect to the control voltage at that time. FIG. In FIG. 10, unlike FIG. 8, the configuration is such that Vref decreases as the temperature rises. As a result, Vg−Vref−Vth is always constant regardless of temperature fluctuations even when the temperature increases and the threshold voltage Vth increases, or when the temperature decreases and the threshold voltage Vth decreases. It is possible to draw the same control characteristics as shown in FIG.

  The circuit operation for realizing the variation correction as shown in FIG. 11 will be described using the variable attenuation circuit of FIG. The gate potential of the source bias generation MOSFET 417 of the source bias circuit section 402 in FIG. Like the signal attenuation MOSFET 411, the source bias generation MOSFET 417 has a characteristic that the threshold voltage increases as the temperature rises. Therefore, the threshold voltage increases as the temperature rises, while the gate potential is constant. Therefore, the source potential decreases and the current flowing through the source bias generation MOSFET 417 decreases. As a result, the source bias potential of the signal attenuating MOSFET 411 is reduced, and correction of the threshold voltage fluctuation can be realized.

  Next, a circuit operation for realizing a linear control characteristic will be described using the variable attenuation circuit of FIG. A continuous control voltage from 0 V to the power supply voltage potential is input to the control terminal (Vc) 406 of the attenuation control circuit unit 401 in FIG. This control voltage is divided by the resistors 415 and 416 and input to the gate of the signal attenuation MOSFET 411. The signal attenuating MOSFET 411 is used with a drain-source bias of 0 V. When the gate potential is 0 V, the ON resistance is the largest. As the gate potential increases, the ON resistance gradually decreases, and the gate potential becomes the power supply voltage. Then, the ON resistance is minimized. As the ON resistance changes, the attenuation of the pass characteristic from the signal input terminal 404 to the signal output terminal 405 also varies. Further, by dividing the voltage with the resistor 415 and the resistor 416, an arbitrary control characteristic can be realized.

  However, when a variable attenuation circuit is realized with a Si substrate, for example, a signal leaks due to the parasitic capacitance generated between the drain and gate of the signal attenuating MOSFET 411 and between the gate and the source, and the ON resistance of the signal attenuating MOSFET 411 The determined amount of attenuation cannot be obtained, and linearity cannot be ensured. In order to eliminate the influence, the capacitor 403 is inserted between the gate of the signal attenuation MOSFET 411 and the ground. By inserting the capacitor 403, the signal leakage path between the drain and gate of the signal attenuating MOSFET 411 and between the gate and source is cut off to ensure linearity.

  In the same way as described above, for example, when the variable attenuation circuit is realized with a Si substrate, the impedance between the back gate and the substrate of the signal attenuation MOSFET 411 is low due to the low substrate resistance. Leakage, the amount of attenuation determined by the ON resistance of the signal attenuation MOSFET 411 cannot be obtained, and linearity cannot be ensured. In order to eliminate the influence, for example, the MOSFET 411 is manufactured in a triple well structure, and a high resistance is inserted between the back gate of the MOSFET 411 and the substrate, thereby blocking a signal leakage path and ensuring linearity.

  For example, when a variable attenuation circuit is realized using a MOSFET on a Si substrate, it is necessary to apply the same potential to the source and drain of the MOSFET 411. At that time, a method is generally used in which the voltage generated by the source bias circuit 402 is supplied to the source via the high resistance 422 and supplied to the drain via the high resistance 423. However, in that case, in a high attenuation state, there is a problem that a signal leaks from the drain to the source via the resistor, and the attenuation amount cannot be as much as the attenuation characteristic when the MOSFET 411 is cut off. In order to eliminate the influence, for example, the capacitor 425 and the switch 426 are inserted between the connection portion of the source bias resistor 422 and the drain bias resistor 423 of the MOSFET 411 and the ground terminal, and the switch 426 is turned on in the high isolation state. Thus, a path through which a signal leaks from the input terminal to the output terminal via the source bias resistor and the drain bias resistor can be cut off, and the attenuation characteristic at the time of high isolation can be improved. Further, in the passing state, the switch 426 is turned OFF to prevent the signal from leaking when passing due to the influence of the capacitor 425.

  FIG. 14A shows a result of circuit simulation actually using the variable attenuation circuit of FIGS. 4 and 2. There is no difference in the level at the maximum output (Vc = 1.8V) between the conventional circuit and the circuit according to the present invention. However, when Vc = 1.5V or less, the signal leakage is large in the conventional circuit and the attenuation is sufficiently obtained. In contrast, in the circuit of the present invention to which the third embodiment is applied, the original performance of the MOSFET 411 is obtained by adding the gate capacitor 403, the back gate added high resistance 424, the capacitor 425 added to the source bias circuit, and the switch 426. A damping amount close to is obtained, and the damping control characteristic is greatly improved.

  In addition, the variable attenuation circuit has improved noise characteristics due to the addition of the capacitor 403. The attenuation amount control circuit unit 401 is usually composed of a resistor. Therefore, noise generated by this resistor is mixed through the gate of the signal attenuating MOSFET 411 and is applied to the high-frequency signal that has entered from the signal input terminal 404, thereby deteriorating noise characteristics. For example, GSM communication system reception band noise, etc. The requirement is not met.

  However, by adding the capacitor 403, the noise generated in the attenuation control circuit unit 401 is cut off by the filter effect of the capacitor 403 and the resistor 414, and the noise characteristic is improved in any state of the continuously changing variable attenuation circuit. Can do. FIG. 14B shows the result of circuit simulation using the variable attenuation circuit of FIGS. 4 and 2 in practice. In the third embodiment, the noise characteristics are greatly improved by adding the capacitor 403.

  As described above, by adding the source bias circuit unit 402, the capacitor 403, the back gate additional high resistance 424, the source bias additional capacitor 425 + the switch 426 to the variable attenuation circuit having the signal attenuation MOSFET 411, the manufacturing process and temperature variation It is possible to correct the threshold variation of the signal attenuation MOSFET 411 due to the variation, and it is possible to eliminate the signal leakage of the signal attenuation MOSFET 411 and other resistors in any attenuation state, thereby improving the linearity. . Furthermore, noise generated in the attenuation control circuit unit 401 can be reduced, and noise characteristics can be improved. As a result, a variable attenuation circuit compatible with the multi-band multi-communication system can be realized by the Si process, and can be made into one chip with other radio circuit blocks.

  Note that only one of the source bias circuit unit 402, the capacitor 403, the back gate additional high resistance 424, the source bias circuit additional capacitor 425 and the switch 426, or only two, or only three, Alternatively, a configuration in which all are connected may be used. The MOSFET may be a P-channel MOSFET. Further, it is sufficient that the same effect can be exhibited even if the triple well structure is not used. Further, instead of the series circuit of the source bias circuit additional capacitor 425 and the switch 425, only the source bias circuit additional capacitor 425 may be provided.

(Fourth embodiment)
Hereinafter, a variable attenuation circuit (integrated circuit) according to a fourth embodiment of the present invention will be described with reference to FIG.

  6 is a variable attenuation circuit using at least one of the variable attenuation circuit of FIG. 1, the variable attenuation circuit of FIG. 3, or the variable attenuation circuit of FIG. The circuit configuration and operation principle will be described.

  In general, a variable attenuation circuit using GaAs or the like is often produced independently on a substrate. In that case, both input and output must be terminated at 50Ω at a high frequency, and the variable attenuation circuit is configured as shown in FIG. . In FIG. 16, reference numerals 1601 to 1604 denote variable resistors (variable attenuation circuits). Vc is an attenuation control terminal, Vref1 to Vref4 are bias terminals, IN is an input terminal, and OUT is an output terminal. In this circuit configuration, a variable resistance portion inserted in parallel (shunt) is terminated at 50 Ω for both input and output from a high attenuation state to a low attenuation state. However, when manufacturing on a Si substrate, it is not always necessary to terminate both input and output. For example, when the input side is a digital circuit such as an inverter, the input impedance of the variable attenuation circuit is low, and inserting a first-stage parallel variable resistor has no effect. Also, by inserting a variable resistor in the first stage, the input impedance of the variable attenuation circuit is lowered, and a large driving force is required for the previous circuit. In such a case, a ladder-type variable attenuation circuit as shown in FIG. 5 is desirable. In FIG. 5, 501 and 502 are variable attenuation circuits as shown in FIG. 1 or FIG. 4, 503 and 504 are variable attenuation circuits as shown in FIG. 3, 505 is a signal input terminal, 506 is a signal output terminal, 507 Is a gain control terminal.

  By inserting the variable resistor inserted in the first stage into the middle stage, the effect of inserting the resistor is produced, the attenuation characteristic is improved, and the input impedance of the variable attenuation circuit can be constantly increased, so that the previous stage circuit is driven. The force can be reduced, and the consumption can be reduced.

  FIG. 6 shows a variable attenuation circuit using the variable attenuation circuit of FIGS. 4 and 3 in the circuit configuration of FIG. In FIG. 6, the high-frequency signal that has entered from the signal input terminal 601 is attenuated by the attenuation operation units 611, 612, 613, and 614 and is output from the signal output terminal 602. The attenuation operation units 611, 612, 613, and 614 here are a collection of the signal attenuation unit and the attenuation amount control unit in FIG. 4 or FIG. 3.

  The attenuation is continuously controlled from the high attenuation state to the low attenuation state by the attenuation amount control terminal (Vc) 603. In this variable attenuation circuit, a common source bias generation circuit 615 shown in FIG. 4 is added as a threshold voltage variation correction circuit for the signal attenuating MOSFETs of the attenuation operation unit 611 and the attenuation operation unit 613, and the attenuation operation unit 612. The gate bias generation circuit 616 shown in FIG. 3 is added as a variation correction circuit for the threshold voltage of the signal attenuating MOSFET, and the threshold voltage variation correction circuit for the signal attenuating MOSFET of the attenuation operation unit 614 is added as shown in FIG. The gate bias generation circuit 617 shown in FIG. Further, in order to ensure linearity and improve noise characteristics, a capacitance is added between the gate and ground terminal of each signal attenuating MOSFET. Each MOSFET has a triple well structure, and a high resistance is inserted between the back gate and the substrate in order to reduce signal leakage to the substrate. A capacitor and a switch are inserted between the connection portion of the source bias resistor and the drain bias resistor of the signal attenuating MOSFETs of the attenuation operation unit 611 and the attenuation operation unit 613 and the ground.

  Here, a series circuit of a capacitor and a MOSFET constituting the attenuating operation units 12 and 14 plays the role of the capacitance and the switch.

  15A and 15B show the results of circuit simulation using the variable attenuation circuit shown in FIG. FIG. 15A shows the control characteristics, and FIG. 15B shows the noise characteristics. The linearity is greatly improved by adding a capacitor and a switch added to the gate capacitance, back gate added high resistance, source bias circuit, and serial signal attenuator and parallel signal attenuator are connected in two stages alternately. Thus, the control characteristics as shown in FIG. 15A were realized, and a variable attenuation range of 50 dB or more was realized in both the 800 MHz band and the 2 GHz band. In addition, it can be seen from FIG. 15B that the noise characteristics are greatly improved. As a result, a variable attenuation circuit having excellent variation characteristics, linearity, and noise characteristics can be manufactured.

  In the variable attenuation circuit of FIG. 6, at least one of the capacitors added between the gate and the ground terminal of each signal attenuation MOSFET, or at least one of the high resistances between the back gate and the substrate, or It is sufficient that at least one of the threshold voltage variation correction circuits of the signal attenuating MOSFET or at least one of the source bias and drain bias additional capacitors is added, and all of them need not be connected. Further, the connection between the parallel (shunt) signal attenuating unit and the series signal attenuating unit may not be in this order, and the number of stages may be any number. The MOSFET may be a P-channel MOSFET. Further, it is sufficient that the same effect can be exhibited even if the triple well structure is not used.

(Fifth embodiment)
Hereinafter, an integrated circuit according to a fifth embodiment of the present invention will be described with reference to FIG.

  FIG. 7 is a block diagram showing an example of a high-frequency wireless transmission circuit system (apparatus) using the variable attenuation circuit of FIG. 1, FIG. 3, FIG. 4, or FIG. The circuit configuration and operation principle will be described.

  As shown in FIG. 7, the high-frequency radio transmission circuit system divides the oscillation signal of an oscillator (VCO) 701 by a divider 702 and passes through a buffer 703 constituted by an inverter or the like. Thereafter, the gain is controlled by a variable attenuation circuit (Variable Attenuator) 704 to be attenuated, amplified by a driver amplifier (Driver) 705, further amplified by a high frequency amplifier (PA) 706, and transmitted from an antenna 707.

  By applying the present invention to the variable attenuation circuit 704 of the high-frequency wireless transmission circuit system of FIG. 7, even when the variable attenuation circuit is constructed on the same Si semiconductor substrate as other circuit blocks, variation characteristics and linearity are achieved. Therefore, a variable attenuation circuit excellent in isolation characteristics and noise characteristics can be realized, and a system having good pass characteristics can be obtained.

  Note that the configuration example of the high-frequency wireless transmission circuit system is not limited to the above, and is connected to the wireless transmission device including at least one variable attenuation circuit, at least one oscillator, and at least one amplifier, and at least connected to the wireless transmission device. Any radio transmission circuit system including an antenna capable of transmitting and receiving one radio frequency may be used.

  According to this embodiment, the same effect as that of the above embodiment can be obtained.

  The present invention is useful for use in attenuation of high-frequency signals in various wireless communication devices.

It is a circuit diagram which shows one circuit structure of the variable attenuation circuit in the 1st Embodiment of this invention. It is a circuit diagram which shows the prior art example of the variable attenuation circuit produced using the GaAs process. It is a circuit diagram which shows one circuit structure of the variable attenuation circuit in the 2nd Embodiment of this invention. It is a circuit diagram which shows one circuit structure of the variable attenuation circuit in the 3rd Embodiment of this invention. It is a block diagram which shows one circuit structure of the variable attenuation circuit in the 4th Embodiment of this invention. It is a circuit diagram which shows one circuit structure of the variable attenuation circuit in the 4th Embodiment of this invention. It is a block diagram which shows an example of the high frequency wireless transmission circuit system to which this invention is applied. FIG. 3 is a schematic diagram showing fluctuation of each bias value of a MOSFET with respect to temperature in the conventional variable attenuation circuit as shown in FIG. 2. In the conventional variable attenuation circuit like FIG. 2, it is the schematic diagram showing the attenuation amount of the variable attenuation circuit with respect to the control voltage. FIG. 5 is a schematic diagram showing fluctuation of each bias value of a MOSFET with respect to temperature in the variable attenuation circuit of FIGS. 1 and 4 in the first and third embodiments of the present invention. FIG. 5 is a schematic diagram showing the attenuation amount of the variable attenuation circuit with respect to the control voltage in the variable attenuation circuit of FIGS. 1 and 4 in the first and third embodiments of the present invention. FIG. 6 is a schematic diagram showing fluctuations of each bias value of a MOSFET with respect to temperature in the variable attenuation circuit of FIG. 3 in the second embodiment of the present invention. FIG. 6 is a schematic diagram showing the attenuation amount of the variable attenuation circuit with respect to the control voltage in the variable attenuation circuit of FIG. 3 in the second embodiment of the present invention. It is a figure which shows the simulation result of the attenuation amount with respect to a control voltage in the variable attenuation circuit of FIG. 4 in the 3rd Embodiment of this invention, and the conventional variable attenuation circuit. It is a figure which shows the simulation result of the noise characteristic with respect to a control voltage in the variable attenuation circuit of FIG. 4 in the 3rd Embodiment of this invention, and the conventional variable attenuation circuit. It is a figure which shows the simulation result of the attenuation amount with respect to a control voltage in the variable attenuation circuit of FIG. 6 in the 4th Embodiment of this invention, and the conventional variable attenuation circuit. It is a figure which shows the simulation result of the noise characteristic with respect to a control voltage in the variable attenuation circuit of FIG. 6 in the 4th Embodiment of this invention, and the conventional variable attenuation circuit. It is a block diagram which shows one circuit structure of the conventional variable attenuation circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Signal attenuation part 101 Attenuation amount control part 102 Source bias circuit part with threshold bias correction function 103 Gate additional capacity 104 Signal input terminal 105 Signal output terminal 106 Attenuation (gain) control terminal 107 Power supply voltage terminal 111 Signal attenuation MOSFET
112, 113 DC blocking capacitance 114 Gate bias supply resistor 115, 116 Attenuation control resistor 117 Source bias generation MOSFET
118, 119, 120, 121 Source bias generation resistor 122 Source bias generation resistor 123 Drain bias generation resistor 124 Back gate additional high resistance 231 Signal input terminal 232 Signal output terminal 233 Attenuation (gain) control terminal 234 Source bias supply Terminal 235 Gate bias supply terminal 236, 237 Ground terminal 238, 242 DC blocking capacitor 239 Source bias supply resistor 240 Signal attenuation FET
241 Drain bias supply resistor 243, 248, 249, 254 DC blocking capacitor 244, 247, 250, 253 Input / output matching resistor 245, 251 Shunt side signal attenuating FET
246, 252 Source potential supply resistor 255, 257, 258 Gate bias supply resistor 256, 259 Drain bias supply resistor 260 Signal attenuation unit 261, 262 Shunt side signal attenuation unit 300 Shunt side signal attenuation unit 301 Attenuation amount control unit 302 Gate bias circuit section with threshold bias correction function 303 Additional gate capacitance 304 Signal input terminal 305 Signal output terminal 306 Gain control terminal 307 Power supply voltage terminal 311 Signal attenuation MOSFET
312 and 313 DC blocking capacitance 314 Impedance adjustment resistor 315 and 316 DC blocking capacitance 317 Drain bias supply resistor 318 Gate bias generation MOSFET
319, 320, 321, 322 Gate bias generation resistor 323 Gate bias generation resistor 324 Source bias generation resistor 325 Back gate additional high resistance 400 Signal attenuation unit 401 Attenuation amount control unit 402 Source bias circuit with threshold bias correction function Section 403 Additional gate capacitance 404 Signal input terminal 405 Signal output terminal 406 Attenuation (gain) control terminal 407 Power supply voltage terminal 411 Signal attenuation MOSFET
412 413 DC blocking capacitance 414 Gate bias supply resistor 415 416 Attenuation amount control resistor 417 Source bias generation MOSFET
418, 419, 420, 421 Source bias generating resistor 422 Source bias generating resistor 423 Drain bias generating resistor 424 Back gate additional high resistance 425 Source bias additional capacitance 426 Source bias additional switch 501 502 The variable as shown in FIG. Attenuation circuits 503 and 504 Variable attenuation circuits as shown in FIG. 3 505 Signal input terminal 506 Signal output terminal 507 Gain control terminal 601 Signal input terminal 602 Signal output terminal 603 Gain control terminals 611 and 613 Variable attenuation circuit 612 and FIG. 614 Variable attenuation circuit shown in FIG. 3 615 Source bias generation circuit shown in FIG. 4 616, 617 Gate bias generation circuit shown in FIG. 3 701 Oscillator (VCO)
702 Divider
703 Buffer
704 Variable Attenuator
705 Driver Amplifier
706 High frequency amplifier (PA)
707 Antenna 1601, 1602 Variable attenuating unit 1603 shown in FIG. 2 1603 Variable attenuating unit 1603 shown in FIG. 2 1604 Variable attenuating unit shown in 262 of FIG.

Claims (18)

A signal attenuating unit having a signal attenuating element inserted in series in a signal path between the signal input unit and the signal output unit;
An attenuation control circuit unit for supplying an attenuation control signal to the signal attenuation element;
A bias circuit section for applying a bias to the signal attenuating element;
A variable attenuation circuit including a capacitor connected between a connection portion between the signal attenuation element and the attenuation amount control circuit portion and a ground terminal.   The signal attenuating element is an FET, the attenuation control circuit unit applies an attenuation control signal to the gate terminal of the FET to control the ON resistance of the FET, and the bias circuit unit is connected to the source terminal of the FET. 2. The variable attenuation circuit according to claim 1, wherein a bias is applied, and the capacitor is connected between a gate terminal of the FET and the ground terminal. A signal attenuating unit having a signal attenuating FET inserted in series in a signal path between the signal input unit and the signal output unit;
An attenuation amount control circuit unit that applies an attenuation amount control signal to the gate terminal of the signal attenuation FET to control the ON resistance of the signal attenuation FET;
A bias circuit section for applying a bias to the source terminal of the signal attenuation FET;
The bias circuit section is a variable attenuation circuit having a bias FET that compensates for variations in threshold voltage of the signal attenuation FET. A signal attenuating unit having a signal attenuating FET inserted in series in a signal path between the signal input unit and the signal output unit;
An attenuation amount control circuit unit that applies an attenuation amount control signal to the gate terminal of the signal attenuation FET to control the ON resistance of the signal attenuation FET;
A bias circuit section for applying a bias to the source terminal of the signal attenuation FET;
A variable attenuation circuit comprising a back gate portion of the signal attenuation FET and a resistor connected between the substrates. A signal attenuating unit having a signal attenuating FET inserted in series in a signal path between the signal input unit and the signal output unit;
An attenuation amount control circuit unit that applies an attenuation amount control signal to the gate terminal of the signal attenuation FET to control the ON resistance of the signal attenuation FET;
A bias circuit section for applying a bias to the source terminal of the signal attenuation FET;
A variable attenuation circuit including a capacitor or a capacitor and a switch connected between the bias circuit section and a ground terminal. A signal attenuation that is output by controlling the amount of attenuation of the signal applied to the signal input unit by a signal applied to the gate terminal of the FET by inserting and connecting a FET to the signal path between the signal input unit and the signal output unit And
An attenuation amount control circuit unit that applies a signal to the gate terminal to vary the ON resistance value of the FET;
A bias circuit section for connecting a first capacitor element between the other end of the resistor element having one end connected to the source terminal of the FET and a ground terminal, and applying a DC voltage via the resistor element;
A resistor connected between the back gate portion of the FET and the ground terminal;
A variable attenuation circuit, wherein a second capacitor element is connected between the gate terminal and the ground terminal. A signal attenuating unit having a signal attenuating element inserted between the signal path between the signal input unit and the signal output unit and the ground terminal;
An attenuation control circuit unit for supplying an attenuation control signal to the signal attenuation element;
A bias circuit section for applying a bias to the signal attenuating element;
A variable attenuation circuit comprising a capacitor connected between a connection portion between the signal attenuating element and the bias circuit portion and the ground terminal.   The signal attenuating element is an FET, the attenuation control circuit unit applies an attenuation control signal to the drain terminal of the FET to control the ON resistance of the FET, and the bias circuit unit is connected to the gate terminal of the FET. 8. The variable attenuation circuit according to claim 7, wherein a bias is applied, and the capacitor is connected between a gate terminal of the FET and the ground terminal. A signal attenuation unit having a signal attenuation FET inserted between the signal path between the signal input unit and the signal output unit and the ground terminal;
An attenuation control circuit unit that applies an attenuation control signal to the drain terminal of the signal attenuation FET to control the ON resistance of the signal attenuation FET;
A bias circuit section for applying a bias to the gate terminal of the signal attenuation FET,
The bias circuit section is a variable attenuation circuit having a bias FET that compensates for variations in threshold voltage of the signal attenuation FET. A signal attenuation unit having a signal attenuation FET inserted between the signal path between the signal input unit and the signal output unit and the ground terminal;
An attenuation control circuit unit that applies an attenuation control signal to the drain terminal of the signal attenuation FET to control the ON resistance of the signal attenuation FET;
A bias circuit section for applying a bias to the gate terminal of the signal attenuation FET;
A variable attenuation circuit comprising a back gate portion of the signal attenuation FET and a resistor connected between the substrates. A current path terminal pair of the first capacitor element and the FET is inserted and connected in series between the signal path between the signal input unit and the signal output unit and the AC ground, and the current path of the first capacitor element and the FET is A signal attenuating unit for controlling and outputting the attenuation amount of the signal given to the signal input unit by a signal given to a connection part with one end;
An attenuation control circuit unit that applies a signal to the one end of the FET to vary the ON resistance value of the FET;
A bias circuit section for applying a DC voltage to the gate terminal of the FET via a resistance element;
A resistor connected between the back gate portion of the FET and the ground terminal;
A variable attenuation circuit, wherein a second capacitor element is connected between the gate terminal and the ground terminal. A first signal attenuating unit having a first signal attenuating element inserted in series in a signal path between the signal input unit and the signal output unit;
A first attenuation control circuit unit for supplying an attenuation control signal to the first signal attenuating element;
A first bias circuit section for applying a bias to the first signal attenuating element;
A first capacitor connected between a connection portion between the first signal attenuating element and the first attenuation control circuit portion and a ground terminal;
A second signal attenuating unit having a second signal attenuating element inserted between a signal path between the signal input unit and the signal output unit and a ground terminal;
A second attenuation control circuit unit for supplying the attenuation control signal to the second signal attenuation element;
A second bias circuit section for applying a bias to the second signal attenuating element;
A variable attenuation circuit including a second capacitor connected between a connection portion between the second signal attenuating element and the second bias circuit portion and the ground terminal. The first signal attenuating element is a first FET, and the first attenuation control circuit unit applies an attenuation control signal to the gate terminal of the first FET to turn on the ON resistance of the first FET. The first bias circuit unit applies a bias to the source terminal of the first FET, the first capacitor is connected between the gate terminal of the first FET and the ground terminal;
The second signal attenuating element is a second FET, and the second attenuation control circuit unit provides an attenuation control signal to the drain terminal of the second FET to turn on the ON resistance of the second FET. The second bias circuit unit applies a bias to the gate terminal of the second FET, and the second capacitor is connected between the gate terminal of the second FET and the ground terminal. The variable attenuation circuit according to claim 12. A first signal attenuating unit having a first signal attenuating FET inserted in series in a signal path between the signal input unit and the signal output unit;
A first attenuation control circuit unit that applies an attenuation control signal to the gate terminal of the first signal attenuation FET to control the ON resistance of the first signal attenuation FET;
A first bias circuit section for applying a bias to a source terminal of the first signal attenuating FET;
A second signal attenuating unit having a second signal attenuating FET inserted between a signal path between the signal input unit and the signal output unit and a ground terminal;
A second attenuation control circuit unit that applies an attenuation control signal to the drain terminal of the second signal attenuation FET to control the ON resistance of the second signal attenuation FET;
A second bias circuit section for applying a bias to the gate terminal of the second signal attenuating FET,
The first bias circuit section includes a first bias FET that compensates for variations in threshold voltage of the first signal attenuating FET,
The second bias circuit unit is a variable attenuation circuit having a second bias FET that compensates for variations in threshold voltage of the second signal attenuation FET. A first signal attenuating unit having a first signal attenuating FET inserted in series in a signal path between the signal input unit and the signal output unit;
A first attenuation control circuit unit that applies an attenuation control signal to the gate terminal of the first signal attenuation FET to control the ON resistance of the first signal attenuation FET;
A first bias circuit section for applying a bias to a source terminal of the first signal attenuating FET;
A second signal attenuating unit having a second signal attenuating FET inserted between a signal path between the signal input unit and the signal output unit and a ground terminal;
A second attenuation control circuit unit that applies an attenuation control signal to the drain terminal of the second signal attenuation FET to control the ON resistance of the second signal attenuation FET;
A second bias circuit section for applying a bias to the gate terminal of the second signal attenuating FET;
A first resistor connected between the back gate portion of the first signal attenuating FET and the substrate;
A variable attenuation circuit comprising a back gate portion of the second signal attenuation FET and a second resistor connected between the substrates. A first signal attenuating unit having a first signal attenuating FET inserted in series in a signal path between the signal input unit and the signal output unit;
A first attenuation control circuit unit that applies an attenuation control signal to the gate terminal of the first signal attenuation FET to control the ON resistance of the first signal attenuation FET;
A first bias circuit section for applying a bias to a source terminal of the first signal attenuating FET;
A second signal attenuating unit having a second signal attenuating FET inserted between a signal path between the signal input unit and the signal output unit and a ground terminal;
A second attenuation control circuit unit that applies an attenuation control signal to the drain terminal of the second signal attenuation FET to control the ON resistance of the second signal attenuation FET;
A second bias circuit section for applying a bias to the gate terminal of the second signal attenuating FET;
A variable attenuation circuit comprising a capacitor or a capacitor and a switch connected between the first bias circuit section and a ground terminal. A first resistor is connected between the back gate portion of the first signal attenuating FET and the ground terminal;
17. The variable attenuation circuit according to claim 16, wherein a second resistor is connected between the back gate portion of the second signal attenuating FET and the ground terminal.   A wireless transmission device comprising at least one variable attenuation circuit according to any one of claims 1 to 17, at least one high-frequency amplifier circuit, and at least one oscillator, and connected to the wireless transmission device And a high frequency radio circuit system including an antenna for transmitting radio frequency.

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