JP2008060258A - Plasma processing apparatus and plasma processing method - Google Patents

Abstract

Uniform plasma treatment can be performed even on a large-diameter wafer, and reaction products can be prevented from adhering to the inner wall surface of a top plate on which an ICP coil is disposed, thereby preventing generation of particles. A plasma processing apparatus and a plasma processing method are provided.
A plurality of coils 31, 32, 33 constituting an ICP coil are disposed on a top plate 30 of a chamber 11 provided at a position facing a processing surface of a wafer 21. Between the plurality of coils 31, 32, 33, spaces 37, 38, 39 for reducing mutual interference of electromagnetic fields generated by the coils between adjacent coils are provided. On the outer wall of the top plate 30 corresponding to the spaces 37, 38, and 39, Faraday shield electrodes 14, 15, and 16 that are capacitively coupled to the plasma in the chamber 11 via the top plate 30 are disposed.
[Selection] Figure 1

Description

  The present invention relates to a plasma processing apparatus and a plasma processing method, and more particularly to a plasma processing apparatus and a plasma processing method suitable for fine processing on a nonvolatile material film.

2. Description of the Related Art In recent years, semiconductor integrated circuits equipped with non-volatile memories such as RRAM (Resistance Random Access Memory) and MRAM (Magnetoresistive Random Access Memory) as semiconductor integrated circuit devices become highly integrated, highly functional, and increase in operation speed. A device has been proposed. Platinum (Pt), iridium (Ir), lead zirconate titanate (PZT), or the like is used as the electrode material of the capacitor constituting the nonvolatile memory. For the fine pattern formation, a plasma dry etching technique mainly using chlorine or hydrogen bromide as a halogen gas is used. However, it is very difficult to dry-etch Pt and Ir among these electrode material films. The cause is that, as shown in Table 1 below, the boiling point of the reaction product generated during these dry etchings is remarkably high and it is difficult to gasify (vaporize). That is, while the boiling point of SiCl ₄ which is a reaction product when etching polysilicon or the like is about 58 ° C., the boiling points of PtCl ₂ and PtCl ₄ which are reaction products when etching platinum are respectively 581 ° C and 370 ° C. The boiling point of IrCl ₃ , which is a reaction product when iridium is etched, is 763 ° C. Since these high boiling point reaction products easily solidify when they reach the inner wall of the chamber, they remain without being exhausted from the inside of the chamber during etching and become a generation source of particles.

  For dry etching of the electrode material film as described above, an inductively coupled plasma etching apparatus equipped with a single spiral coil is used. This type of plasma processing apparatus has a sample stage on which a wafer to be processed is placed inside a chamber configured to be depressurized. The upper top plate constituting the chamber wall surface at a position facing the sample table is made of an insulator (dielectric material) such as quartz or ceramic. A spiral inductive coupling coil (hereinafter referred to as an ICP coil) that generates plasma in the chamber by inductive coupling is disposed on the upper top plate.

  In the plasma etching apparatus, a reaction product generated during the etching process and attached to the inner wall of the chamber becomes a particle generation source. In particular, the particles generated from the reaction product adhering to the upper top plate often drop on the wafer and cause pattern formation defects or the like in subsequent processes, which is a serious problem.

  In view of this, a dry etching apparatus in which a Faraday shield electrode is installed between the upper top plate and the ICP coil has been proposed in order to prevent the reaction product from adhering particularly to the upper top plate (for example, Patent Document 1). reference.). In the dry etching apparatus, a DC component or a high frequency power is applied to the Faraday shield electrode to cause ions in plasma to enter the upper top plate using a capacitive coupling component generated immediately below the upper top plate. The reaction product adhering to is removed during the etching process. At this time, by setting the voltage applied to the Faraday shield electrode to an optimum value, an optimum value of the capacitive coupling component, that is, the sputtering component is secured on the inner wall of the upper top plate directly under the ICP coil. As a result, it is possible to realize a chamber state in which the upper top plate is not etched by the incident ions, and reaction products generated during the etching process do not adhere to the upper top plate, that is, there is no particle generation factor. .

On the other hand, with the recent increase in diameter of wafers, plasma processing apparatuses having a single spiral ICP coil as described above are required to further improve the etching uniformity within the wafer surface. In response to this requirement, Patent Document 2 and Non-Patent Document 1 described below show a technique in which an ICP coil is constituted by a plurality of coils and high frequency power is independently applied to each coil. In this method, each coil is embedded in a groove formed in the upper top plate in order to reduce mutual interference of electromagnetic fields formed by each ICP coil. According to this method, the electric field distribution and the magnetic flux density distribution in the wafer surface are made uniform by adjusting the amount of current flowing through each coil in a situation where mutual interference of electromagnetic fields formed by each ICP coil is suppressed. It is said that it can be made.
JP 2005-535117 A JP 2000-58296 A “2005 Semiconductor Factory / Equipment / Equipment”, Electronic Journal Co., Ltd., October 5, 2004, p.200-202

  However, according to the technique disclosed in Patent Document 2, the processing uniformity within the wafer surface can be improved. However, when an electrode material film such as Pt or Ir is processed, between the ICP coils. There arises a problem that the reaction product adheres to the interfering interference mitigation site. This is because there is no capacitive coupling component due to the ICP coil at the mutual interference mitigation site, and there are no ions incident from the plasma, and the mutual interference mitigation site has a groove structure. This is because it is difficult to remove. As described above, particles generated by separation of the reaction product attached to the upper top plate fall on the wafer and reduce the manufacturing yield of semiconductor devices and the like.

  In addition, with the technique disclosed in Patent Document 1, it is difficult to ensure sufficient uniformity for a large-diameter wafer.

  The present invention has been proposed in view of the above-described conventional circumstances, and is capable of performing uniform plasma processing even on a large-diameter wafer, and the inner wall surface of the upper top plate on which the ICP coil is disposed. An object of the present invention is to provide a plasma processing apparatus and a plasma processing apparatus that can prevent the reaction product from adhering to the surface.

  In order to achieve the above object, the present invention employs the following technical means. That is, the plasma processing apparatus according to the present invention includes a chamber in which a workpiece is disposed and a dielectric wall that transmits electromagnetic waves at a position facing the processing surface of the workpiece. The chamber is connected to a gas introduction part for introducing a process gas and a gas discharge part for exhausting a gas containing an internal process gas. A plurality of coils for generating plasma in the chamber are disposed outside the chamber corresponding to the dielectric walls. Mutual interference reducing means is provided between the plurality of coils. The mutual interference reducing means reduces the mutual interference of electromagnetic fields generated by the coils between adjacent coils. A Faraday shield electrode that is capacitively coupled to the plasma in the chamber is provided through the dielectric wall at a position where the mutual interference reducing means is disposed.

  According to this configuration, there is no generation of particles during the plasma processing, and the plasma processing of the workpiece can be performed with low defects.

  In the above configuration, for example, the coils are accommodated in a plurality of grooves formed in the dielectric wall, and the mutual interference reducing means is continuous with the internal space of the chamber formed between the grooves. It is possible to employ a configuration in which the Faraday shield electrode is provided on the outer wall side of the dielectric wall corresponding to the space. The Faraday shield electrode can be commonly connected to one coil selected from the plurality of coils. Alternatively, the Faraday shield electrode can be connected to different coils.

  On the other hand, in another aspect, the present invention can provide a plasma processing method that can be implemented in the above-described plasma processing apparatus or the like. That is, in the plasma processing method according to the present invention, the plasma processing of the workpiece disposed in the chamber is performed by the plasma generated in the chamber using a plurality of coils disposed at positions facing the processing surface. In the plasma processing method for performing the process, first, a process gas is introduced into the chamber, and high frequency power is applied to the plurality of coils to generate plasma. Then, with the potential applied to the Faraday shield electrode provided at each of the positions where the mutual interference reducing means for reducing the mutual interference of the electromagnetic fields generated by the coils between adjacent coils is applied, the plasma treatment is performed. Done.

  The plasma treatment can be performed, for example, in a state where an independent potential is applied to each of the Faraday shield electrodes. Further, each potential applied to the Faraday shield electrode is, for example, in a state in which products generated during the plasma processing and attached to the inner wall of the chamber corresponding to the position where the mutual interference reducing means are disposed are removed. Set independently.

  According to the present invention, it is possible to prevent the reaction product from adhering to the inner wall side of the dielectric wall facing the workpiece during plasma processing, and to perform uniform plasma processing even on a large-diameter wafer. . Further, since the reaction product can be prevented from adhering, particles are not generated during the etching process. As a result, the workpiece can be processed with a high manufacturing yield, and the manufacturing cost can be reduced.

  Hereinafter, a plasma processing apparatus and a plasma processing method according to embodiments of the present invention will be described with reference to the drawings. In the following, the present invention is embodied as a plasma etching apparatus that performs an etching process on a laminated film of Pt and Ir, which is a difficult-to-etch material (nonvolatile material).

(First embodiment)
FIG. 1 is a schematic configuration diagram showing a plasma etching apparatus (plasma processing apparatus) according to the first embodiment of the present invention. FIG. 2 is a schematic plan view showing the plasma etching apparatus in the present embodiment. A cross-sectional view taken along line AA in FIG. 2 corresponds to FIG.

  As shown in FIG. 1, in the plasma processing apparatus according to this embodiment, a lower electrode 12 that also serves as a sample stage is installed in a chamber 11. A wafer 21 (workpiece) to be processed is placed on the lower electrode 12. The upper top plate 30 (dielectric wall) of the chamber 11 facing the lower electrode 12 is made of a dielectric (insulator) such as quartz or ceramic. A plurality of inductive coupling coils (ICP coils) are arranged above the upper top plate 30, that is, on the outer wall side of the upper top plate 30. In the example of FIG. 1, the ICP coil includes an outermost central ICP coil 31, an intermediate ICP coil 32, and an outermost peripheral ICP coil 33. Each ICP coil 31, 32, 33 is a ring-shaped coil. Further, as shown in FIG. 2, the outer diameter of the outermost ICP coil 31 is smaller than the inner diameter of the intermediate ICP coil 32, and the outer diameter of the intermediate ICP coil 32 is smaller than the inner diameter of the outermost ICP coil 33. It has become. Each ICP coil 31, 32, 33 is arranged concentrically.

  Further, as shown in FIG. 1, the upper top plate 30 of the plasma processing apparatus of the present embodiment includes a groove portion 34 in which the most central ICP coil 31 is disposed, a groove portion 35 in which the intermediate ICP coil 32 is disposed, and an uppermost portion. It has the groove part 36 by which the outer peripheral part ICP coil 33 is arrange | positioned. Each groove 34, 35, 36 is formed so as to protrude into the internal space of the chamber 11, and is located between the center of the groove 34, between the groove 34 and the groove 35, and between the groove 35 and the groove 36. , Spaces 37, 38, 39 that are continuous with the internal space of the chamber 11 are provided. The spaces 37, 38, and 39 are provided concentrically in a plan view, like the ICP coils 31, 32, and 33. Further, as will be described later, the spaces 37, 38, 39 have a function of reducing mutual interference of electromagnetic fields generated by coils housed in grooves adjacent to the respective spaces. In addition, about the space 37, the mutual interference between the conductors which comprise the coil 31 arrange | positioned on both sides of the space 37 is reduced.

  A bias applying high frequency power supply 26 is connected to the lower electrode 12. Further, a high frequency power supply 17 for applying high frequency power via the tuning capacitor 22 is connected to the most central ICP coil 31. Similarly, a high-frequency power source 18 that applies high-frequency power to the intermediate ICP coil 32 via a tuning capacitor 23 is connected. Similarly, a high frequency power supply 19 that applies high frequency power is connected to the outermost peripheral ICP coil 33 via a tuning capacitor 24. Plasma is generated in the chamber 11 immediately below the upper top plate 30 by the inductively coupled component (inductive magnetic field) generated when the high frequency power sources 17, 18, 19 apply high frequency power to the ICP coils 31, 32, 33. The Although not shown, the process gas is introduced into the chamber 11 through a gas introduction pipe connected to the upper portion of the chamber 11. Further, the gas in the chamber 11 is exhausted through an exhaust port 20 connected to the lower portion of the chamber 11. The pressure in the chamber 11 is maintained at a predetermined pressure by adjusting the opening of the exhaust gate valve 13 disposed on the upstream side of the exhaust port 20.

  In the plasma etching apparatus of this embodiment, the Faraday shield electrodes 14, 15, 16 (hereinafter referred to as FS electrodes 14, 15, 16). That is, as shown in FIGS. 1 and 2, the most central FS electrode 14 is provided on the outer wall side of the space 37 with the upper top plate 30 interposed therebetween. An intermediate FS electrode 15 is provided on the outer wall side of the space 38 with the upper top plate 30 interposed therebetween. Further, the outermost peripheral FS electrode 16 is provided on the outer wall side of the space 39 with the upper top plate 30 interposed therebetween. Moreover, as shown in FIG. 2, each FS electrode 14,15,16 is arrange | positioned concentrically in planar view.

  As shown in FIG. 1, in the plasma etching apparatus of the present embodiment, each FS electrode 14, 15, 16 is connected to the most central ICP coil 31 through a conductive tap 25. Therefore, high frequency power is applied to each FS electrode 14, 15, 16 from the high frequency power supply 17 through the most central ICP coil 31. As a result, a DC bias component that is capacitively coupled to the plasma generated in the chamber 11 is applied to each FS electrode 14, 15, 16.

  When performing the etching process in the plasma etching apparatus having the above-described configuration, first, the wafer 21 to be processed is loaded from a loading / unloading port (not shown) provided on the side wall of the chamber 11 and placed on the lower electrode 12. Here, as shown in the structural cross-sectional view of FIG. 3A, the wafer 21 has a titanium nitride (TiN) film 44, Ir on the lower layer film 46 such as a silicon nitride film covering the lower structure from the lower layer. It is assumed that the film 43 and the Pt film 42 are sequentially stacked by a sputtering method or the like. On the Pt film 42, a mask pattern 41 made of a titanium nitride film is formed by a known lithography technique.

  After the wafer 21 is placed in the chamber 11, the wafer 21 is etched. Here, the etching process is performed under the conditions shown in Table 2 below.

That is, first, a process gas composed of a mixed gas of Cl ₂ gas and O ₂ gas whose flow rate is controlled through a gas introduction unit (not shown) is introduced into the chamber 11. Here, the flow rate of Cl ₂ gas is 100 sccm (standard cubic centimeter per minute), and the flow rate of O ₂ gas is 250 sccm. At this time, the pressure in the chamber 11 is maintained at about 2.0 Pa by adjusting the opening of the exhaust gate valve 13. Further, the temperature of the lower electrode 12 is maintained at 450 ° C. by the heater built in the lower electrode 12. Thereby, the temperature of the wafer 21 is also raised to a similar temperature.

  After the pressure inside the chamber 11 is stabilized, high frequency power is applied to the ICP coils 31, 32, 33 by the high frequency power sources 17, 18, 19. Here, high-frequency power having a frequency of 13.56 MHz is applied to the most central ICP coil 31 at 300 W, the intermediate ICP coil 32 at 400 W, and the outermost peripheral ICP coil 33 at 600 W. As a result, plasma of the process gas is generated in the chamber 11. At this time, plasma is also generated in the spaces 37, 38, and 39, which are mutual interference reducing means, adjacent to the grooves 34, 35, and 36 that accommodate the ICP coils 31, 32, and 33, respectively. When plasma is formed in the spaces 37, 38, 39, electromagnetic energy generated by the ICP coils 31, 32, 33 is absorbed or reflected by the plasma. Therefore, the electromagnetic energy generated by each ICP coil 31, 32, 33 cannot pass through the spaces 37, 38, 39, and the electromagnetic field generated by each ICP coil 31, 32, 33 is the space 37, 38. , 39 are confined within the range of the grooves 34, 35, 36. That is, interference between each electromagnetic field is reduced. Thus, since interference between the electromagnetic fields formed by the ICP coils 31, 32, 33 is reduced, high frequency power is independently applied to the ICP coils 31, 32, 33 from the high frequency power sources 17, 18, 19, respectively. By doing so, etching uniformity can be secured even for a large-diameter wafer having a diameter of about 300 mm. The lower electrode 12 is applied with a 200 W high frequency power (frequency 13.56 MHz) from a high frequency power supply 26.

  Further, as described above, the FS electrodes 14, 15, 16 provided on the outer wall surface of the upper top plate 30 corresponding to the spaces 37, 38, 39 are connected to the most central ICP coil 31 by the conductive tap 25. Has been. For this reason, the high frequency power is applied to the FS electrodes 14, 15 and 16 simultaneously with the application of the high frequency power to the most central ICP coil 31. Here, a DC bias component of 600 V is applied to each FS electrode 13, 14, 15 by adjusting the capacitance value of the tuning capacitor 22.

Reaction products such as PtCl ₂ , PtCl ₄ , and IrCl ₃ generated in the course of the etching process solidify and try to adhere when they reach the upper top plate 30. However, in the present embodiment, the FS electrode 14 to which a DC bias that is capacitively coupled with the plasma in the chamber 11 is applied to the outer wall side of the upper top plate 30 corresponding to the spaces 37, 38, and 39, which are mutual interference reducing means. 15 and 16 are provided. For this reason, ions in the plasma can be incident during the etching process, and reaction products can be prevented from adhering to the spaces 37, 38, 39 due to the sputtering action of the ions. As a result, unlike the prior art, reaction products adhere to the space that is a means for reducing mutual interference, and particles using the attached reaction products as a generation source are not generated. In addition, adhesion of reaction products to the inner wall side of the chamber 11 in the grooves 34, 35, 36 is prevented by incidence of ions or the like due to capacitive coupling components generated by the ICP coils 31, 32, 33. For example, in the etching process under the conditions shown in Table 2, the number of particles having a particle diameter of 0.1 μm or more (the value obtained by subtracting the number of particles on the wafer before processing from the number of particles on the wafer after processing) is 20 There are very few levels.

  In the present embodiment, the FS electrode is not disposed on the entire outer wall surface of the upper top plate 30, but only at positions corresponding to the spaces 37, 38, 39 where a large amount of reaction products adhere, 15 and 16 are arranged. For this reason, the excessive sputtering to the position where a reaction product does not adhere much is suppressed, and the problem that the inner wall side is shaved and the upper top plate 30 is consumed does not occur.

  By performing the etching process under the above conditions, as shown in FIG. 3B, the Ir film 42 and the Pt film 43 in the region not covered with the mask pattern 41 are removed, and the Ir film 42 and the Pt film 43 are removed. An electrode pattern is formed.

Thereafter, dry etching using CF ₄ or the like as a process gas is performed, and as shown in FIG. 3C, the mask pattern 41 made of a TiN film and the TiN film 44 exposed by the above etching process are removed.

  As described above, an electrode pattern having a laminated structure of Pt film / Ir film is formed. Such an electrode pattern is used as a lower electrode of a capacitor constituting a nonvolatile memory. FIG. 4 is a cross-sectional view of such a capacitor. In FIG. 4, the same reference numerals are given to the elements described in FIG. In FIG. 4, the lower structure covered with the lower layer film 46 includes a semiconductor substrate 50 in which a semiconductor element such as a transistor is formed in a region divided by the element isolation 51, a BPSG (Boro-Phospho Silicate Glass) film, and the like. This is an interlayer insulating film 47. On the lower electrode formed as described above, a ferroelectric film 45 such as a strontium bismuth tantalate (SBT) film is formed as a capacitor insulating film, and the upper electrode is formed on the ferroelectric film 45. As a result, a Pt film 48 is formed. Although not shown in FIG. 3, the lower electrode is connected to the active layer 52 on the surface of the semiconductor substrate 50 by a contact plug made of tungsten or the like that penetrates the interlayer insulating film 47.

  As described above, according to the present embodiment, it is possible to prevent reaction products from adhering to the upper top plate during plasma processing, and it is possible to perform uniform plasma processing even on large-diameter wafers. As a result, the workpiece can be processed with a high manufacturing yield, and the manufacturing cost can be reduced.

(Second Embodiment)
In the first embodiment, the same DC bias component is applied to each FS electrode 14, 15, 16. However, a different DC bias component may be applied to each FS electrode 14, 15, 16.

  FIG. 5 is a schematic block diagram showing a plasma etching apparatus in the second embodiment of the present invention. FIG. 6 is a schematic plan view showing the plasma etching apparatus in the present embodiment. Note that a cross-sectional view taken along line BB in FIG. 6 corresponds to FIG. Note that the plasma etching apparatus of this embodiment is different from that of the first embodiment in that the FS electrodes 14, 15, 16 provided on the outer wall side of the upper top plate 30 corresponding to the spaces 37, 38, 39 are conductive taps. 27, 28, and 29 are different in that they are connected to different ICP coils 31, 32, and 33. Other configurations are the same as those of the plasma etching apparatus of the first embodiment. According to this configuration, high frequency power is applied to the FS electrode 14 from the high frequency power supply 17 through the most central ICP coil 31. Further, high frequency power is applied to the FS electrode 15 from the high frequency power supply 18 through the intermediate ICP coil 32. Further, high frequency power is applied to the FS electrode 16 from the high frequency power source 19 through the outermost peripheral ICP coil 33. As a result, each FS electrode 14, 15, 16 can be independently provided with a DC bias component that capacitively couples with the plasma generated in the chamber 11. In FIG. 5, the same elements as those described in FIG. 1 are denoted by the same reference numerals, and detailed description below is omitted.

  When performing the etching process in the plasma etching apparatus of this configuration, first, the wafer 21 to be processed is loaded from a loading / unloading port (not shown) provided on the side wall of the chamber 11 and placed on the lower electrode 12. Here, as in the first embodiment, the sample shown in the structural cross-sectional view of FIG. After the wafer 21 is placed in the chamber 11, the wafer 21 is etched. Here, the etching process is performed under the conditions shown in Table 3 below.

That is, first, a process gas composed of a mixed gas of Cl ₂ gas and O ₂ gas whose flow rate is controlled through a gas introduction unit (not shown) is introduced into the chamber 11. Here, as in the first embodiment, the flow rate of Cl ₂ gas is 100 sccm, and the flow rate of O ₂ gas is 250 sccm. At this time, the pressure in the chamber 11 is maintained at about 2.0 Pa. The lower electrode 12 is maintained at 450 ° C. Thereby, the temperature of the wafer 21 is also raised to a similar temperature.

  After the pressure inside the chamber 11 is stabilized, high frequency power is applied to the ICP coils 31, 32, 33 by the high frequency power sources 17, 18, 19. Here, high-frequency power having a frequency of 13.56 MHz is applied to the most central ICP coil 31 at 300 W, the intermediate ICP coil 32 at 400 W, and the outermost peripheral ICP coil 33 at 600 W. As a result, plasma of the process gas is generated in the chamber 11. At this time, the electromagnetic field generated by each ICP coil 31, 32, 33 is confined within the range of the grooves 34, 35, 36 divided by the spaces 37, 38, 39. Further, 200 W high frequency power (frequency 13.56 MHz) is applied to the lower electrode 12 from a high frequency power supply 26.

  As described above, the FS electrodes 14, 15, and 16 are connected to the most central ICP coil 31, the intermediate ICP coil 32, and the outermost peripheral ICP coil 33 by the conductive taps 27, 28, and 29, respectively. For this reason, the high frequency power is applied to the FS electrodes 14, 15, 16 simultaneously with the application of the high frequency power to the ICP coils 31, 32, 33. Here, by adjusting the capacitance values of the tuning capacitors 22, 23, and 24, DC bias components of 1000 V, 800 V to the FS electrode 14, and 600 V to the FS electrode 15 are applied to the FS electrode 13, respectively.

  Also in this embodiment, as shown in Table 3, the number of particles having a particle diameter of 0.1 μm or more is 20 or less, and a good etching process with few particle defects is performed as in the first embodiment. Can do. In particular, in the present embodiment, different potentials can be applied to the FS electrodes 14, 15, and 16 independently. Since this configuration can set an optimum voltage value according to the position of the upper top plate 30, it is particularly suitable when the deposition rate of the reaction product differs between the central portion and the outer peripheral portion of the upper top plate 30. Generally, the reaction product generated from the wafer 21 isotropically scatters in the direction of the upper top plate 30, so that the reaction product reaches the center portion of the upper top plate 30 more than the peripheral portion. For this reason, the DC bias component applied according to the position of the upper top plate 30 can be optimized by adopting a configuration in which a voltage can be independently applied to the FS electrodes 14, 15, and 16. Therefore, according to the configuration of the present embodiment, the reaction product is prevented from adhering over the entire surface of the upper top plate 30, and excessive sputtering to the upper top plate 30 is prevented, so that the upper top plate 30 is etched. This can be prevented more reliably.

  As described above, according to the present invention, it is possible to prevent the reaction product from adhering to the inner surface of the chamber of the dielectric wall facing the workpiece during plasma processing, and even to a large-diameter wafer. Plasma treatment can be performed. Further, since the reaction product can be prevented from adhering, particles are not generated during the etching process. As a result, the workpiece can be processed with a high manufacturing yield, and the manufacturing cost can be reduced.

  The present invention is not limited to the embodiment described above, and various modifications and applications are possible within the scope of the effects of the present invention. For example, in the above description, the case where the mutual interference reducing unit is a space has been described. However, it is also possible to employ a mutual interference reducing unit having another configuration. For example, the mutual interference reducing means can be formed of an insulator. In this case, as shown in FIG. 7, the upper top plate 30 is configured as a flat flat plate, and is used to reduce mutual interference between the ICP coils 31, 32, and 33 arranged on the chamber outer wall side of the upper top plate 30. Insulator 61 is disposed. In this case, each of the FS electrodes 14, 15, and 16 is disposed between the insulator 61 and the upper top plate 30. In the example of FIG. 7, each FS electrode 14, 15, 16 is connected to the most central ICP coil 31 by the conductive tap 25 as in the first embodiment, but is the same as in the second embodiment. Alternatively, an independent potential may be applied to each FS electrode 14, 15, 16.

  The present invention is not limited to a plasma etching apparatus, and can be applied to any plasma processing apparatus having an ICP coil corresponding to a dielectric wall. In addition, in the above, an etching process of a difficult-to-etch material such as Pt or Ir, to which the present invention is particularly suitable, has been shown as a specific example, but the present invention is similar to any material film etching process. An effect can be obtained.

  INDUSTRIAL APPLICABILITY The present invention is useful as a plasma processing apparatus and a plasma processing method for generating or processing a platinum-based or noble metal-based material compound that has a low vapor pressure and is not easily removed, such as a nonvolatile memory electrode material.

1 is a schematic configuration diagram showing a plasma processing apparatus according to a first embodiment of the present invention. 1 is a schematic plan view showing a plasma processing apparatus according to a first embodiment of the present invention. Cross section of sample structure for plasma treatment Sectional drawing of the structure of a semiconductor device provided with the electrode shown in FIG. The schematic block diagram which shows the plasma processing apparatus in the 2nd Embodiment of this invention. The schematic plan view which shows the plasma processing apparatus in the 2nd Embodiment of this invention. The schematic block diagram which shows the modification of the plasma processing apparatus in embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Chamber 12 Lower electrode 14 Central part FS electrode 15 Middle part FS electrode 16 Outermost part FS electrode 17, 18, 19, 26 High frequency power supply 21 Wafer 22, 23, 24 Tuning capacitor 25, 27, 28, 29 Conductive tap 30 Upper top plate 31 Centralmost ICP coil 32 Intermediate ICP coil 33 Outermost peripheral ICP coil 34, 35, 36 Groove 37, 38, 39 Space (Mutual interference reducing means)

Claims (7)

In a plasma processing apparatus that performs plasma processing of a workpiece disposed in a chamber by plasma generated in the chamber,
A chamber having a dielectric wall that transmits electromagnetic waves at a position facing a workpiece disposed therein;
A gas introduction part for introducing a process gas into the chamber;
A gas discharge unit for discharging a gas containing the process gas in the chamber;
A plurality of coils disposed outside the chamber corresponding to the dielectric wall and generating plasma in the chamber;
Means for reducing mutual interference of electromagnetic fields generated between the plurality of coils and generated by each coil;
A Faraday shield electrode provided at each of the arrangement positions of the mutual interference reducing means,
A plasma processing apparatus comprising:   The plurality of coils are accommodated in a plurality of grooves formed in the dielectric wall, respectively, and the mutual interference reducing means is provided adjacent to each groove by a space continuous with the internal space of the chamber. The plasma processing apparatus according to claim 1, wherein the Faraday shield electrode is provided on an outer wall side of the dielectric wall corresponding to the space.   The plasma processing apparatus according to claim 1, wherein the Faraday shield electrode is commonly connected to one coil selected from the plurality of coils.   The plasma processing apparatus according to claim 1, wherein the Faraday shield electrode is connected to the different coils. In a plasma processing method for performing plasma processing on a workpiece disposed in a chamber by plasma generated in the chamber using a plurality of coils disposed at positions opposed to the processing surface,
Introducing a process gas into the chamber and generating a plasma by applying high frequency power to the plurality of coils;
Performing plasma treatment in a state where a potential is applied to the Faraday shield electrode provided at each of the positions where the mutual interference reducing means for reducing the mutual interference of the electromagnetic fields generated by the coils is disposed;
A plasma processing method comprising:   The plasma processing method according to claim 5, wherein the plasma processing is performed in a state where an independent potential is applied to each of the Faraday shield electrodes. Each potential applied to the Faraday shield electrode is independently set to a state in which a product generated during the plasma processing and attached to the inner wall of the chamber corresponding to the position where the mutual interference reducing means is disposed is removed. The plasma processing method according to claim 6.

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