JP2007242865A - Multilayer flexible printed wiring board - Google Patents

Abstract

A multilayer flexible printed wiring board capable of reducing the thickness of a substrate as much as possible and minimizing warpage and deformation during reflow is provided.
A multilayer flexible printed wiring board (multi-layer printed circuit board) having an inner layer substrate (11) having circuits on both sides and an outer layer substrate (16) laminated on both sides of the inner layer substrate (11), wherein inter-layer conduction of circuits of each layer is made by plating. FPC) 10, the thickness B of the outer plating layer 18 is set to 100 to 200% of the thickness A of the inner plating layer 13.
[Selection] Figure 1

Description

  The present invention relates to a multilayer flexible printed wiring board in which two or more substrates are laminated, and more particularly to a multilayer flexible printed wiring board in which interlayer conduction is achieved by plating.

  Conventionally, as a multilayer printed wiring board used as a circuit board in electrical and electronic equipment, a rigid flex (RF) print in which a rigid printed wiring board (RPC) and a flexible printed wiring board (FPC) are combined. Wiring boards are well known, and R-F printed wiring boards are employed in electronic devices such as digital cameras. Furthermore, in recent years, in order to reduce the weight and thickness of electric and electronic devices, the adoption of multilayer flexible printed wiring boards (multilayer FPC), which is composed entirely of FPCs, is also progressing.

As an example of the structure of a general multilayer printed wiring board, an example of the structure of a four-layer flexible printed wiring board is shown in FIG. An example of a manufacturing process for the multilayer FPC 20 shown in FIG.
(1) A through hole 22 is formed at a predetermined position of the double-sided CCL to be the inner layer substrate 21, and the inner surface of the through-hole 22 and the copper foil 21b of the double-sided CCL are plated and between both sides (L2, L3 layers) of the double-sided CCL. Ensure continuity. Reference numeral 21a denotes a double-sided CCL base material, and reference numeral 23 denotes an inner plating layer.
(2) After circuit formation of the inner layers (L2, L3), coverlay (CL) 24 is adhered. Reference numeral 24a is a CL24 base material, and reference numeral 24b is a CL24 adhesive.
(3) Single-sided CCL to be the outer layer substrate 26 is bonded to both sides of the inner layer substrate 21 via the adhesive layer 25, respectively.
(4) A non-through hole 27 (the inner layer circuits L2 and L3 serve as the bottom of the non-through hole 27) is formed in the outer substrate 26 using a laser.
(5) The inner surface of the non-through hole 27 and the copper foil 26b of the outer layer substrate 26 are plated to ensure conduction between the inner layer and the outer layer (L1 layer and L2 layer, L3 layer and L4 layer). Reference numeral 26a denotes a single-sided CCL base material, and reference numeral 28 denotes an outer plating layer.
(6) Circuit formation of the outer layers (L1, L4) is performed.
(7) Surface layer resist process and surface treatment are performed. Reference numeral 29 denotes a surface layer resist.

Regarding the mounting technology of components to FPC, Patent Document 1 discloses that in a thin substrate fixing jig having a weak adhesive layer on one side of a flat plate, at least flip to prevent the thin substrate from being bent downward during flip chip mounting. In a position opposite to the position where the chip is mounted on the thin substrate, a bulging portion is projected on the surface of the flat plate.
Further, in Patent Document 2, a slit is provided around a part of the component mounting board where an electrical component is installed (referred to as “inner board” in Patent Document 2), and a part outside the slit (Patent Document 2). Document 2 describes a configuration that can relieve the stress applied to the electrical component and the connection part between the electrical component and the component mounting board even if the external substrate is deformed by external force. Yes.
JP 2005-175071 A JP-A-9-148687

  However, with the thinning of the wiring board, there is a problem in that defective mounting of IC components and passive components occurs and the yield decreases. This is because the multilayer FPC has the advantage that the board is thin and can be bent, but the rigidity of the substrate is lower than that of the multilayer RPC or RP printed wiring board, and the wiring board bends during component mounting. This is because the wiring board tends to warp during the reflow process.

  For the above problem, there are proposals of Patent Documents 1 and 2, for example. However, in the case of Patent Document 1, since mounting is performed after the wiring board is fixed to the substrate fixing jig, there is a problem that a jig or fixing work is required and the cost is increased. Further, in the case of Patent Document 2, since the design is restricted, the imposition efficiency is lowered, or this method cannot be adopted depending on the design.

In general, glass epoxy plates (glass fibers hardened with epoxy resin) are widely used as RPC materials, and although the total thickness of the substrate increases, the substrate has high rigidity, excellent surface smoothness, and reflow. Since the board does not warp during the process, the component mounting performance is generally excellent.
This reflow process is already known as surface mounting technology (SMT), flip chip mounting. Simply put, this is a process of mounting a component with solder applied to the tip of the printed wiring board at a relevant location and soldering the component to the printed wiring board through a belt conveyor type reflow furnace. Here, the components refer to IC components, passive components, resistors, capacitors, etc. used in electronic devices. The temperature of the reflow furnace is set higher than the temperature at which the solder melts. In general, the temperature is often set to 250 ° C. or 270 ° C. And when it comes out of a reflow furnace, since it is the temperature below the melting | fusing point of solder, it is a board | substrate with which components were solder-fixed.

  When considering component mountability during the reflow process, one of the points is warping or deformation of the board. That is, if the substrate is warped or deformed at a high temperature, the components may be misaligned or the soldering may be insufficient. In a severe case, a conduction failure may occur, and the function as a printed wiring board may be lost. Therefore, it is obvious that the warpage and deformation of the substrate must be minimized as much as possible during the reflow process.

In general, a rigid plate is known to be excellent in heat resistance in terms of its material and rigidity, and warpage and deformation of the substrate are small during the reflow process. On the other hand, in the case of a flexible substrate, it is known that the degree of warpage and deformation when a high temperature is applied is relatively large.
However, in recent years, the space occupied by the printed wiring board in the housing has been limited and reduced due to the downsizing and higher functionality of electronic devices. Furthermore, the number of components to be mounted is increasing, and high reliability is required for component mounting. That is, there has been a demand for a printed wiring board in which the substrate thickness is made as thin as possible and the warpage and deformation during reflow are as small as possible.

  The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a multilayer flexible printed wiring board capable of reducing the substrate thickness as much as possible and minimizing warpage and deformation during reflow. To do.

In order to solve the above-mentioned problems, the present invention provides a multilayer flexible print comprising an inner layer substrate having circuits on both sides and an outer layer substrate laminated on both sides of the inner layer substrate, wherein interlayer conduction of circuits in each layer is made by plating. Provided is a multilayer flexible printed wiring board, wherein the thickness of the outer plating layer is 100 to 200% of the thickness of the inner plating layer.
The inner plating layer and the outer plating layer are preferably formed by plating once or twice or more on the same layer.

  According to the present invention, in the multilayer flexible printed wiring board, the thickness of the outer plating layer is set to 100 to 200% of the thickness of the inner plating layer, so that the substrate thickness is larger than the printed wiring board using the rigid board. And the rigidity of the substrate in the flexible wiring board can be ensured. As a result, it is possible to minimize the warpage and deformation of the substrate during the reflow process and component mounting, and to improve component mountability.

  In the present invention, the rigidity of the substrate is improved by controlling the plating thickness of the outer layer with respect to the inner layer while realizing the thinning of the wiring board by using the FPC in the multilayer printed wiring board, We have achieved reduction in warpage and deformation of the substrate during the reflow process, and improved mounting of electronic components (yield in mounting IC components and passive components).

Specifically, when plating is performed on the inner layer and the outer layer of a multilayer flexible printed wiring board (hereinafter sometimes referred to as “multilayer FPC”), the thickness of the outer layer plating layer is the thickness of the inner layer plating layer. Within the range of 100 to 200% of the thickness. That is, in the present invention, when the plating thickness of the inner layer is A (μm) and the plating thickness of the outer layer is B (μm), the percentage expressed by “B / A × 100%” (hereinafter referred to as “to the inner layer”). The outer layer plating thickness (%) ”may be 100 to 200%.
Here, the thickness of the inner layer plating thickness A and the outer layer plating thickness B is the thickness of the plating layer formed on the copper foil of the copper clad laminate (CCL) as shown in FIGS. In other words, it does not include the plating portion formed on the inner surface of the hole.

The reason why it is desirable to form the outer layer plating thickness B at 100% or more with respect to the inner layer plating thickness A is that the rigidity of the substrate can be improved. That is, in the multilayer FPC, component mounting is performed in a multilayer portion in which the inner layer substrate 11 and the outer layer substrate 16 are laminated. As the thickness of the outer plating layer is increased, insufficient rigidity of the flexible wiring board is reinforced by the rigidity of the plating layer, and it becomes easier to ensure the rigidity of the board necessary for component mounting.
Therefore, in the present invention, since the lower limit of the plating thickness B of the outer layer is specified, it is set to 100% or more of the plating thickness A of the inner layer, whereby the component mountability of the substrate can be improved.

The reason why it is desirable to set the outer layer plating thickness B to 200% or less with respect to the inner layer plating thickness A is that excessive plating on the outer layer results in excessive quality and increases costs. This is because the variation of the plating thickness becomes large. In general, it is difficult to perform plating uniformly, and it is known to be affected by various effects such as current density, concentration and temperature of a chemical solution, size of a workpiece, and distance from an electrode. As a result, it is known that more plating is deposited at places where plating is likely to deposit, so that the greater the target plating thickness, the greater the degree of unevenness on the surface of the resulting plating layer. The greater the degree of unevenness, the more likely the electrical connection between the outer layer circuit and the mounted component via the solder bumps becomes uncertain.
Therefore, in the present invention, in order to define the upper limit of the plating thickness B of the outer layer, it is set to 200% or less of the plating thickness A of the inner layer, thereby improving the component mountability of the substrate.

  In general, interlayer conduction in a multilayer FPC is performed by a low-cost technique called pattern plating of a substrate. For example, the method of depositing metallic copper on a board | substrate by immersing a board | substrate in a copper sulfate solution etc. and supplying with electricity is mentioned. Furthermore, when forming a multilayer board, the inner layer substrate (multiple layers are allowed) and the outer layer substrate (multiple layers are permitted) are bonded together, and each layer is subjected to pattern plating to achieve interlayer conduction. Is common.

  In the multilayer FPC of the present invention, there are no particular limitations on the substrate size, material thickness, number of layers, configuration, and the like. As an example of the structure of the multilayer FPC, for example, a four-layer flexible printed wiring board illustrated in FIG. In addition, this example is an example and is not intended to limit the present invention. In the multilayer FPC of the present invention, the inner layer substrate may be composed of only one CCL, or may be composed of only two or more CCLs. Further, the number of outer layer substrates may be configured by laminating one CCL on each side of the inner layer substrate, or by laminating two or more.

  A multilayer FPC 10 shown in FIG. 1 includes an inner substrate 11 having circuits L2 and L3 on both surfaces, coverlays 14 and 14 bonded to both surfaces (upper and lower surfaces in FIG. 1) of the inner substrate 11, and circuit L1 on one surface. , L4, two outer layer substrates 16 and 16, adhesive layers 15 and 15 for bonding the inner layer and the outer layer, and a resist layer 19 provided on the outer surface layer. In this multilayer FPC 10, interlayer conduction between the inner layer circuits is taken by the inner layer plating layer 13 including the inner surface of the hole 12 opened in the inner layer substrate 11, and interlayer conduction between the inner layer and the outer layer is performed by the coverlay 14 and The outer layer plating layer 18 includes the inner surface of the hole 17 opened in the outer layer substrate 16.

  Although the manufacturing method of the multilayer FPC 10 shown in FIG. 1 is not particularly limited, a manufacturing process shown below is given as an example.

  For the inner layer substrate 11, first, a double-sided copper-clad laminate (double-sided CCL) in which copper foils 11b and 11b are respectively laminated on both sides of a flexible insulating base material 11a made of an insulating resin such as polyimide is prepared. The through hole 12 is opened at a predetermined position. Here, the double-sided CCL may be formed by directly laminating the insulating base material 11a and the copper foil 11b, and the insulating base material 11a and the copper foil 11b are bonded together via an adhesive (not shown). It may be a thing.

  Next, the inner surface of the through hole 12 and the copper foil 11b on both sides are plated to form the inner plating layer 13 to ensure conduction between the circuits L2 and L3. The inner plating layer 13 may be formed by one plating, or may be formed by two or more platings, either of which may be used.

  Next, the inner conductor layer composed of the copper foil 11b and the plating layer 13 is patterned to form inner layer circuits L2 and L3, and a coverlay (CL) for circuit protection on each of the circuits L2 and L3. 14 is pasted. The coverlay 14 used in this example has an adhesive 14b on one side of a flexible insulating base material 14a made of an insulating resin such as polyimide.

  Next, single-sided CCL to be the outer layer substrate 16 is bonded to both sides of the inner layer substrate 11 (specifically, the surface of the base material 14a of the cover lay 14) via the adhesive layer 15, respectively. In addition, even if the single-sided CCL is formed by directly laminating the insulating base material 16a and the copper foil 16b, the insulating base material 16a and the copper foil 16b are bonded together with an adhesive (not shown). It does not matter.

  Next, the outer layer substrate 16 and the coverlay 14 are drilled from the surface of the outer layer substrate 16 using a laser, and the non-through holes 17 reaching the inner layer circuits L2 and L3 (the circuits L2 and L3 are the bottoms of the non-through holes 17). Dawn.)

Next, the inner surface of the non-through hole 17 and the copper foil 16b of the outer layer substrate 16 are plated to form the outer layer plating layer 18, and between the inner layer and the outer layer (between the L1 layer and the L2 layer and between the L3 layer and the L4 layer). To ensure electrical continuity). The outer plating layer 18 may be formed by one plating, or may be formed by two or more platings, either of which may be used.
In the present invention, the thickness B of the plating layer 18 formed on the copper foil 16 b of the outer layer substrate 16 is set to 100 to 200 of the thickness A of the plating layer 13 formed on the copper foil 11 b of the inner layer substrate 11. %. As a result, the rigidity of the board in the flexible wiring board can be ensured, and the warpage and deformation of the board during the reflow process for mounting the parts on the outer-layer circuits L1 and L4 can be reduced as much as possible to improve the component mounting performance. Is possible.

(6) Next, the outer conductor layer composed of the copper foil 16b and the plating layer 18 is patterned to form the outer circuits L1 and L4.
(7) Then, by performing a surface layer resist process or surface treatment for forming the resist layer 19 at a predetermined position on the outer layer substrate 16, the multilayer FPC 10 shown in FIG. 1 is obtained.

The multilayer FPC 10 in which the thickness B of the outer plating layer 18 obtained by the above manufacturing process is 100 to 200% of the thickness A of the inner plating layer 13 is excellent in the rigidity of the substrate in the flexible wiring board, and the outer layer circuit L1. , Warpage and deformation of the substrate during the reflow process for mounting components on L4 are minimized. For this reason, the component mountability is excellent. Moreover, since it comprised only the flexible printed wiring board without using a rigid board, the total thickness of a board | substrate can be suppressed and it can respond to weight reduction and thickness reduction.
The present invention does not require the use of a special jig for component mounting, and has an excellent advantage that it can be implemented at a low cost without any design restrictions and a decrease in imposition efficiency.

In this experiment, a 20-piece multilayer FPC was fabricated for each condition. The multi-layer FPC has 10 IC components and 80 passive components mounted on each piece.
The produced multilayer FPC is subjected to a gas phase heat shock test (-25 ° C to 125 ° C / 60 min cycle), and the number of cycles until one of the IC components or passive components is disconnected is measured. The average value of 20 pieces Was used as an index for mounting evaluation. That is, it is judged that the mountability is better as the number of cycles is larger.

(Materials used)
Inner layer (L2, L3 layer) double-sided CCL: rolled copper foil (12 μm thickness), polyimide substrate (25 μm thickness)
Outer layer (L1, L4 layer) single-sided CCL: electrolytic copper foil (12 μm thickness), polyimide substrate (25 μm thickness)
Coverlay (CL): Epoxy adhesive (25 μm thickness), polyimide substrate (25 μm thickness)
Interlayer adhesive sheet: Epoxy adhesive (25 μm thick)
Surface resist: Alkali developable dry film type solder resist (38μm thick)
Substrate size: 300x300mm
10 pieces of IC parts and 80 pieces of passive parts are mounted on a flip chip per piece of 60 pieces per sheet.

(Production method)
(1) A through hole is made at a predetermined position of the double-sided CCL to be the inner layer substrate, and the inner surface of the through-hole and the copper foil of the double-sided CCL are plated to ensure conduction between both sides (L2, L3 layers) of the double-sided CCL. To do.
(2) After circuit formation of the inner layers (L2, L3), a cover lay (CL) is stuck on each circuit.
(3) A single-sided CCL to be an outer layer substrate is bonded to both sides of the inner layer substrate via an adhesive layer.
(4) Using a laser, a non-through hole (inner layer circuits L2 and L3 serve as the bottom of the non-through hole) is formed in the outer layer substrate.
(5) The inner surface of the non-through hole and the copper foil on the outer layer substrate are plated to ensure conduction between the inner layer and the outer layer (L1 layer and L2 layer, and L3 layer and L4 layer).
(6) Circuit formation of the outer layers (L1, L4) is performed.
(7) A surface layer resist process and surface treatment are performed to complete a multilayer FPC.

<Test Example 1>
Only the plating thickness was changed so that the total substrate thickness was the same, and samples were produced. For each condition, 20 pieces (however, only in Test Example 1, the number of components mounted was one IC component and eight passive components mounted per piece). Vapor phase heat shock test (-25 ° C to 125 ° C / 60 min cycle) is performed, and the number of cycles until either one of the IC components or passive components breaks is measured. It was used as an index.
FIG. 3 shows the relative value of the number of cycles until disconnection, with the case where the plating thickness (%) of the outer layer relative to the inner layer is 100% as a reference (relative value of the number of cycles = 100%).

  From the result of Test Example 1 shown in FIG. 3, the line representing the relationship of the relative value of the cycle number to the plating thickness (%) of the outer layer relative to the inner layer can be divided into three regions. That is, region 1 (outer layer plating thickness with respect to inner layer (%) = 50% or more and less than 100%) is a region where the cycle number (relative value) until disconnection changes greatly, region 2 (outer layer plating thickness with respect to inner layer (%) ) = 100% or more and 200% or less) is a region where the number of cycles until disconnection (relative value) does not decrease, and region 3 (outer layer plating thickness (%) with respect to inner layer = more than 200% and less than 300%) This is a region where the number of cycles (relative value) changes greatly.

  Considering the quality and manufacturing cost as an electronic device or electric device, the region 2 having a high cycle number (relative value) until disconnection is most suitable. On the other hand, in the region 1 and the region 3, the number of cycles (relative value) until disconnection greatly changes due to a change in the plating thickness (%) of the outer layer with respect to the inner layer, which causes a large variation in quality. There is a problem.

<Test Example 2>
In general, a double-sided CCL (double-sided board) used on the inner surface of a multilayer board is subjected to through-hole plating in order to achieve interlayer conduction. In recent years, the double-sided CCL has been thinned, and a mainstream is a 25 μm thick polyimide bonded with a 9 to 12 μm thick copper foil. In the case of such a double-sided CCL, although depending on the diameter of the through hole, it is known that if the plating thickness is approximately 10 μm or more, the reliability can be maintained in the accelerated deterioration test and the heat shock test. Therefore, in Test Example 2, the inner layer plating thickness was fixed to 13 μm, and only the outer layer plating thickness was changed to prepare a sample. The roughness Rz of the sample surface was measured with a laser microscope for each 20 pieces. The result is shown in FIG.

  From the result of Test Example 2 shown in FIG. 4, the line representing the relationship of the surface roughness Rz to the plating thickness (%) of the outer layer relative to the inner layer can be divided into two regions. That is, region 1 (outer layer plating thickness (%) with respect to inner layer = 50% or more and 200% or less) is a region with low roughness, region 2 (outer layer plating thickness (%) with respect to inner layer = over 200% and 300% or less) ) Is a region where the roughness greatly changes.

In general, it is difficult to perform plating uniformly, and it is known to be affected by various effects such as current density, concentration and temperature of a chemical solution, size of a workpiece, and distance from an electrode. As a result, the plating copper is plated more in places where copper plating is likely to be deposited, so that when the substrate is viewed microscopically, surface irregularities are generated. It is known that the surface roughness increases as the plating thickness increases. Since Test Example 2 has the inner layer plating thickness fixed at 13 μm, the horizontal axis of FIG. 4 can be converted to the absolute value of the outer layer plating thickness. Therefore, a line representing the relationship of the surface roughness Rz to the plating thickness (%) of the outer layer relative to the inner layer is always a curve that rises to the right.
Further, the present inventors have found that in this relationship, the curve does not rise monotonously but has a certain inflection point and is divided into two regions.

<Test Example 3>
Samples were produced by changing only the plating thickness so that the total substrate thickness was the same. The substrate stiffness was measured for each 20 pieces.
FIG. 5 shows the relative value of the rigidity of the wiring board, with the reference (relative value of the rigidity of the substrate = 1.0) when the plating thickness (%) of the outer layer with respect to the inner layer is 100%.

  From the result of Test Example 3 shown in FIG. 5, the line indicating the relationship of the relative value of the rigidity of the wiring board to the plating thickness (%) of the outer layer relative to the inner layer can be divided into two regions. That is, the region 1 (outer layer plating thickness with respect to the inner layer (%) = 50% or more and less than 100%) is a region where the relative value of the rigidity of the wiring board changes greatly, and the region 2 (outer layer plating thickness with respect to the inner layer (%)) = 100% or more and 300% or less) is a region having high rigidity.

The multilayer FPC in this test example is composed of copper, plated copper, polyimide, adhesive, and resist. Among them, except for the plated copper, the thickness is determined at the material stage such as CCL and CL, but only the thickness of the plated copper is determined at the process stage of the multilayer FPC. That is, when the constituent material is determined, it is the thickness of the plated copper that determines the rigidity of the finished substrate. It is obvious that as the thickness of the plated copper increases, the rigidity of the board increases. Therefore, the line representing the relative value of the rigidity of the wiring board to the plating thickness (%) of the outer layer relative to the inner layer is always the right It becomes a rising curve.
Further, the present inventors have found that in this relationship, the curve does not rise monotonously but has a certain inflection point and is divided into two regions.

(Conclusion based on Test Examples 1 to 3)
From Test Examples 1 to 3, it is understood that the mountability (number of cycles until disconnection) is affected by the roughness of the surface of the wiring board and the rigidity of the wiring board. That is, in the region where the plating thickness (%) of the outer layer with respect to the inner layer is 50% or more and less than 100%, the wiring board has low rigidity, so that the mountability is reduced, and the plating thickness (%) of the outer layer with respect to the inner layer exceeds 200%. In the region of 300% or less, the roughness of the wiring board is greatly increased, and the mountability is deteriorated.
On the other hand, a region where the plating thickness (%) of the outer layer with respect to the inner layer is 100% or more and 200% or less is a region where both the rigidity of the wiring board and the surface roughness Rz are good, and thus the mountability is high.

  Since the multilayer flexible printed wiring board of the present invention is excellent in component mountability, it is suitable as a multilayer printed wiring board used as a circuit board in electrical equipment and electronic equipment.

It is typical sectional drawing which shows an example of the multilayer flexible wiring board of this invention. It is typical sectional drawing which shows an example of the conventional multilayer flexible wiring board. 6 is a graph showing the results of Test Example 1. 6 is a graph showing the results of Test Example 2. 10 is a graph showing the results of Test Example 3.

Explanation of symbols

A ... inner layer plating thickness, B ... outer layer plating thickness, 10 ... multilayer flexible printed wiring board (multilayer FPC), 11 ... inner layer substrate, 13 ... inner layer plating layer, 16 ... outer layer substrate, 18 ... outer layer plating layer.

Claims (2)

A multilayer flexible printed wiring board comprising an inner layer substrate having circuits on both sides, and an outer layer substrate laminated on both sides of the inner layer substrate, wherein the interlayer conduction of the circuit of each layer is made by plating,
A multilayer flexible printed wiring board, wherein the thickness of the outer plating layer is 100 to 200% of the thickness of the inner plating layer.   2. The multilayer flexible printed wiring board according to claim 1, wherein the inner plating layer and the outer plating layer are formed on the same layer by one or more times of plating.

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