JP2007129163A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the device area of an ESD protection semiconductor device. <P>SOLUTION: In the ESD protection semiconductor device, a protection thyristor 10 interposed between its I/O terminal and its GND terminal, and a protection thyristor 20 interposed between its power-supply terminal and its GND terminal, have a first NPN transistor 21 in common. Also, the impurity diffusing layer to be the anode of the protection thyristor 20 interposed between its power-supply terminal and its GND terminal, and the impurity diffusing layer to be the anode of the protection thyristor 10 interposed between its I/O terminal and its GND terminal, are formed in a single well. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a protection circuit for protecting internal elements in an internal circuit from ESD (Electro-Static Discharge), and more particularly to a semiconductor device having an ESD protection circuit with high area efficiency.

  In recent years, along with the miniaturization of semiconductor integrated circuits, there is a demand for an ESD protection semiconductor device having a small area, high ESD current discharge capability, and high area efficiency. As ESD protection semiconductor devices with high area efficiency, various ESD protection elements and ESD protection circuits using thyristors have been proposed.

  FIG. 7 is a circuit diagram showing a configuration of a conventional ESD protection semiconductor device. The configuration shown in FIG. 7 is disclosed in Non-Patent Document 1, for example. As shown in FIG. 7, in a conventional ESD protection semiconductor device, an N-type MIS transistor is used for each of an I / O (In / Out) terminal-GND terminal protection thyristor 110 and a power supply terminal-GND terminal protection thyristor 120. Some trigger elements 113 and 123 are provided. In the configuration shown in FIG. 7, the breakdown currents of the trigger elements 113 and 123 are caused to flow through the emitters and bases of the PNP transistors 111 and 122 constituting the thyristors 110 and 120, whereby the PNP transistors 111 and 122 and the NPN transistors 112 and 121 are The operation state is entered, and the thyristors 110 and 120 operate.

  FIG. 8 is a cross-sectional view showing the structure of the semiconductor device constituting the circuit shown in FIG. As shown in FIG. 8, in a conventional semiconductor device, a trigger element 113 for an I / O terminal-GND terminal protection thyristor 110 and an I / O terminal-GND terminal protection thyristor 110 are provided in a P-type semiconductor substrate 131. The trigger element 123 for the power supply terminal-GND terminal protection thyristor 120 and the power supply terminal-GND terminal protection thyristor 120 are arranged independently.

When a thyristor is used as a protection element, an ESD protection circuit can generally be configured with a smaller area than when an N-type MIS transistor or a P-type MIS transistor is used as a protection element.
Markus PJMergens et al., IEEE., 2003, 0-7803-7873-3

  However, in the conventional configuration, when the protective thyristor 120 between the power supply terminal and the GND terminal is formed, there is a problem that the area of the ESD protection semiconductor device is increased.

  Accordingly, an object of the present invention is to reduce the device area of an ESD protection semiconductor device.

  The semiconductor device according to the first aspect of the present invention is a semiconductor device having a protection circuit, and the protection circuit includes a first PNP transistor having an emitter connected to the input / output terminal and protection between the input / output terminals and the GND terminal. A thyristor, a power supply terminal-GND terminal protection thyristor having a second PNP transistor having a base connected to a base of the first PNP transistor and an emitter connected to a power supply terminal; and a base of the first PNP transistor And a first NPN whose collector is connected to the base of the second PNP transistor, whose emitter is connected to the GND terminal, and whose base is connected to the collector of the first PNP transistor and the collector of the second PNP transistor. And the first NPN transistor includes the input / output terminal -GN. It is shared by the inter-terminal protecting thyristors and the power supply terminals -GND inter-terminal protection thyristor.

  According to the semiconductor device of the first aspect of the present invention, since the first NPN transistor is shared by the protective thyristor between the input / output terminal and the GND terminal and the protective thyristor between the power supply terminal and the GND terminal, the device area can be reduced. Therefore, the chip can be downsized.

  In the semiconductor device according to the first aspect of the present invention, the semiconductor region, the P-type well formed in the semiconductor region, the N-type well formed in the semiconductor region, and the P-type well are formed. A first P-type impurity diffusion layer and a first N-type impurity diffusion layer; a second P-type impurity diffusion layer formed in the N-type well; a third P-type impurity diffusion layer; A first impurity diffusion layer, and the first PNP transistor includes the second P-type impurity diffusion layer, the N-type well, and the P-type well including the first P-type impurity diffusion layer, The second PNP transistor includes the P-type well including the third P-type impurity diffusion layer, the N-type well, and the first P-type impurity diffusion layer, and the first NPN transistor includes the first NPN transistor, First N-type impurity diffusion layer It may be composed of the P-type well and the second of said N-type well including the N-type impurity diffusion layer. In this case, since the second P-type impurity diffusion layer and the third P-type impurity diffusion layer are formed in one N-type well, the device area can be further reduced.

  In this case, the semiconductor device may further include a third PNP transistor having the second P-type impurity diffusion layer as a collector, the third P-type impurity diffusion layer as an emitter, and the N-type well as a base. In this case, the punch-through breakdown voltage between the emitter and the collector of the third PNP transistor is set to a value smaller than the breakdown voltage of the gate oxide film of the P-type MIS transistor in the internal circuit, so that there is a gap between the power supply terminal and the input / output terminal. Can have a protective function.

  In the semiconductor device of the first aspect of the present invention, a semiconductor region, an N-type well formed in the semiconductor region, a P-type diffusion region formed in the N-type well, and the P-type diffusion region The formed first P-type impurity diffusion layer and first N-type impurity diffusion layer, the second P-type impurity diffusion layer, the third P-type impurity diffusion layer and the first P-type impurity diffusion layer formed in the N-type well. 2 N-type impurity diffusion layers, and the first PNP transistor includes the second P-type impurity diffusion layer, the N-type well, and the P-type well including the first P-type impurity diffusion layer. The second PNP transistor includes the P-type well including the third P-type impurity diffusion layer, the N-type well, and the first P-type impurity diffusion layer, and the first NPN The transistor includes the first N-type impurity Goldenrod, may be constituted from the P-type well and the second of said N-type well including the N-type impurity diffusion layer. In this case, the punch-through breakdown voltage between the emitter and the collector of the third PNP transistor is set to a value smaller than the breakdown voltage of the gate oxide film of the P-type MIS transistor in the internal circuit, so that there is a gap between the power supply terminal and the input / output terminal. Can have a protective function.

  In the semiconductor device according to the first aspect of the present invention, a third PNP transistor having the second P-type impurity diffusion layer as a collector, the third P-type impurity diffusion layer as an emitter, and the N-type well as a base. May be further provided.

  The semiconductor device according to the first aspect of the present invention may further include a trigger element connected to a base of the first PNP transistor and a collector of the first NPN transistor. That is, the trigger element may be attached to the outside of the thyristor.

  In the semiconductor device according to the first aspect of the present invention, an emitter is connected to the input / output terminal, a collector is connected to a collector of the first PNP transistor, and a base is connected to a base of the second PNP transistor. And a fifth PNP transistor having an emitter connected to the power supply terminal, a collector connected to the collector of the fourth PNP transistor, and a base connected to the collector of the first NPN transistor. Furthermore, you may provide.

  In the semiconductor device according to the first aspect of the present invention, when the trigger element is attached to the inside of the thyristor, the semiconductor region, the P-type well formed in the semiconductor region, and the semiconductor element are formed in the semiconductor region. An N-type well, a first P-type impurity diffusion layer and a first N-type impurity diffusion layer formed in the P-type well, and a second P-type impurity diffusion layer formed in the N-type well , A third P-type impurity diffusion layer and a fourth P-type impurity diffusion layer, wherein the first PNP transistor includes the second P-type impurity diffusion layer, the N-type well, and the first P-type impurity diffusion layer. The P-type well including a P-type impurity diffusion layer, and the second PNP transistor includes the P-type impurity diffusion layer, the N-type well, and the P-type impurity diffusion layer. Consists of mold wells The first NPN transistor includes the first N-type impurity diffusion layer, the P-type well, and the N-type well, and the fourth PNP transistor includes the second P-type impurity diffusion layer, The fifth PNP transistor includes an N-type well and the third P-type impurity diffusion layer, and the fifth PNP transistor includes the third P-type impurity diffusion layer, the N-type well, and the fourth P-type impurity diffusion layer. It may be configured. In this case, the device area can be further reduced by sharing the impurity diffusion layer between the thyristor layer and the trigger element.

  In the semiconductor device according to the first aspect of the present invention, when the trigger element is attached to the inside of the thyristor, the semiconductor region, the N-type well formed in the semiconductor region, and the N-type well are formed. A P-type diffusion region, a first P-type impurity diffusion layer and a first N-type impurity diffusion layer formed in the P-type diffusion region, and a second P-type formed in the N-type well. And an impurity diffusion layer, a third P-type impurity diffusion layer, and a fourth P-type impurity diffusion layer, wherein the first PNP transistor includes the second P-type impurity diffusion layer, the N-type well, and the first P-type impurity diffusion layer. The second PNP transistor includes the fourth impurity diffusion layer, the N-type well, and the first P-type impurity diffusion layer. Consists of the P-type diffusion region The first NPN transistor includes the first N-type impurity diffusion layer, the P-type well, and the N-type well, and the fourth PNP transistor includes the second P-type impurity diffusion layer. And the N-type well and the third P-type impurity diffusion layer, and the fifth PNP transistor includes the third P-type impurity diffusion layer, the N-type well and the fourth P-type impurity diffusion layer. It may be composed of layers. In this case, the device area can be further reduced by sharing the impurity diffusion layer between the thyristor layer and the trigger element.

  According to the ESD protection semiconductor device of the present invention, two thyristors, that is, a power supply terminal-GND terminal protection thyristor and an I / O terminal-GND terminal protection thyristor can be arranged with high area efficiency.

(First embodiment)
FIG. 1 is a circuit diagram showing a configuration of an ESD protection semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, the ESD protection semiconductor device according to the present embodiment includes an I / O terminal-ground terminal protection thyristor 10, a power supply terminal-GND terminal protection thyristor 20, a third PNP transistor 4, and a power supply. It has a terminal 1, an I / O terminal 2, and a GND terminal 3. The I / O terminal 2 is connected to the gate of, for example, a P-type MIS transistor 39 that is an internal element in the internal circuit 30.

  The power supply terminal-GND terminal protection thyristor 20 includes a first NPN transistor 21 and a second PNP transistor 22. The emitter of the first NPN transistor 21 is connected to the GND terminal 3 and grounded. The emitter of the second PNP transistor 22 is connected to the power supply terminal 1, the collector is connected to the base of the first NPN transistor 21, and the base is connected to the collector of the first NPN transistor 21.

  On the other hand, the I / O terminal-GND terminal protection thyristor 10 includes a first PNP transistor 11 and a first NPN transistor 21. The emitter of the first PNP transistor 11 is connected to the I / O terminal 2, the collector is connected to the base of the first NPN transistor 21, and the base is connected to the collector of the first NPN transistor 21.

  The power supply terminal-GND terminal protection thyristor 20 and the I / O terminal-GND terminal protection thyristor 10 share the first NPN transistor 21.

  The emitter of the third PNP transistor 4 is connected to the power supply terminal 1, the collector is connected to the I / O terminal 2, and the base is connected to the collector of the first NPN transistor 21. The third PNP transistor 4 is formed between the power supply terminal 1 and the I / O terminal 2. By setting the emitter-collector punch-through breakdown voltage of the third PNP transistor 4 to a value smaller than the breakdown voltage of the gate oxide film of the P-type MIS transistor 39 in the internal circuit 30, the power supply terminal 1 and the I / O terminal 2 A protective function can be provided between them.

  Although illustration is omitted, a parasitic resistance or a purposely provided resistance may be interposed between the transistors.

  The collector of the first NPN transistor 21, the base of the third PNP transistor 4, the base of the first PNP transistor 11, and the base of the second PNP transistor 22 are connected to one end of the trigger element 5. The other end of the trigger element 5 is connected to the GND terminal 3.

  FIG. 2 is a cross-sectional view showing the structure of a semiconductor device that realizes the circuit shown in FIG. As shown in FIG. 2, in the ESD protection semiconductor device of this embodiment, a P-type well 32 having a P-type impurity concentration higher than that of the semiconductor substrate 31 and an N-type well 33 are arranged in a P-type semiconductor substrate 31. is doing. In the P-type well 32, a P-type impurity diffusion layer 34 and an N-type impurity diffusion layer 35 having a P-type impurity concentration higher than that in the P-type well 32 are formed with the P-type well 32 interposed therebetween.

  In the N-type well 33, a P-type impurity diffusion layer 36 and a P-type impurity diffusion layer 37 are arranged apart from each other with the N-type well 33 interposed therebetween. And the N-type impurity diffusion layer 38 are formed so as to sandwich the N-type well 33 therebetween.

  The GND terminal 3 is connected to the N-type impurity diffusion layer 35, the I / O terminal 2 is connected to the P-type impurity diffusion layer 36, and the power supply terminal 1 is connected to the P-type impurity diffusion layer 37. Yes. One end of the trigger element 5 is connected to the N-type impurity diffusion layer 38. As the trigger element 5, a PNP transistor, an N-type MIS transistor, a P-type MIS transistor, a Zener diode, or the like can be used. Further, instead of the trigger element 5, a trigger circuit composed of a plurality of elements may be used. The other end of the trigger element 5 is connected to the GND terminal 3.

  The N-type impurity diffusion layer 35, the P-type well 32, and the N-type impurity diffusion layer 38 (or the N-type well 33) include the N-type impurity diffusion layer 35 as an emitter, the P-type well 32 as a base, and an N-type impurity. A first NPN transistor 21 having the diffusion layer 38 (or N-type well 33) as a collector is formed. On the other hand, the P-type impurity diffusion layer 36, the N-type well 33, and the P-type impurity diffusion layer 34 (or P-type well 32) have a P-type impurity diffusion layer 36 as an emitter, an N-type well 33 as a base, and a P-type impurity diffusion layer 36. The first PNP transistor 11 having the collector of the impurity diffusion layer 34 (or P-type well 32) as a collector is configured. The P-type impurity diffusion layer 37, the N-type well 33, and the P-type impurity diffusion layer 34 (or the P-type well 32) include the P-type impurity diffusion layer 37 as an emitter, the N-type well 33 as a base, and a P-type impurity diffusion layer 37. The second PNP transistor 22 having the impurity diffusion layer 34 (or the P-type well 32) as a collector is formed. The P-type impurity diffusion layer 36, the N-type well 33, and the P-type impurity diffusion layer 37 include the P-type impurity diffusion layer 37 as an emitter, the N-type well 33 as a base, and the P-type impurity diffusion layer 36 as a collector. The third PNP transistor 4 is configured.

  The I / O terminal-GND protection thyristor 10 includes a P-type impurity diffusion layer 36, an N-type well 33, a P-type well 32, and an N-type impurity diffusion layer 35. This is a thyristor having an anode and an N-type impurity diffusion layer 35 as a cathode. On the other hand, the protective thyristor 20 between the power supply terminal and the GND terminal includes a P-type impurity diffusion layer 37, an N-type well 33, a P-type well 32, and an N-type impurity diffusion layer 35. The P-type impurity diffusion layer 37 is an anode. And a thyristor having an N-type impurity diffusion layer 35 as a cathode.

  In the present embodiment, the N-type well 33 is preferably set to a floating potential. This is to prevent the protective thyristor from being turned on after the power supply during actual use of the integrated circuit is turned on to keep current flowing. The reason is as follows.

  That is, when the voltage at the I / O terminal 2 rises faster than the voltage at the power supply terminal 1 when the power is turned on, the P-type impurity diffusion layer 36 and the N-type well 33 connected to the I / O terminal 2 Attempt to pass current through the PN junction. At this time, if the N-type well 33 is connected to the power supply terminal 1 via a wiring, an element or a circuit, the emitter-base current of the first PNP transistor 11 passes from the power supply terminal 1 via the internal circuit 30. Then, it flows into the GND terminal 3. Therefore, the first PNP transistor 11 enters the operating state, and the I / O terminal-GND terminal protection thyristor 10 enters the operating state. At this time, the first NPN transistor 21 configuring the I / O terminal-GND protection thyristor 10 brings the power supply terminal-GND terminal protection thyristor 20 into an operating state. Therefore, after the power supply is turned on, there arises a problem that the current continuity is kept flowing while the power supply terminal-GND terminal protection thyristor 20 is in the ON state.

  Next, the operation of the semiconductor device of this embodiment will be described. First, the operation when the GND terminal 3 is grounded and positive ESD stress is applied to the I / O terminal 2 will be described with reference to FIGS. In this case, a voltage at which the thyristor is activated (hereinafter referred to as a trigger voltage) is determined by the trigger element 5. When an MIS type integrated circuit is used as the trigger element 5, the trigger voltage is set to a value equal to or lower than the breakdown voltage of the gate insulating film. Here, a case where the gate insulating film withstand voltage is 8V and the trigger voltage is set to 6V is taken as an example.

  The positive ESD current flowing into the I / O terminal 2 flows from the P-type impurity diffusion layer 36 (emitter of the first PNP transistor 11) to the N-type impurity diffusion layer 38 (base of the first PNP transistor 11). Flows into the trigger element 5.

  When the voltage of the trigger element 5 reaches 6 V which is the trigger voltage, the ESD current that has entered from the I / O terminal 2 flows out of the N-type impurity diffusion layer 38 and flows into the GND terminal 3 through the trigger element 5. Since this current is the emitter-base current of the first PNP transistor 11, the first PNP transistor 11 is in an operating state, and a collector current flows. That is, the current entered from the P-type impurity region 36 also flows through the N-type well 33 and the P-type well 32. The current that has entered the P-type well 32 enters the N-type impurity region 35 and flows into the GND terminal. That is, since the collector current of the first PNP transistor 11 becomes the base-emitter current of the first NPN transistor 21, the first NPN transistor 21 operates.

  With the above operation, the I / O terminal-GND terminal protection thyristor 10 including the first PNP transistor 11 and the first NPN transistor 21 operates, and the ESD current that has entered the I / O terminal 2 is applied to the GND terminal 3. Let it drain.

  Next, an operation when the GND terminal 3 is grounded and a positive ESD stress is applied to the power supply terminal 1 will be described with reference to FIGS. Here, the trigger voltage is set to 6V as an example.

  The positive ESD current that has flowed into the power supply terminal 1 flows from the P-type impurity diffusion layer (emitter of the second PNP transistor 22) 37 connected to the power supply terminal 1 to the N-type well 33 (second PNP transistor 22). And the N-type impurity diffusion layer 38 (the base of the second PNP transistor 22) and the trigger element 5.

  When the voltage of the trigger element 5 reaches 6 V which is the trigger voltage, the ESD current that has entered from the I / O terminal 2 flows out of the N-type impurity diffusion layer 38 and flows into the GND terminal 3 through the trigger element 5. Since this current is the emitter-base current of the second PNP transistor 22, the second PNP transistor 22 is in an operating state, and a collector current flows. That is, the current entered from the P-type impurity region 37 also flows through the N-type well 33 and the P-type well 32. The current that has entered the P-type well 32 enters the N-type impurity region 35 and flows into the GND terminal 3. That is, since the collector current of the second PNP transistor 22 becomes the base-emitter current of the first NPN transistor 21, the first NPN transistor 21 operates.

  Through the above operation, the power supply terminal-GND terminal protection thyristor 20 including the second PNP transistor 22 and the first NPN transistor 21 operates, and discharges the ESD current that has entered the power supply terminal 1 to the GND terminal 3. .

  In the present embodiment, the first NPN transistor 21 is shared by the power supply terminal-GND terminal protection thyristor 20 and the I / O terminal-GND terminal protection thyristor 10. As a result, the device area can be reduced as compared with the conventional case where an NPN transistor is formed in each thyristor.

  Further, a P-type impurity diffusion layer 37 that is the anode of the power supply terminal-GND terminal protection thyristor 20 and a P-type impurity diffusion layer 36 that is the anode of the I / O terminal-GND terminal protection thyristor 10 are Two N-type wells 33 are formed. As a result, the device area can be reduced as compared with the conventional case where the P-type impurity diffusion layer is formed in a separate N-type well. As described above, in this embodiment, it is possible to reduce the size of the chip by reducing the device area.

  Moreover, the trigger element is formed outside each thyristor. Thereby, since a transistor other than the MIS type transistor can be used as the trigger element, the range of selection can be expanded.

(Second Embodiment)
The configuration of the ESD protection semiconductor device according to the second embodiment of the present invention will be described below with reference to the drawings. The ESD protection semiconductor device of this embodiment has a circuit configuration similar to that of the ESD protection semiconductor device of the first embodiment, but the layout on the semiconductor substrate is different. FIG. 3 is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment. As shown in FIG. 3, in the ESD protection semiconductor device of this embodiment, an N-type well 42 is formed in a P-type semiconductor substrate 41. A P-type diffusion region 43 is formed in the N-type well 42, and a P-type impurity diffusion layer 44 and an N-type impurity diffusion layer 45 sandwich the P-type diffusion region 43 in the P-type diffusion region 43. Is formed.

  On the other hand, a P-type impurity diffusion layer 46 is formed in the N-type well 42 so as to face the P-type diffusion region 43 with the N-type well 42 interposed therebetween. A P-type impurity diffusion layer 47 is formed in the N-type well 42 at a position facing the P-type impurity diffusion layer 46 with the N-type well 42 interposed therebetween. An N-type impurity diffusion layer 48 is formed in the N-type well 42 so as to face the P-type impurity diffusion layer 47 with the N-type well 42 interposed therebetween.

  The P-type impurity diffusion layer 46 is connected to the I / O terminal 2, the P-type impurity diffusion layer 47 is connected to the power supply terminal 1, and the N-type impurity diffusion layer 45 is connected to the GND terminal 3. The N-type impurity diffusion layer 48 is connected to one end of the trigger element 5.

  The N type impurity diffusion layer 45, the P type diffusion region 43, and the N type well 42 (or N type impurity diffusion layer 48) have the N type impurity diffusion layer 45 as an emitter, the P type diffusion region 43 as a base, and an N type. A first NPN transistor 21 having the well 42 (or N-type impurity diffusion layer 48) as a collector is formed. On the other hand, the P-type impurity diffusion layer 46, the N-type well 42, and the P-type diffusion region 43 (or P-type impurity diffusion layer 44) have the P-type impurity diffusion layer 46 as an emitter, the N-type well 42 as a base, and a P-type A first PNP transistor 11 is formed using the diffusion region 43 (or P-type impurity diffusion layer 44) as a collector. The P-type impurity diffusion layer 47, the N-type well 42, and the P-type well 43 (or P-type impurity diffusion layer 44) have a P-type impurity diffusion layer 47 as an emitter, an N-type well 42 as a base, and a P-type impurity diffusion layer 47. A second PNP transistor 22 having the well 43 (or P-type impurity diffusion layer 44) as a collector is formed. The P-type impurity diffusion layer 46, the N-type well 42, and the P-type impurity diffusion layer 47 include the P-type impurity diffusion layer 47 as an emitter, the N-type well 42 as a base, and the P-type impurity diffusion layer 46 as a collector. The third PNP transistor 4 is configured.

  The I / O terminal-GND terminal protection thyristor 10 includes a P-type impurity diffusion layer 46, an N-type well 42, a P-type diffusion region 43, and an N-type impurity diffusion layer 45, and includes a P-type impurity diffusion layer. A thyristor 46 has an anode and an N-type impurity diffusion layer 45 as a cathode. On the other hand, the power supply terminal-GND terminal protection thyristor 20 includes a P-type impurity diffusion layer 47, an N-type well 42, a P-type diffusion region 43, and an N-type impurity diffusion layer 45. This is a thyristor having an anode and an N-type impurity diffusion layer 45 as a cathode.

  In the present embodiment, the N-type well 42 is preferably set to a floating potential. This is to prevent the protective thyristor from being turned on after the power supply during actual use of the integrated circuit is turned on to keep current flowing. The reason is as follows.

  That is, when the voltage at the I / O terminal 2 rises earlier than the voltage at the power supply terminal 1 when the power is turned on, the P-type impurity diffusion layer 46 and the N-type well 42 connected to the I / O terminal 2 Attempt to pass current through the PN junction. At this time, if the N-type well 42 is connected to the power supply terminal 1 via a wiring, an element or a circuit, the emitter-base current of the first PNP transistor 11 passes from the power supply terminal 1 via the internal circuit 30. Therefore, it flows into the GND terminal 3. Therefore, the first PNP transistor 11 enters the operating state, and the I / O terminal-GND terminal protection thyristor 10 enters the operating state. At this time, the first NPN transistor 21 constituting the I / O terminal-GND terminal protection thyristor 10 brings the power supply terminal-GND terminal protection thyristor 20 into an operating state. Therefore, after the power supply is turned on, there arises a problem that the power supply terminal-GND terminal protection thyristor 20 is kept in the ON state and the current continues to flow.

  Next, the operation of the semiconductor device of this embodiment will be described. First, the operation when the GND terminal 3 is grounded and a positive ESD stress is applied to the I / O terminal 2 will be described with reference to FIGS. In this case, a voltage at which the thyristor is activated (hereinafter referred to as a trigger voltage) is determined by the trigger element 5. When an MIS type integrated circuit is used as the trigger element 5, the trigger voltage is set to a value equal to or lower than the breakdown voltage of the gate insulating film. Here, a case where the gate insulating film withstand voltage is 8V and the trigger voltage is set to 6V is taken as an example.

  The positive ESD current flowing into the I / O terminal is generated from the P-type impurity diffusion layer (emitter of the first PNP transistor 11) 46 to the N-type well (base of the first PNP transistor 11) 42 and the N-type impurity. It flows into the diffusion layer (base of the first PNP transistor 11) 48 and flows into the trigger element 5.

  When the voltage of the trigger element 5 reaches 6 V, which is the trigger voltage, the ESD current that has entered from the I / O terminal 2 flows out of the N-type impurity diffusion layer 48 and flows to the GND terminal 3 via the trigger element 5. Since this current is the emitter-base current of the first PNP transistor 11, the first PNP transistor 11 is in an operating state, and a collector current flows. That is, the current that has entered from the P-type impurity diffusion layer 46 also flows through the paths of the N-type well 42 and the P-type diffusion region 43. The current that has entered the P-type diffusion region 43 enters the N-type impurity diffusion layer 45 and flows into the GND terminal 3. That is, since the collector current of the first PNP transistor 11 becomes the base-emitter current of the first NPN transistor 21, the first NPN transistor 21 operates.

  With the above operation, the I / O terminal-GND terminal protection thyristor 10 including the first PNP transistor 11 and the first NPN transistor 21 operates, and the ESD current that has entered the I / O terminal 2 is applied to the GND terminal 3. Let it drain.

  Next, an operation when the GND terminal 3 is grounded and a positive ESD stress is applied to the power supply terminal 1 will be described with reference to FIGS. Here, the trigger voltage is set to 6V as an example.

  The positive ESD current flowing into the power supply terminal 1 flows from the P-type impurity diffusion layer 47 (emitter of the second PNP transistor 22) connected to the power supply terminal 1 to the N-type well 42 (second PNP transistor 22). ) And the N-type impurity diffusion layer 48 (the collector of the second PNP transistor 22), and flows into the trigger element 5.

  When the trigger element 5 reaches 6 V, which is the trigger voltage, the ESD current that has entered from the power supply terminal 1 flows out of the N-type impurity diffusion layer 48 and flows to the GND terminal 3 through the trigger element 5. Since this current is the emitter-base current of the second PNP transistor 22, the second PNP transistor 22 is in an operating state, and a collector current flows. That is, the current entered from the P-type impurity diffusion layer 47 also flows through the N-type well 42 and the P-type diffusion region 43. The current that has entered the P-type diffusion region 43 enters the N-type impurity diffusion layer 45 and flows into the GND terminal 3. That is, since the collector current of the second PNP transistor 22 becomes the base-emitter current of the first NPN transistor 21, the first NPN transistor 21 operates.

  Through the above operation, the power supply terminal-GND terminal protection thyristor 20 including the first PNP transistor 11 and the first NPN transistor 21 operates, and discharges the ESD current that has entered the power supply terminal 1 to the GND terminal 3. .

  In this embodiment, since the P-type diffusion region 43 is formed in the N-type well 42, the first NPN transistor 21 constituting the thyristor performs a so-called vertical operation (the depth of the collector-emitter current). Therefore, the current gain (amplification factor) (β) can be increased. Thus, by setting the current gain (β) to a large value, the on-resistance of the thyristor is lowered, and the thyristor area can be reduced.

  In particular, in the BiCMIS process, an NPN-based dedicated P-type impurity diffusion layer may be provided. When this P-type impurity diffusion layer dedicated for NPN base is applied to the P-type diffusion region 43, a thyristor protection element having a smaller area can be realized.

  The first NPN transistor 21 is shared by the power supply terminal-GND terminal protection thyristor 20 and the I / O terminal-GND terminal protection thyristor 10. As a result, the device area can be reduced as compared with the conventional case where an NPN transistor is formed in each thyristor.

  Further, a P-type impurity diffusion layer 46 which is an anode of the protective thyristor 20 between the power supply terminal and the GND terminal and a P-type impurity diffusion layer 45 which is an anode of the protective thyristor 10 between the I / O terminal and the GND terminal are Two N-type wells 42 are formed. As a result, the device area can be reduced as compared with the conventional case where the P-type impurity diffusion layer is formed in a separate N-type well. As described above, in this embodiment, it is possible to reduce the size of the chip by reducing the device area.

  Moreover, the trigger element is formed outside each thyristor. Thereby, since a transistor other than the MIS type transistor can be used as the trigger element, the range of selection can be expanded.

(Third embodiment)
FIG. 4 is a circuit diagram showing a configuration of an ESD protection semiconductor device according to the third embodiment of the present invention. As shown in FIG. 4, the ESD protection semiconductor device of this embodiment includes an I / O terminal-GND terminal protection thyristor 10, a power supply terminal-GND terminal protection thyristor 20, a third PNP transistor 4, and a second PNP transistor 4. 4 PNP transistors 14, a power supply terminal 1, an I / O terminal 2, and a GND terminal 3. The I / O terminal 2 is connected to the gate of, for example, a P-type MIS transistor 39 that is an internal element in the internal circuit 30.

  The power supply terminal-GND terminal protection thyristor 20 includes a first NPN transistor 21 and a second PNP transistor 22. The emitter of the first NPN transistor 21 is connected to the GND terminal 3 and grounded. The emitter of the second PNP transistor 22 is connected to the power supply terminal 1, the collector is connected to the base of the first NPN transistor 21, and the base is connected to the collector of the first NPN transistor 21.

  On the other hand, the I / O terminal-GND terminal protection thyristor 10 includes a first PNP transistor 11 and a first NPN transistor 21. The emitter of the first PNP transistor 11 is connected to the I / O terminal 2, the collector is connected to the base of the first NPN transistor 21, and the base is connected to the collector of the first NPN transistor 21.

  The power supply terminal-GND terminal protection thyristor 20 and the I / O terminal-GND terminal protection thyristor 10 share the first NPN transistor 21.

  The collector of the third PNP transistor 4 is connected to the I / O terminal 2, the emitter is connected to the power supply terminal 1, and the base is connected to the collector of the first NPN transistor 21.

  Furthermore, the fourth PNP transistor 14 and the fifth PNP transistor 24 are provided as trigger elements. The emitter of the fourth PNP transistor 14 is connected to the I / O terminal 2, the collector is connected to the base of the first NPN transistor 21, and the base is connected to the collector of the first NPN transistor 21. The emitter of the fifth PNP transistor 24 is connected to the power supply terminal 1, the collector is connected to the base of the first NPN transistor 21, and the base is connected to the collector of the first NPN transistor 21.

  FIG. 5 is a cross-sectional view showing the structure of a semiconductor device that realizes the circuit shown in FIG. As shown in FIG. 5, in the ESD protection semiconductor device of this embodiment, a P-type well 52 having a P-type impurity concentration higher than that of the semiconductor substrate 51 and an N-type well 53 are arranged in a P-type semiconductor substrate 51. is doing. In the P-type well 52, a P-type impurity diffusion layer 54 and an N-type impurity diffusion layer 55 having a P-type impurity concentration higher than that in the P-type well 52 are formed with the P-type well 52 interposed therebetween. .

  In the N-type well 53, P-type impurity diffusion layers 56, 57, and 58 are formed apart from each other with the N-type well 53 interposed therebetween.

  The GND terminal 3 is connected to the N-type impurity diffusion layer 55, the I / O terminal 2 is connected to the P-type impurity diffusion layer 56, and the power supply terminal 1 is connected to the P-type impurity diffusion layer 58. Yes. A resistor or a capacitor 6 is connected to the P-type impurity diffusion layers 54 and 57.

  The N-type impurity diffusion layer 55, the P-type well 52 and the N-type well 53 are the first NPN transistor 21 having the N-type impurity diffusion layer 55 as an emitter, the P-type well 52 as a base, and the N-type well 53 as a collector. Is configured. On the other hand, the P-type impurity diffusion layer 56, the N-type well 53, and the P-type well 52 (or P-type impurity diffusion layer 54) have the P-type impurity diffusion layer 56 as an emitter, the N-type well 53 as a base, and a P-type well. The first PNP transistor 11 is configured with 52 (or P-type impurity diffusion layer 54) as a collector. The P-type impurity diffusion layer 58, the N-type well 53, and the P-type well 52 (or P-type impurity diffusion layer 54) include the P-type impurity diffusion layer 58 as an emitter, the N-type well 53 as a base, and a P-type well. The second PNP transistor 22 having the collector 52 (or P-type impurity diffusion layer 54) as a collector is formed. The P-type impurity diffusion layer 56, the N-type well 53, and the P-type impurity diffusion layer 57 include the P-type impurity diffusion layer 56 as an emitter, the N-type well 53 as a base, and the P-type impurity diffusion layer 57 as a collector. The fourth PNP transistor 14 is configured. The P-type impurity diffusion layer 57, the N-type well 53, and the P-type impurity diffusion layer 58 include the P-type impurity diffusion layer 5 as an emitter, the N-type well 53 as a base, and the P-type impurity diffusion layer 57 as a collector. The fifth PNP transistor 24 is configured.

  The P-type impurity diffusion layers 56 and 58 and the N-type well 53 are third PNPs having the P-type impurity diffusion layer 58 as an emitter, the N-type well 53 as a base, and the P-type impurity diffusion layer 56 as a collector. A transistor 4 (shown in FIG. 4) is formed. However, the circuit symbol of the third PNP transistor 4 is not shown in FIG.

  The I / O terminal-GND protective thyristor 10 includes a P-type impurity diffusion layer 56, an N-type well 53, a P-type well 52, and an N-type impurity diffusion layer 55. This is a thyristor having an anode and an N-type impurity diffusion layer 55 as a cathode. On the other hand, the power supply terminal-GND terminal protection thyristor 20 includes a P-type impurity diffusion layer 58, an N-type well 53, a P-type well 52, and an N-type impurity diffusion layer 55. The P-type impurity diffusion layer 58 is an anode. And a thyristor having an N-type impurity diffusion layer 55 as a cathode.

  Next, the operation of the semiconductor device in the third embodiment will be described. First, the operation when the GND terminal 3 is grounded and a positive ESD stress is applied to the I / O terminal 2 will be described with reference to FIGS. In this case, a voltage at which the thyristor is activated (hereinafter referred to as a trigger voltage) is generated between the P-type impurity diffusion layer 56 (collector of the fourth PNP transistor 14) connected to the I / O terminal 2 and the trigger terminal. This is determined by the punch-through breakdown voltage with respect to a certain P-type impurity diffusion layer 57 (the collector of the fourth PNP transistor 14 and the collector of the fifth PNP transistor 24). In the case of an MIS type integrated circuit, the trigger voltage is usually set to a gate oxide film breakdown voltage or lower. Here, a case where the gate oxide film breakdown voltage is 8V and the trigger voltage is set to 6V is taken as an example.

  When a positive ESD current flows into the I / O terminal 2 and the voltage of the I / O terminal 2 reaches 6 V, which is the trigger voltage, the ESD current that has entered from the I / O terminal 2 becomes a P-type impurity diffusion layer ( The first NPN transistor 21 is operated by flowing out from the trigger electrode 57 and entering the P-type impurity diffusion layer (base of the first NPN transistor 21) 54 and the N-type impurity diffusion layer 55 via the wiring 7. .

  When the first NPN transistor 21 operates, current flows from the emitter (I / O terminal 2) and base of the first PNP transistor 11 to the collector of the first NPN transistor 21, and the first PNP transistor 11 operates. . With the above operation, the I / O terminal-GND terminal protection thyristor 10 including the first PNP transistor 11 and the first NPN transistor 21 operates, and the ESD current that has entered the I / O terminal 2 is applied to the GND terminal 3. Let it drain.

  Next, an operation when the GND terminal 3 is grounded and a positive ESD stress is applied to the power supply terminal 1 will be described with reference to FIGS. 4 and 5. FIG. In this case, the trigger voltage includes a P-type impurity diffusion layer 58 (emitter of the fifth PNP transistor 24) connected to the power supply terminal 1 and a P-type impurity diffusion layer 57 (fourth PNP transistor) serving as the trigger terminal. 14 and the collector of the fifth PNP transistor 24). Here, a case where the punch-through breakdown voltage is set to 6V is taken as an example.

  When a positive ESD current flows into the power supply terminal 1 and the voltage of the power supply terminal 1 reaches 6 V which is the trigger voltage, the ESD current entered from the power supply terminal 1 flows out from the P-type impurity diffusion layer (trigger electrode) 57. The first NPN transistor 21 enters the P-type impurity diffusion layer 54 (base of the first NPN transistor 21) and the N-type impurity diffusion layer 55 (emitter of the first NPN transistor 21) via the wiring 7. To work.

  When the first NPN transistor 21 operates, current flows from the emitter (power supply terminal 1) and base of the fifth PNP transistor 24 to the collector of the first NPN transistor 21, and the fifth PNP transistor 24 operates. Therefore, the power supply terminal-GND terminal protection thyristor 20 including the fifth PNP transistor 24 and the first NPN transistor 21 operates, and discharges the ESD current that has entered the power supply terminal 1 to the GND terminal 3.

  In the present embodiment, the N-type well 53 is preferably set to a floating potential. This is to prevent the protective thyristor from being turned on after the power supply during actual use of the integrated circuit is turned on to keep current flowing. The reason for this will be described below.

  That is, when the voltage at the I / O terminal 2 rises earlier than the voltage at the power supply terminal 1 when the power is turned on, the P-type impurity diffusion layer 56 and the N-type well 53 connected to the I / O terminal 2 Attempt to pass current through the PN junction. At this time, if the N-type well 53 is connected to the power supply terminal 1 via a wiring, an element or a circuit, the emitter-base current of the first PNP transistor 11 passes from the power supply terminal 1 via the internal circuit. Therefore, it flows into the GND terminal 3. Therefore, the first PNP transistor 11 enters the operating state, and the I / O terminal-GND terminal protection thyristor 10 enters the operating state. At this time, the first NPN transistor 21 configuring the I / O terminal-GND terminal protection thyristor 10 brings the power supply terminal-GND terminal thyristor 20 into an operating state. Therefore, after the power supply is turned on, there arises a problem that the current continuity is kept flowing while the power supply terminal-GND terminal protection thyristor 20 is in the ON state.

  In the present embodiment, the fourth PNP transistor 14 and the fifth PNP transistor 24 are provided as trigger elements, and the P-type impurity diffusion layer 56 that is the emitter of the fourth PNP transistor 14 is used as the base of the first PNP transistor 11. And share with. Further, the P-type impurity diffusion layer 58 that is the emitter of the fifth PNP transistor 24 is shared with the emitter of the second PNP transistor 22. Further, the fourth PNP transistor 14 and the fifth PNP transistor 24 share the P-type impurity diffusion layer 57 as a collector. As a result, the device area can be reduced as compared with the conventional case where separate impurity diffusion layers are formed for each element.

  Further, in this embodiment, the I / O terminal-GND terminal protection thyristor 10 and the power supply terminal-GND terminal protection thyristor 20 share the first NPN transistor 21. As a result, the device area can be reduced as compared with the conventional case where an NPN transistor is formed in each thyristor.

  Further, a P-type impurity diffusion layer 58 serving as an anode of the power supply terminal-GND terminal protection thyristor 20 and a P-type impurity diffusion layer 56 serving as an anode of the I / O terminal-GND terminal protection thyristor 10 are combined with each other. Two N-type wells 53 are formed. As a result, the device area can be reduced as compared with the conventional case where the P-type impurity diffusion layer is formed in a separate N-type well.

  As described above, in this embodiment, it is possible to reduce the size of the chip by reducing the device area.

(Fourth embodiment)
The configuration of the ESD protection semiconductor device according to the fourth embodiment of the present invention will be described below with reference to the drawings. The ESD protection semiconductor device of this embodiment has a circuit configuration similar to that of the ESD protection semiconductor device of the third embodiment, but the layout on the semiconductor substrate is different. FIG. 6 is a cross-sectional view showing the structure of the ESD protection semiconductor device according to the fourth embodiment.

  As shown in FIG. 6, in the ESD protection semiconductor device of this embodiment, an N-type well 62 is disposed in a P-type semiconductor substrate 61. A P-type diffusion region 63 is disposed in the N-type well 62, and a P-type impurity diffusion layer 64 and an N-type impurity diffusion layer 65 sandwich the P-type diffusion region 63 in the P-type diffusion region 63. Has been placed. P-type impurity diffusion layers 66, 67, 68 are sequentially arranged in the N-type well 62 adjacent to the P-type diffusion region 63 so as to be separated from each other.

  The N-type impurity diffusion layer 65 is connected to the GND terminal 3. The P-type impurity diffusion layer 66 is connected to the I / O terminal 2. A power supply terminal 1 is connected to the P-type impurity diffusion layer 68. A resistor or a capacitor 6 is connected to the P-type impurity diffusion layers 63 and 67.

  The N-type impurity diffusion layer 65, the P-type diffusion region 63, and the N-type well 62 are first NPNs having the N-type impurity diffusion layer 65 as an emitter, the P-type diffusion region 63 as a base, and the N-type well 62 as a collector. A transistor 21 is configured. On the other hand, the P-type impurity diffusion layer 66, the N-type well 62, and the P-type diffusion region 63 (or P-type impurity diffusion layer 64) have the P-type impurity diffusion layer 66 as an emitter, the N-type well 62 as a base, The first PNP transistor 11 is configured using the type diffusion region 63 (or P-type impurity diffusion layer 64) as a collector. The P-type impurity diffusion layer 68, the N-type well 62, and the P-type diffusion region 63 (or the P-type impurity diffusion layer 64) have the P-type impurity diffusion layer 68 as an emitter, the N-type well 62 as a base, A second PNP transistor 22 having the collector of the type diffusion region 63 (or P-type impurity diffusion layer 64) is formed. The P-type impurity diffusion layer 66, the N-type well 62, and the P-type impurity diffusion layer 67 include the P-type impurity diffusion layer 66 as an emitter, the N-type well 62 as a base, and the P-type impurity diffusion layer 67 as a collector. The fourth PNP transistor 14 is configured. The P-type impurity diffusion layer 67, the N-type well 62, and the P-type impurity diffusion layer 68 include the P-type impurity diffusion layer 68 as an emitter, the N-type well 62 as a base, and the P-type impurity diffusion layer 67 as a collector. The fifth PNP transistor 24 is configured.

  The P-type impurity diffusion layers 66 and 68 and the N-type well 62 are third PNPs having the P-type impurity diffusion layer 68 as an emitter, the N-type well 62 as a base, and the P-type impurity diffusion layer 66 as a collector. A transistor 4 (shown in FIG. 4) is formed. However, the circuit symbol of the third PNP transistor 4 is not shown in FIG.

  The I / O terminal-GND protection thyristor 10 includes a P-type impurity diffusion layer 66, an N-type well 62, a P-type diffusion region 63, and an N-type impurity diffusion layer 65. Is a thyristor having an N-type impurity diffusion layer 65 as a cathode. On the other hand, the power supply terminal-GND terminal protection thyristor 20 includes a P-type impurity diffusion layer 68, an N-type well 62, a P-type diffusion region 63, and an N-type impurity diffusion layer 65. This is a thyristor having an anode and an N-type impurity diffusion layer 65 as a cathode.

  Note that the operation of the semiconductor device in this embodiment is the same as that described in the third embodiment, and a description thereof will be omitted.

  In the present embodiment, the P-type diffusion region 63 is disposed in the N-type well 62, whereas in the structure of the third embodiment, the N-type well 53 and the P-type well 52 are disposed adjacent to each other. is doing. In other words, in the present embodiment, the thyristors 10 and 20 are constituted by so-called vertical transistors (transistors having a large current component in the depth direction in the emitter-collector current), whereas in the third embodiment. The thyristors 10 and 20 are so-called lateral transistors (transistors having a large amount of current component in the lateral direction in the emitter-collector current). When a vertical transistor is formed in this way, the current gain (β) can be set larger than in the case where a horizontal transistor is formed. Therefore, since the current capability can be increased and the on-resistance can be reduced, a thyristor protection element with a small area can be realized.

  In particular, in the BiCMOS process, a P-type diffusion layer dedicated to NPN base may be provided. When this P-type diffusion layer dedicated to NPN base is applied to the P-type diffusion region 63, a thyristor protection element with a smaller area can be realized.

  In the present embodiment, the I / O terminal-GND terminal protection thyristor 10 and the power supply terminal-GND terminal protection thyristor 20 share the first NPN transistor 21. As a result, the device area can be reduced as compared with the conventional case where an NPN transistor is formed in each thyristor.

  Further, a P-type impurity diffusion layer 68 that is the anode of the power supply terminal-GND terminal protection thyristor 20 and a P-type impurity diffusion layer 66 that is the anode of the I / O terminal-GND terminal protection thyristor 10 are Two N-type wells 62 are formed. As a result, the device area can be reduced as compared with the conventional case where the P-type impurity diffusion layer is formed in a separate N-type well.

  In the present embodiment, the fourth PNP transistor 14 and the fifth PNP transistor 24 are provided as trigger elements, and the P-type impurity diffusion layer 66 that is the emitter of the fourth PNP transistor 14 is provided as the first PNP transistor 11. Share with the base of. Further, the P-type impurity diffusion layer 58 that is the emitter of the fifth PNP transistor 24 is shared with the emitter of the second PNP transistor 22. Further, the fourth PNP transistor 14 and the fifth PNP transistor 24 share the P-type impurity diffusion layer 67 as a collector. As a result, the device area can be reduced as compared with the conventional case where separate impurity diffusion layers are formed for each element. As described above, in this embodiment, it is possible to reduce the size of the chip by reducing the device area.

  As described above, the present invention is useful for forming an ESD protection circuit with good area efficiency.

1 is a circuit diagram showing a configuration of an ESD protection semiconductor device according to a first embodiment of the present invention. It is sectional drawing which shows the structure of the semiconductor device which implement | achieves the circuit shown in FIG. It is sectional drawing which shows the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the ESD protection semiconductor device which concerns on the 3rd Embodiment of this invention. FIG. 5 is a cross-sectional view showing a structure of a semiconductor device that realizes the circuit shown in FIG. 4. It is sectional drawing which shows the structure of the ESD protection semiconductor device which concerns on 4th Embodiment. It is a circuit diagram which shows the structure of the conventional ESD protection semiconductor device. It is sectional drawing which shows the structure of the semiconductor device which comprises the circuit shown in FIG.

Explanation of symbols

1 Power supply terminal
2 I / O terminal
3 GND terminal
4 Third PNP transistor
5 Trigger element
6 capacity
7 Wiring
10 I / O terminal-GND terminal protection thyristor
11 First PNP transistor
14 Fourth PNP transistor
20 Power supply terminal-GND terminal protection thyristor
21 First NPN transistor
22 Second PNP transistor
24 Fifth PNP transistor
30 Internal circuit
31 Semiconductor substrate
32 P type well
33 N-type well
34-38 Impurity diffusion layer
39 P-type MIS transistor
41 Semiconductor substrate
42 N-type well
43 P-type diffusion region
44-48 impurity diffusion layer
51 Semiconductor substrate
52 P-type well
53 N-type well
54-58 Impurity diffusion layer
61 Semiconductor substrate
62 N-type well
63 P-type diffusion region
63-68 Impurity diffusion layer

Claims (9)

A semiconductor device having a protection circuit,
The protection circuit is
An input / output terminal-GND terminal protective thyristor having a first PNP transistor having an emitter connected to the input / output terminal;
A power supply terminal-GND terminal protection thyristor having a second PNP transistor having a base connected to a base of the first PNP transistor and an emitter connected to a power supply terminal; the base of the first PNP transistor; A first NPN transistor having a collector connected to the base of the second PNP transistor, an emitter connected to the GND terminal, and a base connected to the collector of the first PNP transistor and the collector of the second PNP transistor. Prepared,
The semiconductor device, wherein the first NPN transistor is shared by the protection thyristor between the input / output terminal and the GND terminal and the protection thyristor between the power supply terminal and the GND terminal. The semiconductor device according to claim 1,
A semiconductor region; a P-type well formed in the semiconductor region; an N-type well formed in the semiconductor region; a first P-type impurity diffusion layer formed in the P-type well; An N-type impurity diffusion layer, and a second P-type impurity diffusion layer, a third P-type impurity diffusion layer, and a second N-type impurity diffusion layer formed in the N-type well,
The first PNP transistor includes the P-type well including the second P-type impurity diffusion layer, the N-type well, and the first P-type impurity diffusion layer,
The second PNP transistor includes the P-type well including the third P-type impurity diffusion layer, the N-type well, and the first P-type impurity diffusion layer,
The first NPN transistor is a semiconductor device including the N-type well including the first N-type impurity diffusion layer, the P-type well, and the second N-type impurity diffusion layer. The semiconductor device according to claim 2,
A semiconductor device, further comprising: a third PNP transistor having the second P-type impurity diffusion layer as a collector, the third P-type impurity diffusion layer as an emitter, and the N-type well as a base. The semiconductor device according to claim 1,
A semiconductor region, an N-type well formed in the semiconductor region, a P-type diffusion region formed in the N-type well, and a first P-type impurity diffusion layer formed in the P-type diffusion region And a first N-type impurity diffusion layer, and a second P-type impurity diffusion layer, a third P-type impurity diffusion layer, and a second N-type impurity diffusion layer formed in the N-type well,
The first PNP transistor includes the P-type well including the second P-type impurity diffusion layer, the N-type well, and the first P-type impurity diffusion layer,
The second PNP transistor includes the P-type well including the third P-type impurity diffusion layer, the N-type well, and the first P-type impurity diffusion layer,
The first NPN transistor is a semiconductor device including the N-type well including the first N-type impurity diffusion layer, the P-type well, and the second N-type impurity diffusion layer. The semiconductor device according to claim 4,
A semiconductor device, further comprising: a third PNP transistor having the second P-type impurity diffusion layer as a collector, the third P-type impurity diffusion layer as an emitter, and the N-type well as a base. A semiconductor device according to any one of claims 1 to 5,
A semiconductor device further comprising a trigger element connected to a base of the first PNP transistor and a collector of the first NPN transistor. The semiconductor device according to claim 1,
A fourth PNP transistor having an emitter connected to the input / output terminal, a collector connected to a collector of the first PNP transistor, and a base connected to a base of the second PNP transistor;
A semiconductor device further comprising: a fifth PNP transistor having an emitter connected to the power supply terminal, a collector connected to a collector of the fourth PNP transistor, and a base connected to a collector of the first NPN transistor. The semiconductor device according to claim 7,
A semiconductor region; a P-type well formed in the semiconductor region; an N-type well formed in the semiconductor region; a first P-type impurity diffusion layer formed in the P-type well; An N-type impurity diffusion layer, and a second P-type impurity diffusion layer, a third P-type impurity diffusion layer, and a fourth P-type impurity diffusion layer formed in the N-type well,
The first PNP transistor includes the P-type well including the second P-type impurity diffusion layer, the N-type well, and the first P-type impurity diffusion layer,
The second PNP transistor includes the P-type well including the fourth P-type impurity diffusion layer, the N-type well, and the first P-type impurity diffusion layer,
The first NPN transistor includes the first N-type impurity diffusion layer, the P-type well, and the N-type well.
The fourth PNP transistor includes the second P-type impurity diffusion layer, the N-type well, and the third P-type impurity diffusion layer.
The fifth PNP transistor is a semiconductor device including the third P-type impurity diffusion layer, the N-type well, and the fourth P-type impurity diffusion layer. The semiconductor device according to claim 7,
A semiconductor region, an N-type well formed in the semiconductor region, a P-type diffusion region formed in the N-type well, and a first P-type impurity diffusion layer formed in the P-type diffusion region And a first N-type impurity diffusion layer, a second P-type impurity diffusion layer, a third P-type impurity diffusion layer, and a fourth P-type impurity diffusion layer formed in the N-type well,
The first PNP transistor includes the P-type diffusion region including the second P-type impurity diffusion layer, the N-type well, and the first P-type impurity diffusion layer.
The second PNP transistor includes the P-type diffusion region including the fourth impurity diffusion layer, the N-type well, and the first P-type impurity diffusion layer.
The first NPN transistor includes the first N-type impurity diffusion layer, the P-type well, and the N-type well.
The fourth PNP transistor includes the second P-type impurity diffusion layer, the N-type well, and the third P-type impurity diffusion layer.
The fifth PNP transistor is a semiconductor device including the third P-type impurity diffusion layer, the N-type well, and the fourth P-type impurity diffusion layer.

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