JP2007115888A - Semiconductor device - Google Patents

Abstract

A semiconductor device that reduces the switching time of turn-on and turn-off of a gate drive transistor and further makes the drive of a transistor cell uniform.
A first gate lead electrode 1a provided on the outer periphery of an actual operation region 4a, a first gate metal wiring 1b electrically connected on the first gate lead electrode 1a, an actual operation region 4a, Electrical connection between the trench gate electrode 3 formed in the non-operation region 4c, the second gate extraction electrode 2a formed on the trench gate electrode 3 in the non-operation region 4c, and the second gate extraction electrode 2a And the second gate lead electrode 2a is electrically connected on the trench gate electrode 3, and the first gate lead electrode 1a and the second gate lead electrode 2b are electrically connected. The first gate metal wiring 1b and the second gate metal wiring 2b are spatially separated by the first gap 5a, and the first gate metal wiring 1b is partially separated by the second gap 5b. And spatial separation.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a transistor having a trench gate electrode.

  In a transistor having a trench gate electrode and driven in a high frequency band of several hundred kilohertz or more, reduction of switching loss is desired. In order to reduce the switching loss, the resistance parasitic inside the transistor when the transistor is turned on, that is, the ON resistance is lowered, the capacitance between the gate and the source and between the gate and the drain is reduced, A reduction in gate resistance is required.

  Of the conventional semiconductor devices, the trench type n-channel MOSFET shown in FIGS. 15 and 16 will be described as an example.

  FIG. 15 is a plan view of a semiconductor chip of a trench type n-channel MOSFET. The actual operation region 4a is formed by a plurality of transistor cells 4b formed using a known technique, and the trench gate electrode 3 is formed in a stripe shape. The source electrode 6 is formed on the actual operation region 4a and is electrically connected to the source region and the body region constituting the transistor cell 4b. In FIG. 15, the source region and the body region constituting the transistor cell 4b are omitted.

  The first gate lead electrode 1a electrically connected to the trench gate electrode 3 is formed on the outer periphery of the actual operation region 4a, and the first gate metal wiring 1b is formed on the first gate lead electrode 1a. It is formed.

FIG. 16 is a cross-sectional view of the trench type n-channel MOSFET semiconductor chip shown in FIG. An n ⁻ type epitaxial layer 12 is formed on the n ⁺ type silicon substrate 11 and serves as a drain region. A p ⁻ type region 13 is formed above n ⁻ type epitaxial layer 12 using a technique such as ion implantation. A trench groove is provided so as to penetrate the p ⁻ type region 13 and reach the middle of the n ⁻ type epitaxial layer 12, an oxide film 16 is formed by heat treatment or the like, and a polysilicon layer is deposited on the oxide film 16. Thus, the trench gate electrode 3 is formed. The polysilicon layer used for the trench gate electrode 3 is given a metallic property by diffusing a high-concentration n-type or p-type impurity. An insulating layer 17 is formed on the trench gate electrode 3.

Between adjacent trench gate electrodes 3, an n ⁺ region 14 serving as a source region and a p ⁺ / n ⁺ type region 15 serving as a body / source contact region are formed. The p ⁺ / n ⁺ type region 15 has a shallow source contact layer n ⁺ region on the surface. A transistor cell 4b is formed by a combination of the n ⁺ region 14 and the p ⁺ / n ⁺ type region 15, and a plurality of transistor cells 4b integrated together is an actual operation region 4a. The p ⁺ / n ⁺ type region 15 may be only the p ⁺ type region.

The trench gate electrode 3 is electrically connected to the first gate lead electrode. A first gate metal wiring 1b is formed on the first gate lead electrode 1a. First metal gate line 1b and gate pad electrode 1c are electrically connected. The gate drive is performed by applying a voltage to the gate pad electrode 1c, whereby the transistor operates.
JP 2005-11965 A JP 2004-31386 A JP 2004-55812 A

  In the case of the structure in which the trench gate electrode 3 is formed in a stripe shape as in the prior art, the gate-source and the gate-drain are compared with the structure in which the trench gate electrode 3 is formed in a mesh shape (for example, see Patent Document 1). The parasitic capacitance can be reduced, and the channel region per unit gate length is large.

  However, when the on-resistance is reduced, the length of one trench gate electrode 3 formed in a stripe shape increases, so that the gate resistance Rg of one trench gate electrode 3 has this value. Increase proportionally. Even if the gate resistance Rg of the trench gate electrode 3 formed in a macroscopically striped shape is small, the gate resistance Rg seen microscopically, that is, the gate resistance Rg per one trench gate electrode 3 is large. Overall transistor switching time is increased. For example, when used in a DC / DC conversion switching circuit operating in a band of several hundred kilohertz, there arises a problem that the switching efficiency obtained by dividing the output power by the input power is deteriorated.

  In particular, when the process is miniaturized to the submicron level, the cross-sectional area of the trench gate electrode 3 is reduced, so that the switching efficiency is further deteriorated.

  As a technique for solving this, for example, as in the configuration described in Patent Document 2, a second gate lead electrode is provided on the trench gate electrode 3 to reduce the gate Rg per trench gate electrode 3. Although there is a technique to take in impurities in the actual operation region into the oxide film formed under the second gate lead electrode, it occurs under the second gate lead electrode and in other regions. The gate threshold value is biased, and uniform gate driving cannot be performed.

  Accordingly, an object of the present invention is to provide a semiconductor device in which the gate resistance Rg of one trench gate electrode formed in a stripe shape is reduced, the switching speed is improved, and the gate drive is not biased. To do.

  In order to achieve the above object, a semiconductor device according to the present invention includes a transistor cell formed in a chip region of a semiconductor substrate and having a trench gate electrode having a stripe-like trench structure, and the transistor is included in the chip region. An actual operation region in which a plurality of cells are arranged; a non-operation region in which the transistor cell is not disposed; the non-operation region formed inside the actual operation region; and the outer periphery of the actual operation region. A first gate lead electrode; a first gate metal line formed on the first gate lead electrode and electrically connected to the first gate lead electrode; the actual operating region; The trench gate electrode penetrating each of the operation regions and electrically insulated from the actual operation region and the non-operation region via an oxide film; A second gate extraction electrode formed on the non-operating region via an oxide film, intersecting the trench gate electrode and electrically connected to the trench gate electrode; and the second gate extraction electrode A second metal gate wiring formed on and electrically connected to the second gate lead electrode, and electrically connecting the first gate lead electrode and the second gate lead electrode. , A first gap formed by spatially separating the first gate metal wiring and the second gate metal wiring is formed between the first gate metal wiring and the second gate metal wiring. One or more points are provided between them.

  The present invention can provide a semiconductor device in which the switching speed is improved and the gate drive is not biased by reducing the gate resistance Rg of one trench gate electrode formed in a stripe shape.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of a semiconductor device according to the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a plan view of a semiconductor chip provided with a semiconductor device according to Embodiment 1 of the present invention.

  In FIG. 1, a first gate extraction electrode 1a made of a material mainly made of polysilicon is formed on the outer periphery of the actual operation region 4a. A first gate metal interconnection 1b made of a metal material such as aluminum is formed on the first gate lead electrode 1a.

  The trench gate electrode 3 is formed so as to penetrate the actual operation region 4a and the non-operation region 4c that does not actually operate, and the terminal portion of the trench gate electrode 3 is electrically connected to the first gate extraction electrode 1a.

  The second gate extraction electrode 2a is formed on the non-operation region 4c via an oxide film, and is formed on the trench gate electrode 3 so as to be electrically connected to the trench gate electrode 3. The second gate lead electrode 2a and the trench gate electrode 3 are formed of the same material as the first gate lead electrode 1a.

  A first gap 5a is provided at a location closest to the gate pad electrode 3 in a region where the first gate metal wiring 1b and the second gate metal wiring 2b intersect. In the second gate lead electrode 2a formed under the first gap 5a, the resistance value of the second gate lead electrode 2a in a region limited to the area under the first gap 5a has a value of 1Ω or more. In addition, a first gap 5a is provided.

  A second gap 5b is provided in the first gate metal wiring 1b located in the vicinity of the trench gate electrode 3 and closest to the gate pad electrode 1c. In the first gate extraction electrode 1a formed under the second gap 5b, the resistance value of the first gate extraction electrode 1a in the region limited to the area under the second gap 5b has a value of 1Ω or more. In addition, a second gap 5b is provided.

  The resistance value of the second gate lead electrode 2a in the region limited below the first gap 5a is the same as the resistance value of the first gate lead electrode 1a in the region limited below the second gap 5b. Formed to have a value.

  The source electrode 6 is formed on the actual operation region 4a. The source electrode 6 is divided by the second gate metal wiring 2b, and a plurality of divided source electrodes 6 are formed.

  As described above, since the second gate lead electrode 2a and the second gate metal wiring 2b are formed on the trench gate electrode 3, the gate resistance Rg per one trench gate electrode 3 is reduced. Therefore, the switching time of the transistor is shortened. Furthermore, the second gate metal wiring 2b allows almost the same switching time for every trench gate electrode 3 in the actual operation region 4a, so that the gate drive can be made uniform and the switching time can be further shortened. it can.

  Further, by providing the first gap 5a and the second gap 5b, when a surge is input to the gate pad electrode 1c, the arrival time of the surge to the trench gate electrode 3 is reduced to the first gap 5a and the second gap 5b. In addition to being delayed by the second gap 5b, the surge reaches all the trench gate electrodes 3 uniformly, so that local concentration of the surge on the trench gate electrode 3 can be prevented. In particular, surge concentration on the trench gate electrode 3 located immediately below the second gate metal wiring 2b can be prevented.

  Furthermore, the parasitic capacitance between the gate and the source can be reduced by dividing the source region 6 into a plurality of parts. Therefore, switching time is reduced. In addition, since the unevenness is not formed below the source electrode 6, the source electrode 6 can be formed flat.

  2 is a perspective view seen from the front left side with respect to the area A in FIG. 1, and FIG. 3 is a perspective view seen from the front right side with respect to the area A in FIG. 2 and 3, the source electrode is omitted.

An n ⁻ type epitaxial layer 12 is formed on the n ⁺ type silicon substrate 11 and serves as a drain region. A p ⁻ type region 13 is formed above the n ⁻ type epitaxial layer 12 by ion implantation or the like. A trench groove is provided so as to penetrate the p ⁻ type region 13 and reach the middle of the n ⁻ type epitaxial layer 12, and an oxide film 16 is formed by heat treatment or the like. A polysilicon layer is deposited on the oxide film 16. Thus, the trench gate electrode 3 is formed.

At this time, the second gate lead electrode 2a is also formed on the trench gate electrode 3 and the p ⁻ type region 13 at the same time. Between type region 13, the oxide film 16 is formed, the second gate lead-out electrode 2a and the p ^{- -} second gate extraction electrode 2a and the p type region 13 are electrically insulated.

High-concentration n-type or p-type impurities are diffused in the polysilicon layer used for the second gate extraction electrode 2a and the trench gate electrode 3 to have metallic properties. An insulating layer 17 is formed on the trench gate electrode 3. Between the adjacent trench gate electrodes 3, an n ⁺ region 14 serving as a source region and a p ⁺ type region 15 serving as a body region are formed. A transistor cell 4b is formed by a combination of the n ⁺ region 14 and the p ⁺ type region 15, and a plurality of transistor cells 4b are integrated into the actual operation region 4a. A second gate metal wiring 2b is formed on the second gate lead electrode 2a.

  FIG. 4 is a schematic diagram showing a cross section taken along line BB in FIG. 1 and corresponds to a partial region around the first gap 5a. The first gate lead electrode 1a and the second gate lead electrode 1b are electrically connected, and the first gate metal line 1b and the second gate metal line 2b are electrically insulated.

  FIG. 5 is a schematic view showing a cross section taken along the line CC of FIG. 1, and the trench gate electrode 3 is electrically connected to the second gate lead electrode 2a. A second gate metal wiring 2b is formed on the second gate lead electrode 2a. An insulating layer 17 is formed on the trench gate electrode 3, the source electrode 6 is formed on the insulating layer 17, and the trench gate electrode 3 and the source electrode 6 are electrically insulated.

For example, a trench type n-channel having a semiconductor chip area of 1 mm ² , Ciss which is the sum of the parasitic capacitance between the gate and source and between the gate and drain is 500 pF, and the length of one trench gate is 600 μm. In the MOSFET, the turn-on time in the prior art is 10 ns, and the turn-off time is 90 ns.

  Here, when this embodiment is carried out by providing the second gate extraction electrode 2a and the second gate metal wiring 2b so that the length of one trench gate is 150 μm, the turn-on time is 6 ns, The turn-off time was 20 ns. That is, by implementing this embodiment, the turn-on time can be shortened by about 40% and the turn-off time can be shortened by about 80%. In addition, even when a surge voltage based on a human body model is applied to the gate pad electrode 1c, it has the same characteristics as the conventional one, and the surge resistance can be maintained.

  The semiconductor device according to Embodiment 1 of the present invention has been described above, but the present invention is not limited to this embodiment.

For example, in the embodiment 1, p ⁺ -type region 15 serving as the n ⁺ -type region 14 and the body region to be a source region is formed alternately between the trench gate electrode 3, the n ⁺ -type region 14 trench gate electrode 3, and the p ⁺ -type region 15 may be formed at the center of the adjacent trench gate electrode 3.

(Embodiment 2)
FIG. 6 is a plan view of a semiconductor chip provided with a semiconductor device according to Embodiment 2 of the present invention. In the following description of the second embodiment, the same elements as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

  In FIG. 6, the source electrode 6 is not divided and is all formed on the same plane, and the second gate metal wiring 2 b is formed only on the second gate extraction electrode 2 a where the source electrode 6 does not straddle. Is formed.

  FIG. 7 is a schematic view showing a cross section taken along the line DD of FIG. When the source electrode 6 straddles the trench gate electrode 3 and the second gate lead electrode 2a, an insulating film 17 is formed and is electrically insulated from the trench gate electrode 3 and the second gate lead electrode 2a.

  In the semiconductor chip of the second embodiment, the source electrode 6 is not divided and forms a single plane. Therefore, when assembling the semiconductor chip into the pad electrode of the package, wire bonding or the like is performed in the region of the arbitrary source electrode 6. It can be carried out. Therefore, the bonding process in the assembly process is simplified.

  In the above embodiment, the source electrode 6 is formed by forming the insulating film 17 on the second gate lead electrode 2a. However, a gap is formed between the second gate lead electrode 2a and the source electrode 6. It may be provided. In this case, the parasitic capacitance between the gate and the source can be reduced. Therefore, the switching time is reduced.

  Further, the second gate metal wiring 2 b is formed so as to cover a part of the insulating film 17, but may not be covered as long as it is electrically insulated from the source electrode 6.

(Embodiment 3)
FIG. 8 is a plan view of a semiconductor chip provided with a semiconductor device according to Embodiment 3 of the present invention. In the following description of the third embodiment, the same elements as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

  In FIG. 8, like the configuration of the second embodiment, the source electrodes 6 are all formed on the same plane without being divided. The difference from the second embodiment is that the second gate metal wiring 2b formed on the second gate extraction electrode 2a is divided on the second gate extraction electrode 2a, and the divided region The source electrode 6 is formed on the second gate extraction electrode 2a located at a position via an insulating film.

  In the semiconductor chip according to the third embodiment, even when wire bonding is performed at an arbitrary position of the source electrode 6, an increase in parasitic resistance between the entire region of the source electrode 6 and the wire bonding position 20 is suppressed. Can do. For example, when wire bonding is performed at the wire bonding position 20 located on the source electrode 6 in the second and third embodiments, the source electrode 6 is replaced with a distributed constant circuit, so that the third embodiment is the second embodiment. The resistance value can be made smaller.

  Further, since the entire transistor structure is symmetrical with respect to the center of the chip except for the region of the gate pad electrode 1c, gate driving can be performed more uniformly than in the second embodiment.

(Embodiment 4)
FIG. 9 is a plan view of a semiconductor chip provided with a semiconductor device according to Embodiment 4 of the present invention. In the following description of the fourth embodiment, the same elements as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

  In FIG. 9, the source electrode 6 is formed on the second gate extraction electrode 2a and the second gate metal wiring 2b via an insulating film.

  FIG. 10 is a schematic diagram showing a cross section taken along the line E-E of FIG. 9, and the source electrode 6 is formed on the second gate wiring metal 2 b through the insulating film 17.

  FIG. 11 is a schematic diagram showing a cross section taken along the line FF of FIG. 9, and the source electrode 6 is formed on the second gate lead-out electrode 2a and the second gate metal wiring 2b with the insulating film 17 interposed therebetween. The

  In the semiconductor chip of Embodiment 4, the second gate metal wiring 2b can be formed on the second gate extraction electrode 2a in all necessary regions. Further, when wire bonding is performed on the source electrode 6, it is possible to reduce the risk of electrical contact with the second gate metal wiring 2b. Therefore, the management of the bonding process in the assembly process becomes easy.

  In the embodiment, the source electrode 6 is formed by forming the insulating film 17 on the second gate extraction electrode 2a and the second gate metal wiring 2b, but the second gate extraction electrode 2a and An air gap may be provided between the second gate metal wiring 2 b and the source electrode 6. In this case, the parasitic capacitance between the gate and the source can be reduced. Therefore, switching time is reduced.

(Embodiment 5)
FIG. 12 is a plan view of a conductor chip provided with a semiconductor device according to Embodiment 5 of the present invention. In the following description of the fifth embodiment, the same elements as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

  In FIG. 12, the source electrode 6 is formed on the second gate lead electrode 2a and the second gate metal wiring 2b via an insulating film, and the second gate lead electrode 2a and the second gate metal A region where the source electrode 6 is not formed is provided in a part of the wiring 2b.

  FIG. 13 is a schematic diagram showing a cross section taken along the line G-G of FIG. Regions that are not formed are provided.

  In the semiconductor chip of the fifth embodiment, a space is provided in a part of the second gate extraction electrode 2a and the second gate metal wiring 2b, and a region where the source electrode 6 is not formed is provided. The parasitic capacitance between the gate and the source can be reduced. Therefore, switching time is reduced.

  In the fifth embodiment, in the fourth embodiment, when a gap cannot be provided instead of the insulating layer 17 between the second gate extraction electrode 2a and the second gate metal wiring 2b and the source electrode 6, It is effective in reducing the parasitic capacitance between the gate and the source.

(Embodiment 6)
FIG. 14 is a plan view of a semiconductor chip provided with a semiconductor device according to Embodiment 6 of the present invention. In the following description of the sixth embodiment, the same elements as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

  In FIG. 14, the first gate metal wiring 1b formed on the first gate lead electrode 1a is formed in a closed curve, and the second gap 5b in FIG. 1 is not formed. In this case, as shown in FIG. 14, the first gap 5a is provided in a region where the first gate metal wiring 1a and the second gate metal wiring 2a intersect.

  The sixth embodiment can be carried out if the resistance value between the first gate metal wiring 1b and the end of the trench gate electrode 3 is 1Ω or more. In this case, all the second gate metal wirings 1b need to be electrically insulated from the first gate metal wiring 1b through the first gap 5a. This is to prevent the surge from reaching the trench gate electrode 3 evenly when the surge is input to the gate pad electrode 1c, and to prevent local concentration of the surge on the trench gate electrode 3. can do.

  It is possible to implement a combination of parts of the configurations of the first to sixth embodiments. In the first to sixth embodiments, the trench type n-channel MOSFET is mainly used as an example, but the present invention is also applied to other transistors and semiconductor elements.

  The present invention can be applied to a semiconductor device including a transistor having a trench gate electrode, and is particularly effective for a semiconductor device having a transistor driven at a high frequency of several hundred kilohertz or more. The present invention can also be applied to a transistor and a semiconductor element that need to improve switching speed, such as a channel MOSFET and an insulated gate bipolar transistor (IGBT).

The top view of the semiconductor chip provided with the semiconductor device in Embodiment 1 of this invention The perspective view seen from the front left side toward the A area | region of FIG. The perspective view seen from the front right side toward the A area | region of FIG. Schematic diagram showing a cross section of line BB in FIG. Schematic diagram showing a cross section along line CC in FIG. The top view of the semiconductor chip provided with the semiconductor device in Embodiment 2 of this invention Schematic diagram showing a cross section taken along the line DD of FIG. The top view of the semiconductor chip provided with the semiconductor device in Embodiment 3 of this invention The top view of the semiconductor chip provided with the semiconductor device in Embodiment 4 of this invention FIG. 9 is a schematic diagram showing a cross section taken along line EE of FIG. FIG. 9 is a schematic diagram showing a cross section taken along line FF in FIG. The top view of the conductor chip provided with the semiconductor device in Embodiment 5 of this invention FIG. 12 is a schematic diagram showing a cross section taken along line GG in FIG. The top view of the semiconductor chip provided with the semiconductor device in Embodiment 6 of this invention Plan view of semiconductor chip of conventional trench type n-channel MOSFET FF sectional view of the semiconductor chip of the trench type n-channel MOSFET of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a 1st gate extraction electrode 1b 1st gate metal wiring 1c Gate pad electrode 2a 2nd gate extraction electrode 2b 2nd gate metal wiring 3 Trench gate electrode 4a Actual operation area | region 4b Transistor cell 4c Non-operation area | region 5a 1st Gap (between the first gate metal interconnect and the second gate metal interconnect)
5b Second gap (between the first gate metal lines)
6 source electrode 11 n ⁺ type silicon substrate 12 n ⁻ type epitaxial layer 13 p ⁻ type region 14 n ⁺ type region 15 p ⁺ type region 16 oxide film 17 insulating layer 20 wire bonding position

Claims (11)

A transistor cell having a trench gate electrode formed in a chip region of a semiconductor substrate and having a stripe-like trench structure,
In the chip region, there are an actual operation region in which a plurality of the transistor cells are disposed, and a non-operation region in which the transistor cells are not disposed,
The non-operation area formed inside the actual operation area;
A first gate extraction electrode formed on the outer periphery of the actual operation region;
A first gate metal line formed on the first gate lead electrode and electrically connected to the first gate lead electrode;
The trench gate electrode penetrating the actual operation region and the non-operation region, respectively, and the actual operation region and the non-operation region are electrically insulated via an oxide film;
A second gate lead electrode formed on the non-operating region via an oxide film, further intersecting the trench gate electrode and electrically connected to the trench gate electrode;
A second gate metal line formed on the second gate lead electrode and electrically connected to the second gate lead electrode;
Electrically connecting the first gate lead electrode and the second gate lead electrode;
A first gap formed by spatially separating the first gate metal wiring and the second gate metal wiring is formed between the first gate metal wiring and the second gate metal wiring. One or more semiconductor devices are provided.   2. The semiconductor device according to claim 1, wherein each of the trench gate electrode, the first gate lead electrode, and the second gate lead electrode is made of a material mainly composed of polysilicon. .   3. The semiconductor device according to claim 1, wherein at least one of the second gate lead electrode and the second gate metal wiring is formed in the chip region.   Among the second gate lead electrodes formed in the first gap portion, the resistance value of the second gate lead electrode formed under the first gap is 1Ω or more, The semiconductor device according to claim 1, wherein the first gap is formed. The first gate metal wiring does not form a closed curve, and is formed to be divided into a plurality of portions with a second gap,
5. The second gap is formed so that a resistance value of the first gate lead electrode formed under the second gap is 1Ω or more. A semiconductor device according to claim 1.   The source electrode is formed on the actual operation region, and is formed on the trench gate electrode and the second gate lead electrode through an insulating film, and is further formed by providing a gap. The semiconductor device according to claim 1.   The source electrode is formed of a plane composed of a combination of a straight line, a curved line, a circular corner, or a non-circular corner, and has a total of four or more of the circular corner or the non-circular corner, and the second gate metal. 7. The wiring according to claim 1, wherein the wiring is electrically insulated from the wiring and further divided into two or more regions by the second gate lead electrode or the second gate metal wiring. The semiconductor device described.   The source electrode is formed of a plane composed of a combination of a straight line, a curved line, a circular corner, or a non-circular corner, and has a total of four or more of the circular corner or the non-circular corner, and the second gate metal. 7. The wiring according to claim 1, wherein the wiring is electrically insulated from the wiring and is not divided into two or more regions by the second gate lead-out electrode or the second gate metal wiring. The semiconductor device described.   9. The semiconductor device according to claim 7, wherein the second gate metal wiring is divided into two or more regions by the source electrode and formed on the second gate lead electrode. .   The source electrode is formed on the second metal wiring through an insulating film or formed by providing a gap, and has a plurality of layers with the second metal wiring. The semiconductor device according to claim 7 or 8.   The semiconductor device according to claim 10, wherein a region that is not partially formed on the second gate metal wiring is provided in the source electrode.

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