JP2007115789A - Stacked semiconductor device and method for manufacturing stacked semiconductor device - Google Patents

Abstract

An object of the present invention is to improve joint stability, strength, and reliability during three-dimensional mounting.
When two semiconductor devices are stacked, an opening 18 serving as a formation region of an intermediate electrode 26 that electrically connects both to an insulating layer between the semiconductor devices is formed in consideration of warpage of the semiconductor device. At this time, the semiconductor device to be stacked is warped by adjusting the opening diameter of the opening 18 so as to be the same volume as the volume of the external electrode serving as the intermediate electrode provided in the semiconductor device 10b on the upper side. However, since the intermediate electrode 26 that reliably connects the two semiconductor devices can be formed without changing the volume of the external electrode, which is the intermediate electrode material of the semiconductor device 10b, according to the warping, the intermediate electrode 26 can be formed. Bonding yield, bonding strength and reliability during dimension mounting can be improved.
[Selection] Figure 1

Description

  The present invention relates to a stacked semiconductor device in which a plurality of semiconductor devices are mounted in one package, and a method for manufacturing the stacked semiconductor device.

In recent years, in order to reduce the size, performance, and speed of electronic devices, semiconductor devices are also required to be smaller, thinner, faster, more terminals, and higher-density mounting. . In particular, a stacked semiconductor device (package on package) in which a semiconductor device is three-dimensionally mounted for the purpose of reducing the mounting area and achieving high-density mounting has attracted attention (see, for example, Patent Document 1 and Patent Document 2).
JP 2004-281919 A JP 2004-289002 A

  However, the semiconductor device has a considerable amount of warpage due to the difference / unbalance of the linear expansion coefficients of the constituent materials. When a semiconductor device is three-dimensionally mounted, due to the occurrence of warping, in the method of stacking semiconductor devices via metal electrodes such as solder balls, the interval between the semiconductor devices is greatly widened, and the occurrence of defective bonding (open failure) There was a problem that joint strength and joint reliability deteriorated.

  Therefore, the present invention provides a stacked semiconductor device and a method for manufacturing the stacked semiconductor device capable of improving the junction yield, the bond strength, and the reliability at the time of three-dimensional mounting in consideration of the warp of the semiconductor device. For the purpose.

  To achieve the above object, according to the first aspect of the present invention, there is provided a method for manufacturing a stacked semiconductor device, wherein one or more electronic components are mounted on a first carrier substrate having a first external electrode and a stacked bonding land. Forming a first semiconductor device and a second semiconductor device having one or more electronic components mounted on a second carrier substrate having a second external electrode formed of a solder material by melting the second external electrode A method of manufacturing a stacked semiconductor device in which an intermediate electrode and the stacked junction land are electrically connected and stacked, wherein the junction land of the first semiconductor device is exposed and the formation position of the intermediate electrode is set to the second position. A step of attaching an insulating layer having an opening that is open by the volume of the external electrode on the electronic component mounting surface of the first semiconductor device; and the second external electrode and the opening are aligned to align the first 1 semiconductor Placing the second semiconductor device on the device; melting the second external electrode by heating and filling the opening to form the intermediate electrode; A step of electrically connecting the first semiconductor device and the second semiconductor device in accordance with an interval between the first semiconductor device and the second semiconductor device when the opening is formed. The height of the opening is adjusted so that an intermediate electrode can electrically connect the first semiconductor device and the second semiconductor device, and the volume of the opening is the same as the volume of the second external electrode The opening diameter of the opening is adjusted to correspond to the height of the opening.

  According to a second aspect of the present invention, there is provided a method for manufacturing a stacked semiconductor device, comprising: a first semiconductor device having one or more electronic components mounted on a first carrier substrate having a first external electrode and a stacked bonding land; and a solder material. An intermediate electrode formed by melting the second external electrode and a second semiconductor device mounting one or more electronic components on a second carrier substrate having the second external electrode are electrically connected to the lamination land. A method of manufacturing a stacked type semiconductor device that is connected and stacked, the step of attaching an insulating layer on the electronic component mounting surface of the first semiconductor device, and a bonding land of the first semiconductor device on the insulating layer Forming an opening that exposes and opens the intermediate electrode by a volume of the second external electrode; and aligns the second external electrode and the opening on the first semiconductor device. Second half A step of placing a body device and a step of melting the second external electrode by heating and filling the opening to form the intermediate electrode and electrically connecting the intermediate electrode and the laminating land When the opening is formed, the intermediate electrode corresponds to the distance between the first semiconductor device and the second semiconductor device due to warpage of the first semiconductor device and the second semiconductor device. The height of the opening is adjusted so that the semiconductor device and the second semiconductor device can be electrically connected, and the volume of the opening is the same as the volume of the second external electrode. The opening diameter of the opening is adjusted in accordance with the height of the portion.

  The method for manufacturing a stacked semiconductor device according to claim 3 is the method for manufacturing a stacked semiconductor device according to claim 1 or 2, wherein each junction of the opening with the second external electrode is provided. Further, a taper corresponding to the warp of the first semiconductor device and the second semiconductor device is provided so that the second external electrode can be stably contacted.

  The method for manufacturing a stacked semiconductor device according to claim 4 is the method for manufacturing a stacked semiconductor device according to claim 1, wherein the first semiconductor device or the second semiconductor device is used. When mounting the electronic components, the electronic components are stacked and mounted.

  The method for manufacturing a stacked semiconductor device according to claim 5 is the method for manufacturing a stacked semiconductor device according to claim 1, wherein the first semiconductor device or the second semiconductor device is used. In mounting the electronic component, the electronic component is mounted in parallel.

  A method for manufacturing a stacked semiconductor device according to claim 6 is the method for manufacturing a stacked semiconductor device according to claim 1, claim 2, claim 3, claim 4, or claim 5. At least one of the parts is a semiconductor element.

  The method for manufacturing a stacked semiconductor device according to claim 7 is a method for manufacturing a stacked semiconductor device according to claim 1, claim 2, claim 3, claim 4, claim 5, or claim 6. The electronic component mounted on the first semiconductor device is resin-sealed.

  The method for manufacturing a stacked semiconductor device according to claim 8 is a stacked semiconductor according to claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, or claim 7. In the device manufacturing method, the electronic component mounted on the second semiconductor device is resin-sealed.

  The stacked semiconductor device according to claim 9, wherein the first semiconductor device has one or more electronic components mounted on a first carrier substrate having a first external electrode and a first stacked junction land, and the first semiconductor device includes: An insulating layer formed on the electronic component mounting surface; and a second carrier substrate that is stacked on the insulating layer facing the first semiconductor device with the insulating layer interposed therebetween, and includes the second stacking junction land. A height corresponding to a distance between the first semiconductor device and the second semiconductor device due to warpage of the first semiconductor device and the second semiconductor device; and a second semiconductor device on which one or more electronic components are mounted. An intermediate electrode for adjusting and electrically connecting the first lamination junction land and the second lamination junction land, and a region for forming the intermediate electrode formed in the insulating layer in the same shape as the intermediate electrode With opening Characterized in that the volume of all of the intermediate electrode corresponds to the diameter the height of the intermediate electrode to be the same.

  The stacked semiconductor device according to claim 10 is the stacked semiconductor device according to claim 9, wherein the height of the intermediate electrode gradually changes from the center of the first semiconductor device toward the outer periphery. To do.

  The stacked semiconductor device according to claim 11 is the stacked semiconductor device according to claim 9, wherein the diameter of the intermediate electrode gradually changes from the center of the first semiconductor device toward the outer periphery. .

  The stacked semiconductor device according to claim 12 is the stacked semiconductor device according to any one of claim 9, claim 10, or claim 11, wherein the opening is adjacent to the second semiconductor device for each opening. A taper corresponding to the warp of the first semiconductor device and the second semiconductor device is provided.

  The stacked semiconductor device according to claim 13 is the stacked semiconductor device according to claim 12, wherein the taper angle of the taper gradually increases as the distance between the first semiconductor device and the second semiconductor device increases. It is characterized by becoming larger.

  The stacked semiconductor device according to claim 14 is the stacked semiconductor device according to any one of claim 9, claim 10, claim 11, claim 12, or claim 13, wherein the first semiconductor device or the second semiconductor device. The electronic components are stacked and mounted on a semiconductor device.

  The stacked semiconductor device according to claim 15 is the stacked semiconductor device according to any one of claim 9, claim 10, claim 11, claim 12, or claim 13, wherein the first semiconductor device or the second semiconductor device. The electronic component is mounted in parallel on a semiconductor device.

  A stacked semiconductor device according to claim 16 is the stacked semiconductor device according to claim 9, claim 10, claim 11, claim 12, claim 13, claim 14, or claim 15, At least one of the electronic components is a semiconductor element.

  The stacked semiconductor device according to claim 17 is a stacked semiconductor device according to any one of claim 9, claim 10, claim 11, claim 12, claim 13, claim 14, claim 15, or claim 16. In the semiconductor device, the electronic component mounted on the first semiconductor device is resin-sealed.

  The stacked semiconductor device according to claim 18 is any one of claim 9, claim 10, claim 11, claim 12, claim 13, claim 14, claim 15, claim 16, or claim 17. The stacked semiconductor device described above is characterized in that the electronic component mounted on the second semiconductor device is resin-sealed.

  As described above, it is possible to improve the bonding yield, the bonding strength and the reliability at the time of three-dimensional mounting while considering the warp of the semiconductor device.

  As described above, when two semiconductor devices are stacked, an opening serving as a formation region of an intermediate electrode that electrically connects the two to the insulating layer between the semiconductor devices is formed in consideration of the warp of the semiconductor device. At this time, by adjusting the opening diameter of the opening so as to be the same as the volume of the external electrode serving as the intermediate electrode included in the upper semiconductor device, even if the semiconductor device to be stacked is warped, It is possible to form an intermediate electrode that reliably connects both semiconductor devices without changing the volume of the external electrode, which is an intermediate electrode material of the semiconductor device to be warped, in accordance with the warpage. Yield, joint strength and reliability can be improved.

Hereinafter, a semiconductor device according to each embodiment of the present invention will be described with reference to FIGS. 1, 2, 3, 4, and 5.
FIG. 1 is a cross-sectional view of a stacked semiconductor device according to the first embodiment of the present invention.

  In FIG. 1, in the first embodiment, a semiconductor device 10a and a semiconductor device 10b are joined (laminated) via an intermediate electrode 26 for electrically connecting the semiconductor devices. The lower semiconductor device 10 a includes a first carrier substrate 11, and first bonding lands 14 and external electrode lands 15 are formed on both surfaces of the first carrier substrate 11. Although not shown, internal metal wiring for obtaining electrical characteristics is formed inside the first carrier substrate 11. The first semiconductor element 12 is flip-chip mounted on the surface of the first carrier substrate 11 where the first bonding land 14 is formed. For example, flip chip mounting is performed by NCF bonding using NCF (Nonconductive Film) for the first adhesive layer 13. In addition, external electrodes 16 are formed on the opposite external electrode lands 15, respectively, and play a role of bonding to a final electronic device mounting board.

  The upper semiconductor device 10 b includes a second carrier substrate 20, and wiring lands 24 and second junction lands 25 are formed on both surfaces of the second carrier substrate 20. Although not shown, internal metal wiring for obtaining electrical characteristics is formed in the second carrier substrate 20. The second semiconductor element 21 is bonded to the surface of the second carrier substrate 20 on which the wiring lands 24 are formed via the second adhesive layer 22. Further, the second semiconductor element 21 and the wiring lands 24 are connected. Are electrically connected by a thin metal wire 23 (wire bond bonding). Further, external electrodes serving as intermediate electrodes 26 are formed on the second junction lands 25 on the opposite side. As an external electrode of the semiconductor device 10b, a solder material is used, which is a solder ball or a solder bump. A second sealing resin 29 is formed so as to cover the entire second carrier substrate including the second semiconductor element 21.

  Further, an insulating layer 17 is provided between the semiconductor device 10a and the semiconductor device 10b. The insulating layer 17 has an opening 18 in the same arrangement as the intermediate electrode 26. The intermediate electrode 26 is formed by melting the external electrode of the semiconductor device 10b in the opening 18 of the insulating layer. The first bonding land 14 and the second bonding land 25 are bonded to each other via the bonding portion 28. As the first carrier substrate 11 and the second carrier substrate 20, for example, a double-sided substrate, a multilayer wiring substrate, a build-up substrate, an ALIVH substrate, a tape substrate, a film substrate, or the like can be used. Glass epoxy resin, BT resin, aramid, polyimide resin, ceramic, or the like can be used.

  Here, the opening 18 of the insulating layer is formed from the center of the first carrier substrate 11 in accordance with the distance between the semiconductor device 10a and the semiconductor device 10b in each opening due to warpage of the semiconductor device 10a and the semiconductor device 10b. In order to match the volume of the intermediate electrode 26 formed by melting the external electrode of the semiconductor device 10b formed so as to have a predetermined volume by changing the height to the outer peripheral portion, the opening diameter is adjusted, and the semiconductor The opening diameter and the thickness of the insulating layer corresponding to the distance between the device 10a and the semiconductor device 10b are secured. For example, when the semiconductor device 10a is warped upward and the semiconductor device 10b is not warped, the diameter of the opening 18 of the insulating layer is made smaller toward the outer peripheral portion than the center portion, and the thickness of the insulating layer 17 is reduced. Make it thicker. On the contrary, when the semiconductor device 10a warps to the opposite side, the opening 18 of the insulating layer is made larger toward the outer peripheral part than the center part, and the thickness of the insulating layer 17 is made thinner.

  Thus, by adjusting the height and opening diameter of the opening formed in the insulating layer while keeping the volume of the opening constant so as to be the height of the intermediate electrode corresponding to the interval between the semiconductor devices, the semiconductor device 10a and the non-uniformity of the distance between the first carrier substrate 11 and the second carrier substrate 20 caused by the warp of the semiconductor device 10b. Stable bonding (stacking) via the intermediate electrode 26 is possible, and the bonding yield, bonding strength and reliability at the time of three-dimensional mounting can be improved in consideration of the warp of the semiconductor device.

  FIG. 2 is a cross-sectional view of a stacked semiconductor device according to the second embodiment of the present invention. In FIG. 2, the basic configuration is the same as that of the first embodiment, but a tapered portion 19 is further provided in the opening 18 of the insulating layer on the second bonding portion 28 side. The tapered portion 19 of the insulating layer also has an outer periphery from the center portion of the first carrier substrate 11 so that each external electrode of the semiconductor device 10b stably contacts the opening in accordance with the warp of the semiconductor device 10a and the semiconductor device 10b. The taper angle is changed over the part. For example, when the semiconductor device 10a is warped upward and the semiconductor device 10b is not warped, the angle of the tapered portion 19 of the insulating layer is increased toward the outer peripheral portion rather than the central portion. On the contrary, when the semiconductor device 10a warps to the opposite side, the angle of the tapered portion 19 of the insulating layer is made smaller toward the outer peripheral portion than the central portion.

  Thus, by providing a taper at the joint portion 28, when the semiconductor device 10b is mounted on the semiconductor device 10a, the penetration of the tip of the external terminal 36 into the opening 18 is deepened, and the taper angle is changed. By adjusting the depth, the depth of penetration of the external terminal 36 into the opening 18 is adjusted to correspond to the warp of the two semiconductor devices, and the opening of the insulating layer is not affected by the warp of the two semiconductor devices. Thus, the external electrode of the semiconductor device 10b to be the intermediate electrode 26 can be contacted (mounted) more stably and uniformly.

  In the above-described embodiment, the first semiconductor element 12 is flip-chip mounted and the second semiconductor element 21 is wire-bonded. However, there is no problem even if either bonding method is adopted. In addition to NCF bonding, NCP (Nonconductive Paste), ACF (Anisotropic Conductive Film), or ACP (Anisotropic Conductive Paste) may be used for flip chip mounting. Further, although only one of the first semiconductor element 12 and the second semiconductor element 21 is illustrated, a plurality of semiconductor elements may be stacked in the vertical direction or joined in parallel. At this time, not only the semiconductor element but also a small electronic component may be joined together with the semiconductor element, and the combination of electronic components to be mounted is arbitrary. Further, the second sealing resin 29 may be omitted if there is no problem in reliability with respect to the sealing resin. Conversely, as shown in the cross-sectional view of the stacked semiconductor device according to the third embodiment of the present invention shown in FIG. 3, the first sealing resin 30 is formed on the first semiconductor element to the extent that the region of the intermediate electrode 26 is not affected. May be formed.

  In the above embodiment, the semiconductor device 10b is not warped, and the case where the semiconductor device 10a warps upward and the case where it warps downward has been described as an example. It is possible to adjust the opening diameter and height so that the volume of the opening is constant, even in all combinations of warping states, including the occurrence of warping, and to cope with the spacing between semiconductor elements. is there.

  Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a process sectional view showing the method for manufacturing the stacked semiconductor device according to the first embodiment of the invention. FIG. 5 is a process sectional view showing the method for manufacturing the stacked semiconductor device according to the second embodiment of the present invention.

  As shown in FIG. 4A, first, the assembled semiconductor device 10a is prepared. Although not shown, a semiconductor device 10b that has been assembled in the same manner is also prepared (the manufacturing method of the semiconductor device 10a and the semiconductor device 10b is omitted because it is a known technique). At this time, the warpage of both semiconductor devices is measured. In addition, the volume of the external terminal of the semiconductor device 10b is formed to be a predetermined size.

  Next, as shown in FIG. 4B, the opening 18 of the insulating layer and the first junction land 14 are aligned with the side on which the first semiconductor device 12 of the semiconductor device 10a is mounted, and the insulation is performed. Layer 17 is formed. For example, the insulating layer 17 in which the thickness of the insulating layer and the opening 18 are controlled in consideration of the warpage of the semiconductor devices 10a and 10b is pasted, or the insulating layer 17 whose thickness is adjusted is pasted on the semiconductor device 10a. After that, the opening 18 may be formed in the opening 18 by laser processing or photolithography. Here, the height of the opening 18 in the insulating layer is adjusted to match the warp of the semiconductor device 10a and the semiconductor device 10b from the central part to the outer peripheral part of the first carrier substrate 11 and the semiconductor device 10a due to the warp of the semiconductor device 10b. Only the difference between the intervals of the semiconductor device 10b is changed. However, since the external electrode 36 of the semiconductor substrate 10b is melted in the opening 18 to form the intermediate electrode 26, the volume of the intermediate electrode 26 and the volume of the opening 18 of the insulating layer must all be the same. The opening diameter is changed in accordance with the warpage of 10a and 10b. For example, when the semiconductor device 10a is warped upward and the semiconductor device 10b is not warped, the diameter of the opening 18 of the insulating layer is made smaller toward the outer peripheral portion than the center portion, and the thickness of the insulating layer 17 is reduced. Make it thicker. On the contrary, when the semiconductor device 10a warps to the opposite side, the opening 18 of the insulating layer is made larger toward the outer peripheral part than the center part, and the thickness of the insulating layer 17 is made thinner.

Next, as shown in FIG. 4C, the semiconductor device 10 b is mounted on the semiconductor device 10 a having the insulating layer 17 by aligning the external terminal 36 and the opening 18 of the insulating layer.
At this time, in order to remove impurities on the surface of the external terminal 36 and the surface of the first bonding land 14, a surface active agent 31 such as flux is applied or pin-transferred to the opening 18 of the insulating layer. Similarly, a surface active agent such as flux is applied or transferred to the surface of the external terminal 36. Then, in a state where the two semiconductor devices 10a and 10b are mounted, they are heated with a desired temperature profile by a high-temperature heating device such as a reflow furnace. When the external terminal 36 is heated to a melting point or higher by this heating and melted, the external terminal 36 flows into the opening 18 of the insulating layer by the capillary phenomenon to form the intermediate electrode 26. And after cooling to normal temperature, as shown in FIG.4 (d), the semiconductor device 10b is joined (laminated | stacked) on the semiconductor device 10a via the intermediate electrode 26. FIG.

  Although the manufacturing method is the same in FIG. 5, since the tapered portion 19 is provided in the opening of the insulating layer, when the semiconductor device 10b is mounted on the semiconductor device 10a in FIG. The depth of penetration of the external terminal 36 into the opening 18 and the taper angle are changed to adjust the depth of penetration of the external terminal 36 into the opening 18 in accordance with the warpage of the two semiconductor devices. In addition, the external terminals 36 can be contacted (mounted) more stably and uniformly on the opening 18 of the insulating layer without being affected by the warpage of the two semiconductor devices.

  In the above manufacturing method, the semiconductor device 10b is not warped, and the case where the semiconductor device 10a is warped upward and the case where it warps downward has been described as an example. Similarly, in all combinations of warpage states, including the occurrence of warpage, the opening diameter and height of the opening having a constant volume, and further the taper can be adjusted according to the interval between the semiconductor devices. Is possible.

  Further, although the external terminal 36 is formed in advance on the semiconductor device 10b and the insulating layer 17 is formed on the semiconductor device 10a, the opposite configuration may be employed. That is, the external terminal 36 may be formed in advance on the first junction land 14 of the semiconductor device 10a, and the insulating layer 17 may be formed on the semiconductor device 10b.

  In this way, by adjusting the opening diameter and height of the opening, which is a region for forming the intermediate electrode of the insulating layer, according to the interval between the semiconductor devices, the semiconductor device 10a and the semiconductor device 10a and Due to the non-uniformity of the distance between the first carrier substrate 11 and the second carrier substrate 20 caused by the warp of the semiconductor device 10b, the opening diameter of the opening 18 of the insulating layer and the insulating layer 17 are also provided at the location where the distance is maximum. By controlling the thickness of the intermediate electrode 26 by adjusting the height of the formed intermediate electrode 26 to the distance between the first carrier substrate 11 and the second carrier substrate 20, the stable bonding (lamination) via the intermediate electrode 26 is performed. In addition, it is possible to improve the bonding strength and reliability, and to improve the bonding yield and bonding strength and reliability at the time of three-dimensional mounting in consideration of the warpage of the semiconductor device. Kill.

  The present invention can improve the junction yield, the junction strength and the reliability at the time of three-dimensional mounting in consideration of the warpage of the semiconductor device, and a stacked semiconductor device and a stacked layer in which a plurality of semiconductor devices are mounted in one package This is useful in a method for manufacturing a type semiconductor device.

Sectional drawing of the laminated semiconductor device which concerns on 1st Embodiment of this invention. Sectional drawing of the laminated semiconductor device which concerns on 2nd Embodiment of this invention. Sectional drawing of the laminated semiconductor device which concerns on 3rd Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the laminated semiconductor device which concerns on 1st Embodiment in this invention. Sectional drawing which shows the manufacturing method of the laminated semiconductor device which concerns on 2nd Embodiment in this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10a Semiconductor device 10b Semiconductor device 11 1st carrier substrate 12 1st semiconductor element 13 1st adhesion layer 14 1st junction land 15 External electrode land 16 External electrode 17 Insulating layer 18 Opening part 19 Tapered part 20 2nd carrier substrate 21 2nd Semiconductor element 22 2nd adhesion layer 23 Metal fine wire 24 Wiring land 25 2nd joining land 26 Intermediate electrode 27 Joining part 28 Joining part 29 2nd sealing resin 30 1st sealing resin 31 Surface active agent

Claims (18)

A first semiconductor device having one or more electronic components mounted on a first carrier substrate having a first external electrode and a laminating bonding land, and a second carrier substrate having a second external electrode formed of a solder material A manufacturing method of a stacked semiconductor device in which a second semiconductor device on which a plurality of electronic components are mounted is stacked by electrically connecting an intermediate electrode formed by melting the second external electrode and the bonding land for stacking. And
An insulating layer having an opening that exposes the junction land of the first semiconductor device and opens the formation position of the intermediate electrode by the volume of the second external electrode is provided on the electronic component mounting surface of the first semiconductor device. A process of attaching to,
Placing the second semiconductor device on the first semiconductor device by aligning the second external electrode and the opening; and
Forming the intermediate electrode by melting the second external electrode by heating and filling the opening, and electrically connecting the intermediate electrode and the laminating land, and forming the opening At this time, the intermediate electrode corresponds to an interval between the first semiconductor device and the second semiconductor device due to warpage of the first semiconductor device and the second semiconductor device, and the intermediate electrode is connected to the first semiconductor device and the second semiconductor device. The height of the opening is adjusted so as to be electrically connected, and the volume of the opening corresponds to the height of the opening so that the volume of the opening is the same as the volume of the second external electrode. A method of manufacturing a stacked semiconductor device, wherein the opening diameter of the opening is adjusted. A first semiconductor device having one or more electronic components mounted on a first carrier substrate having a first external electrode and a laminating bonding land, and a second carrier substrate having a second external electrode formed of a solder material A manufacturing method of a stacked semiconductor device in which a second semiconductor device on which a plurality of electronic components are mounted is stacked by electrically connecting an intermediate electrode formed by melting the second external electrode and the bonding land for stacking. And
Bonding an insulating layer on the electronic component mounting surface of the first semiconductor device;
Exposing a junction land of the first semiconductor device in the insulating layer to form an opening that opens a formation position of the intermediate electrode by a volume of the second external electrode;
Placing the second semiconductor device on the first semiconductor device by aligning the second external electrode and the opening; and
Forming the intermediate electrode by melting the second external electrode by heating and filling the opening, and electrically connecting the intermediate electrode and the laminating land, and forming the opening At this time, the intermediate electrode corresponds to an interval between the first semiconductor device and the second semiconductor device due to warpage of the first semiconductor device and the second semiconductor device, and the intermediate electrode is connected to the first semiconductor device and the second semiconductor device. The height of the opening is adjusted so as to be electrically connected, and the volume of the opening corresponds to the height of the opening so that the volume of the opening is the same as the volume of the second external electrode. A method of manufacturing a stacked semiconductor device, wherein the opening diameter of the opening is adjusted.   A taper corresponding to the warp of the first semiconductor device and the second semiconductor device is provided so that the second external electrode can stably come into contact with each joint portion of the opening with the second external electrode. A method for manufacturing a stacked semiconductor device according to claim 1.   4. The electronic component according to claim 1, wherein the electronic component is stacked and mounted when the electronic component is mounted on the first semiconductor device or the second semiconductor device. 5. A method of manufacturing a stacked semiconductor device.   4. The stack according to claim 1, wherein the electronic components are mounted in parallel when the electronic components are mounted on the first semiconductor device or the second semiconductor device. 5. Type semiconductor device manufacturing method.   The method for manufacturing a stacked semiconductor device according to claim 1, wherein at least one of the electronic components is a semiconductor element.   7. The electronic component mounted on the first semiconductor device is resin-sealed, and the electronic component according to claim 1 or 2, or 3 or 4, or 5 or 6. Manufacturing method of the stacked type semiconductor device.   The electronic component mounted on the second semiconductor device is resin-sealed, wherein the electronic component according to claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, or claim 7. A method for manufacturing a stacked semiconductor device according to any one of the above. A first semiconductor device having one or more electronic components mounted on a first carrier substrate having a first external electrode and a first lamination junction land;
An insulating layer formed on the electronic component mounting surface of the first semiconductor device;
A second semiconductor device having one or more electronic components mounted on a second carrier substrate that is stacked on the insulating layer facing the first semiconductor device across the insulating layer and includes the second bonding junction land; ,
The height is adjusted in accordance with the distance between the first semiconductor device and the second semiconductor device due to warpage of the first semiconductor device and the second semiconductor device, and the first stacked junction land and the second stacked layer are adjusted. An intermediate electrode for electrically connecting the junction land,
The insulating layer has an opening that is formed in the same shape as the intermediate electrode and serves as a formation region of the intermediate electrode, and the diameter of the intermediate electrode is increased so that the volume of all the intermediate electrodes is the same. A stacked semiconductor device characterized by correspondingly.   The stacked semiconductor device according to claim 9, wherein a height of the intermediate electrode gradually changes from a center of the first semiconductor device toward an outer peripheral portion.   10. The stacked semiconductor device according to claim 9, wherein the diameter of the intermediate electrode gradually changes from the center of the first semiconductor device toward the outer periphery.   The taper corresponding to the curvature of said 1st semiconductor device and said 2nd semiconductor device is provided in the edge part adjacent to said 2nd semiconductor device for every said opening part, Claim 10 or Claim 10 or Claims characterized by the above-mentioned. The stacked semiconductor device according to any one of 11.   13. The stacked semiconductor device according to claim 12, wherein the taper angle of the taper gradually increases as the distance between the first semiconductor device and the second semiconductor device increases.   14. The electronic component according to claim 9, claim 11, claim 11, claim 12, or claim 13, wherein the electronic component is stacked and mounted on the first semiconductor device or the second semiconductor device. Stacked semiconductor device.   The stack according to claim 9, claim 10, claim 11, claim 12, or claim 13, wherein the electronic component is mounted in parallel on the first semiconductor device or the second semiconductor device. Type semiconductor device.   16. At least one of the electronic components is a semiconductor element, according to any one of claims 9 or 10, or 11 or 12, or 13 or 14 or 15. Stacked semiconductor device.   The electronic component mounted on the first semiconductor device is resin-sealed, wherein the electronic component is sealed with resin. 15 or 10 or 11 or 12 or 13 or 14 or 15 or 15. The stacked semiconductor device according to claim 16.   The electronic component mounted on the second semiconductor device is resin-sealed, wherein the electronic component is sealed with resin. 15 or 10 or 11 or 12 or 13 or 14 or 15 or 15. The stacked semiconductor device according to claim 16.

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