JP2007033748A - Display control circuit - Google Patents

Abstract

An object of the present invention is to provide a display control circuit in which a display position is stably determined.
A display control circuit according to the present invention includes an oscillation circuit that generates a clock signal having a predetermined frequency, a display start position and a display end based on an externally input synchronization signal and a clock signal from the oscillation circuit. A timing control circuit that outputs a display period signal that indicates a position, and a display device that displays video from the display start position to the display end position in an externally input video signal according to the display period signal output from the timing control circuit A display control circuit configured to display on a horizontal line of the display device, wherein the timing control circuit generates the clock signal starting from a timing defining a start of a horizontal period in the synchronization signal When the number matches the predetermined display start value and display end value, the display start position and the display end are displayed by the display period signal. The end position is indicated.
[Selection] Figure 6

Description

  The present invention relates to a technique for displaying a high-quality video on a display device. More specifically, the present invention relates to a technique for stabilizing an image display position on a display device.

  In a display control circuit that controls to display an image on a display device, in many cases, a clock serving as a reference for the operation of the display control circuit from a composite synchronization signal (C-SYNC signal) separated from a video signal (composite signal) Generate a signal. Specifically, the C-SYNC signal is input to a PLL (Phase Locked Loop) circuit to generate a clock signal synchronized with the C-SYNC signal (see, for example, paragraph number 0002 of Patent Document 1). Then, the display control circuit determines a display start position, a display end position, a display period, and the like based on the generated clock signal.

  A PLL circuit used for clock generation of a display control circuit is an analog circuit that is typically configured using a VCO (Voltage Control Oscillator) using an inductor and a variable capacitor. For this reason, the PLL circuit is easily affected by noise from the surroundings, and the frequency of the clock signal is likely to fluctuate. For example, in a liquid crystal display device, when a cold cathode tube, an inverter transformer, or the like is disposed around a PLL circuit, the frequency of the clock signal output from the PLL circuit varies due to the noise generated by these.

  Further, during the blanking period in the composite synchronization signal, the phase cannot be compared by the PLL circuit, so that the clock signal transmission frequency is shifted. After that, even if the return period ends, it takes time to return to the correct transmission frequency.

When the frequency of the clock signal fluctuates for the above reasons, the display start position, display end position, display period, and the like determined based on the clock signal also fluctuate, and the display quality of the image deteriorates. Specifically, there is a problem that the position of the image displayed for each horizontal line is shifted in the horizontal direction.
JP 2000-241792 A

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a display control circuit capable of stably determining a display position.

  The display control circuit of the present invention designates a display start position and a display end position based on an oscillation circuit that generates a clock signal of a predetermined frequency, a synchronization signal input from the outside, and the clock signal from the oscillation circuit. And a timing control circuit that outputs a display period signal to be displayed, and an image from the display start position to the display end position in a video signal input from the outside according to the display period signal output from the timing control circuit. A display control circuit configured to display on a line, wherein the timing control circuit includes the number of generations of the clock signal starting from a timing that defines a start of a horizontal period in the synchronization signal. When the predetermined display start value and the display end value match, the display start position and the display end are detected by the display period signal. Position instructing, characterized in that.

  The timing control circuit is reset by the synchronization signal and updates a count value by the clock signal, and indicates a display start position when the count value and the display start value coincide with each other. And an arithmetic circuit that indicates a display end position when the display end value matches.

  The timing control circuit stores, at the end of each horizontal period, the maximum value of the number of clock signals generated from the timing defining the start of the horizontal period in the synchronization signal outside the retrace period. During the period, the timing at which the maximum value of the number of generated clock signals coincides with the number of generated clock signals may be set as the timing for defining the start of a new horizontal cycle.

  The display start value and the display end value may be rewritable.

  The oscillation circuit may generate a clock signal asynchronous with the synchronization signal.

  Since the display control circuit of the present invention determines the display start position, the display end position, the display period, and the like based on the number of generated clock signals, the display position in the display device can be stabilized.

The case where the display control circuit of the present invention is applied to a liquid crystal display device will be described as an example.
As shown in FIG. 1, the liquid crystal display device 1 according to the present embodiment includes a liquid crystal panel 2, a display control circuit 3, an oscillation circuit 4, a common driver 5, and a segment driver 6.

  The liquid crystal panel 2 has a matrix of transparent electrodes orthogonal to each other on opposing surfaces of two opposing glass plates. That is, one glass plate has a common electrode (scanning electrode) that receives a scanning signal supplied from the common driver 5, and the other glass plate has a segment electrode (signal) that receives a gradation signal supplied from the segment driver 6. Electrode). Liquid crystal is sealed between the two glass plates. Then, a pixel is formed at a position where the common electrode and the segment electrode intersect. The brightness of the pixel changes depending on the potential difference between the common electrode and the segment electrode. Therefore, a desired image can be displayed by appropriately controlling the potential difference between the common electrodes and the segment electrodes arranged in a matrix.

The display control circuit 3 includes a composite synchronization signal (C-SYNC signal) separated from the video signal by a synchronization separation device (not shown), a signal defining an image (RGB signal), and a clock signal supplied from the oscillation circuit 4. 2 is a control circuit for causing the liquid crystal display device 1 to display a desired image.
As shown in FIG. 2, the display control circuit 3 includes a timing signal generation circuit 31, an AD (Analog to Digital) conversion circuit 32, a data conversion circuit 33, and a liquid crystal drive circuit 34.
The display control circuit 3 may be configured by, for example, a dedicated logic circuit or a microcomputer.

  As shown in FIG. 3, the timing signal generation circuit 31 includes a blanking period determination circuit 311, a first reset generation circuit 312, a horizontal period counter 313, an arithmetic circuit 314, a vertical period counter 315, and a register 316. And a second reset circuit 317, a dot clock output circuit 318, and a memory 319. Based on the C-SYNC signal and the clock signal supplied from the oscillation circuit 4, the timing signal generation circuit 31 generates a timing signal that defines the timing at which each part of the display control circuit 3 operates. Specifically, for example, a signal indicating the conversion timing is supplied to the AD conversion circuit 32, and a signal indicating the display start position and a signal indicating the end of the display period are supplied to the liquid crystal drive circuit 34.

The retrace period determination circuit 311 receives the C-SYNC signal and determines whether the C-SYNC signal is in the retrace period. The blanking period determination circuit 311 outputs a voltage representing a logical value high when it is during the blanking period, and outputs a voltage representing a logical value low when it is not during the blanking period. The output signal of the blanking period determination circuit 311 is supplied to the first reset generation circuit 312 as a signal for inhibiting generation of a pulse of the first reset signal with a logic value high.
The output signal of the blanking period determination circuit 311 is supplied to the vertical period counter 315 as a signal for resetting the count value NV of the vertical period counter 315. Hereinafter, the output signal of the blanking period determination circuit 311 is referred to as a blanking period signal.
The blanking period determination circuit 311 can be realized by, for example, a general sync separation circuit for separating a composite sync signal into a horizontal sync signal and a vertical sync signal.

  The first reset generation circuit 312 receives the C-SYNC signal and generates a pulse of the first reset signal for returning the count value NH of the horizontal period counter 313 to the initial value at every rising edge of the C-SYNC signal. To do. However, the pulse of the first reset signal is not generated while the blanking period signal is the logical high value.

  The first reset generation circuit 312 can be realized, for example, by taking the logical sum of the blanking period signal and the C-SYNC signal by an OR circuit. During the blanking period, the output of the blanking period determination circuit 311 is always high in logic value, so the output of the first reset circuit 312 is also always high in logic value. When it is not the blanking period, the logical value of the C-SYNC signal is output as it is.

  The horizontal period counter 313 is configured by an up counter. The horizontal period counter 313 receives the count value NH in response to the rising edge of the first reset signal from the first reset generation circuit 312 and the rising edge of the second reset signal from the second reset generation circuit 317. Reset to zero. Further, the horizontal period counter 313 increases the count value NH by 1 in response to the clock signal from the oscillation circuit 4. The horizontal period counter 313 supplies the count value NH to the arithmetic circuit 314.

  The arithmetic circuit 314 compares the predetermined display start value A and display end value B stored in the memory 319 in advance with the count value NH supplied from the horizontal period counter 313, and only in the period of A ≦ NH ≦ B. A voltage representing a logic high value is output, and a voltage representing a logic low value is output during other periods. The output of the arithmetic circuit 314 is supplied to the liquid crystal driving circuit 34 and the dot clock output circuit 318. Hereinafter, the output signal of the arithmetic circuit 314 is referred to as a display period signal.

  The vertical period counter 315 is configured by an up counter. The vertical period counter 315 resets the count value NV to 0 in response to the blanking period signal output from the blanking period determination circuit 311. The vertical period counter 315 increases the count value NV by 1 in response to the display period signal. The count value NV of the vertical period counter 315 is supplied to the liquid crystal drive circuit 34.

  The register 316 is a storage element that is configured by a flip-flop or the like and holds an input signal at a timing when a clock signal is supplied. The register 316 receives the first reset signal output from the first reset generation circuit 312 as a clock signal, and receives the count value of the horizontal period counter 313 as data to be held. The register 316 holds the maximum value X (the value immediately before being reset) of the count value NH of the horizontal period counter 313 in each horizontal cycle outside the blanking period.

  The second reset generation circuit 317 generates a reset signal (second reset signal) during the blanking period based on the blanking period signal, the count value NH of the horizontal period counter 313, and the value X held by the register 316. Is generated.

  For example, as shown in FIG. 4, the second reset generation circuit 317 is realized by a comparison circuit, an AND circuit, and a knot circuit. The comparison circuit receives the count value NH of the horizontal period counter 313 and the value X held by the register 316, and outputs a logic value high only when the two values match. The AND circuit receives an output signal from the comparison circuit and a blanking period signal output from the blanking period determination circuit 311 and outputs a logical product of both signals. As described above, the blanking period signal becomes a logical high value only during the blanking period. Only when X matches, a pulse signal having a logic high value is output. Finally, the knot circuit logically inverts the output signal of the AND circuit and outputs it as the second reset signal.

The dot clock output circuit 318 causes the AD conversion circuit 32 to start the conversion operation at the timing when the count value NH of the horizontal period counter 313 matches the display start value A, and converts until the count value NH matches the display end value B. A signal for operation is output based on the output signal of the arithmetic circuit 314. The output signal of the dot clock output circuit 318 is also supplied to the liquid crystal drive circuit 34 as a predetermined number of clock signals (dot clock signals) that match the number of dots in the horizontal direction of the liquid crystal display device 1.
The dot clock output circuit 318 is realized by an OR circuit, for example. That is, the logical product of the display period signal output from the arithmetic circuit 314 and the clock signal output from the oscillation circuit 4 may be supplied to the AD conversion circuit 32 and the liquid crystal driving circuit 34 as a dot clock signal.

  The memory 319 is a storage device configured by, for example, a nonvolatile memory. The memory 319 stores various set values such as a display start value A and a display end value B used in the arithmetic circuit 314. Various setting values stored in the memory 319 may be rewritten by the user.

The AD conversion circuit 32 receives a signal (RGB signal) defining luminance, color difference, etc., which is supplied after being separated from the video signal by an external sync separator, and based on the clock signal from the timing signal generation circuit 31, RGB The signal is converted into a digital signal and supplied to the data conversion circuit 33.
The data conversion circuit 33 converts the digital signal into a gradation data signal in a format that can be received by the liquid crystal drive circuit 34, and supplies it to the liquid crystal drive circuit 34.

The liquid crystal driving circuit 34 is an output circuit for supplying various signals (display period signal, dot clock signal, count value NV of the vertical period counter 315, gradation data signal, etc.) to the common driver 5 and the segment driver 6. .

The common driver 5 is a circuit for applying a scanning signal to the common electrode of the liquid crystal panel 2 and includes a shift register or the like.
The common driver 5 applies a selection voltage to the common electrode corresponding to the first pixel row when the count value NV of the vertical period counter 315 reaches a predetermined value. Thereafter, in synchronization with the rising edge of the display period signal, the common electrode for selecting voltage is shifted in order of the second pixel row, the third pixel row,.

The segment driver 6 is a circuit for applying a gradation signal to the segment electrode of the liquid crystal panel 2, and includes a shift register, a DA (Digital to Analog) conversion circuit, and the like.
The segment driver 6 converts the gradation data signal into an analog gradation signal in synchronization with the dot clock signal, and applies the gradation signal to each segment electrode.

  The oscillation circuit 4 generates a clock signal fixed at a predetermined frequency and supplies it to the display control circuit 3. The oscillation circuit 4 can be configured by a crystal oscillator or the like, for example. The frequency of the clock signal does not need to be synchronized with the synchronization signal (C-SYNC signal), and is set to a frequency suitable for use as a dot clock signal.

  The liquid crystal display device 1 configured as described above displays a desired image on the display unit of the liquid crystal panel 2 under the control of the display control circuit 3. The display control circuit 3 according to the present invention can stabilize the image display position by the operation of the timing signal generation circuit 31 as described below with reference to the drawings.

5 and 6 are time charts showing the operation of the timing signal generation circuit 31. FIG. Input signals to the timing signal generation circuit 31 are a C-SYNC signal (FIG. 5A) and a clock signal (not shown) from the oscillation circuit 4.
The C-SYNC signal is a synchronization signal having both information of a horizontal synchronization signal and a vertical synchronization signal. The C-SYNC signal represents the timing of horizontal synchronization with a negative logic pulse when it is not the blanking period, as indicated by T0 to T2 etc. in FIG. Further, the C-SYNC signal represents the timing of vertical synchronization by emitting a positive logic pulse during the blanking period, as indicated by T3 to T7 in FIG.

As shown in FIG. 5B, the blanking period determination circuit 311 detects the blanking period based on the C-SYNC signal, and outputs the output signal (returning period signal) to the logical value high during the blanking period. To do.
As shown in FIG. 5C, the first reset generation circuit 312 outputs a logical sum of the C-SYNC signal and the blanking period signal output from the blanking period determination circuit 311.

As shown in FIGS. 5D and 6A, the horizontal period counter 313 counts up in response to the clock signal from the oscillation circuit 4. The count value NH is reset to 0 by the first reset signal outside the blanking period and by the second reset signal during the blanking period.
The count values (X ₁ , X _2, etc.) immediately before being reset outside the blanking period are stored in the register 316 as shown in FIG.
Then, as shown in FIG. 5F, the second reset generation circuit 317 uses the count value ( _XY in FIG. 5E) stored in the register 316 at the end outside the blanking period and the horizontal period counter. A second reset signal is generated based on the count value of 313.

As shown in detail in FIG. 6, the arithmetic circuit 314 compares the count value NH (FIG. 6A) of the horizontal period counter 313 with the display start value A and display end value B preset in the memory 319. Then, the output (display period signal) is set to the logic value high only during the period where the count value is A ≦ NH ≦ B (FIGS. 5G and 6B).
As shown in FIG. 6C, the dot clock output circuit 318 outputs a dot clock signal only during a period when the output signal of the arithmetic circuit is a logical value high.
Although not shown, the gradation data signal is supplied to the segment driver 6 in synchronization with the dot clock signal.

  As shown in FIG. 5 (h), the vertical period counter 315 resets the count value NV to 0 by the blanking period signal (T3 in FIG. 5 (h)), and the output of the arithmetic circuit 314 is outside the blanking period. Counts up in response to the display period signal.

By the operation of the timing signal generation circuit 31 as described above, the display period signal, the count value NV of the vertical period counter 315 and the dot clock signal are supplied to the common driver 5 and the segment driver 6.
The common driver 5 applies a selection voltage to the common electrode corresponding to the first pixel row when the count value NV of the vertical period counter 315 reaches a predetermined value. Thereafter, in synchronization with the rising edge of the display period signal, the common electrode for selecting voltage is shifted in order of the second pixel row, the third pixel row,.
The segment driver 6 converts the gradation data signal into an analog gradation signal in synchronization with the dot clock signal, and applies the gradation signal sequentially from the left end (or right end) segment electrode.

  By the operation of the timing signal generation circuit 31 as described above, the arithmetic circuit shown in FIG. 6B is displayed on the liquid crystal panel 2 in the video signal (FIG. 6D) in one horizontal period. This is a portion corresponding to the period from the display start position to the display end position defined by the output signal 314.

  The display control circuit 3 of the present invention counts the stable clock signal supplied from the oscillation circuit 4 with reference to the rising edge of the C-SYNC signal, and determines the display start position and the display end position based on the count values. For this reason, the display start position can be determined stably, and the display quality of the liquid crystal display measure 1 is improved.

When the period of the clock signal is T, the display start position, display end position, and display period with reference to the rising edge of the C-SYNC signal are expressed as follows.
(Display start position) = A × T
(Display end position) = B × T
(Display period) = (B−A) × T

The display control circuit 3 of the present invention can rewrite the display start value A and the display end value B that define the display start position and the display end position stored in the memory 319. For this reason, the display range can be easily expanded and contracted.
In addition, the display control circuit 3 of the present invention can expand and contract the display range by changing the frequency of the clock signal generated by the oscillation circuit 4.

In addition, the display control circuit 3 of the present invention resets the horizontal period counter 313 during the blanking period based on the maximum value of the count value NH outside the blanking period held in the register 316. Therefore, the display period signal and the dot clock signal are output even during the blanking period.
Thereby, the operation of the display control circuit can be stabilized. For example, the unstable operation that occurs when the AD conversion circuit 32 starts the conversion operation from the stopped state can be eliminated.

  In this embodiment, the display start value A and the display end value B are used to define the display start position and the display end position. However, the means for defining the display start position and the display end position is not limited to this. . For example, it may be defined by a display start position and a display period (the number of dot clocks until display is terminated).

  In this embodiment, the case where a composite synchronization signal is input as a synchronization signal to the display control circuit has been described as an example. However, a horizontal synchronization signal and a vertical synchronization signal are input to the display control circuit independently. Also good. In this case, the display start position and the display end position can be defined by the number of clock signals starting from a specific location (for example, a rising edge) in the horizontal synchronization signal.

  In this embodiment, the case where the display control circuit according to the present invention is applied to a liquid crystal display device has been described as an example. However, the display control circuit according to the present invention includes an organic EL (electroluminescence) display, a plasma display, and the like. The present invention can be applied to various display devices.

It is a block diagram which shows the structure of a liquid crystal display device. It is a block diagram which shows the structure of a display control circuit. It is a block diagram which shows the structure of a timing signal generation circuit. It is a block diagram which shows the structure of a 2nd reset generation circuit. It is a time chart which shows operation | movement of a timing signal generation circuit. It is a time chart for demonstrating the determination method of a display start position and a display end position.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display device, 2 ... Liquid crystal panel, 3 ... Display control circuit, 4 ... Oscillation circuit, 5 ... Common driver, 6 ... Segment driver.

Claims (5)

An oscillation circuit for generating a clock signal of a predetermined frequency;
A timing control circuit for outputting a display period signal indicating a display start position and a display end position based on a synchronization signal input from the outside and the clock signal from the oscillation circuit;
In accordance with the display period signal output from the timing control circuit, a display device drive circuit for displaying a video from the display start position to the display end position in a video signal input from the outside on a horizontal line of the display device;
A display control circuit comprising:
The timing control circuit uses the display period signal when the number of generations of the clock signal starting from the timing defining the start of the horizontal period in the synchronization signal coincides with a predetermined display start value and display end value. Specify the display start position and display end position.
A display control circuit. The timing control circuit includes:
A counter that is reset by the synchronization signal and updates a count value by the clock signal;
An operation circuit that indicates a display start position when the count value and the display start value match, and that indicates a display end position when the count value and the display end value match;
The display control circuit according to claim 1. The timing control circuit includes:
Outside the blanking period, the maximum value of the number of generated clock signals starting from the timing defining the start of the horizontal period in the synchronization signal is stored at the end of each horizontal period,
During the retrace period, the timing at which the maximum value of the number of generated clock signals coincides with the number of generated clock signals is defined as the timing for defining the start of a new horizontal cycle.
The display control circuit according to claim 1. The display start value and the display end value can be rewritten.
The display control circuit according to claim 1, wherein the display control circuit is a display control circuit. The oscillation circuit generates a clock signal asynchronous with the synchronous signal;
The display control circuit according to claim 1, wherein the display control circuit is a display control circuit.

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