JP2007088958A - Logic circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate the need to take into account PVT worst (worst conditions of process, voltage and temperature) by performing data transfer at a highest rate, matching the arithmetic speed of a redundant combinational logic circuit. <P>SOLUTION: Data from an input register 10 are inputted to a redundant combinational logic circuit 30, respectively as paired signals comprised of regular bits and redundant bits by a redundant bit encoder 20, and the regular bits of the paired signals outputted from the redundant combinational logic circuit 30 are inputted to an output register which is operated by a forward rotation clock CLK. When a reverse rotation clock CLKX is "0", the paired signals to be outputted are made into "0" together by the redundant bit encoder 20; and when the reverse rotation clock CLKX is "1", the paired signals are outputted, while keeping the input signal, as it is. The redundant combinational logic circuit 30 performs logic operations according to the regular signals in a plurality of inputted paired signals; but when both the inputted paired signals are "0", paired signals of "0" are outputted. The clock is made into "1" or "0" according to each logic of each paired signal outputted from the redundant combinational logic circuit. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a logic circuit that performs arithmetic processing on a plurality of input data by a combinational logic circuit and transfers the processed data to a subsequent stage.

  A circuit shown in FIG. 5 is known as this type of logic circuit (for example, see FIG. 1 of Patent Document 1). The logic circuit is processed by an input register 10 composed of n flip-flops 101 to 10n, a combinational logic circuit 90 that performs a predetermined logical operation based on data held in the input register 10, and the combinational logic circuit 90. The output register 50 includes a plurality of flip-flops 501 to 50m that hold data, and a clock oscillation circuit 100 that supplies a clock CLK to both registers 10 and 50.

In this logic circuit, when the clock CLK output from the clock oscillation circuit 100 becomes “1”, the input data is taken in by the input register 10, and this data is arithmetically processed by the combinational logic circuit 90, and the result of the operation is the next time. When the clock CLK becomes “1”, it is taken into the output register 50.
JP-A-10-149228

  However, in such a logic circuit, the maximum frequency that can be set for the clock CLK is restricted by the longest path from the input register 10 to the output register 50, and therefore, the maximum frequency that can be set up to the PVT worst (worst process, voltage, and temperature conditions). It was necessary to consider.

  An object of the present invention is to perform data transfer in synchronization with the operation start and operation end of a combinational logic circuit, so that the data transfer is performed at the highest speed that matches the operation speed of the combinational logic circuit. Is to provide.

  In order to solve the above-described problem, the logic circuit of the invention according to claim 1 sets the normal output to “1” when the set signal is input and sets the inverted output to “0” when the set signal is input. An SR latch circuit that sets the inverted output to “1” at “0”, an input register that includes a plurality of flip-flops that hold signals that are input when the normal output of the SR latch circuit is “1”, and the input register The normal output of each of the flip-flops is a normal bit and the inverted output is a redundant bit. A signal composed of the normal bit and the redundant bit is used as a pair signal, and the inverted output of the SR latch circuit is set to “1”. The redundant bit encoder that passes as it is when it is “0”, shuts off when it is “0” and outputs both as “0”, and the pair signals output from the redundant bit encoder, When the input pair signals are different from each other, a plurality of pair signals of a predetermined operation result are output, and when the input pair signals are both “0”, a plurality of pair signals are output. A redundant combinational logic circuit that performs the operation, a calculation end detection circuit that outputs a logical sum operation result of each pair signal output from the redundant combinational logic circuit, and all output signals of the calculation end detection circuit are “0”. A reset circuit for sending the reset signal to the SR latch circuit at the time, and a set circuit for sending the set signal to the SR latch circuit when all output signals of the operation end detection circuit are "1"; When the normal output of the SR latch circuit is “1”, a plurality of flip-flops that receive and hold normal bit signals of the pair signals output from the redundant combinational logic circuit. An output register comprised of-up, and configured to include a.

  According to a second aspect of the present invention, in the logic circuit according to the first aspect, the redundant combinational logic circuit has a ripple whose operation signal, operand signal, carry input signal, addition signal, and carry output signal are the pair signals, respectively. It was configured to be a carry adder.

  According to the present invention, when each logic of the output pair signal of the redundant combinational logic circuit is “0”, a plurality of new pair signals are input from the redundant bit encoder and the logical operation is performed in the redundant combinational logic circuit. Upon completion of the operation, the logic of the output pair signals of the redundant combinational logic circuit is different from each other, so that new data is held in the input register, and the normal bit of the redundant combinational logic circuit at that time is held in the output register. Therefore, data transfer is performed according to the logical operation speed of the redundant combinational logic circuit. That is, data transfer is performed at the highest speed that matches the operation speed of the redundant combinational logic circuit.

  When the combinational logic circuit is a ripple carry adder, the propagation time of the carry signal is usually slower than that of the addition signal, and it is necessary to set the clock frequency considering the PVT worst in consideration of this. In the present invention, when a ripple carry adder is configured with a redundant combinational logic circuit, there is an advantage that data transfer is performed at the highest speed that matches the operation speed of the redundant combinational logic circuit regardless of the PVT worst.

  FIG. 1 is a block diagram showing the configuration of a logic circuit according to one embodiment of the present invention. An input register 10 includes n flip-flops 101 to 10n, and updates held data every time the normal clock CLK input to the clock terminal rises to “1”.

  20 is a redundant bit encoder, corresponding to the flip-flop 101 of the input register 10, and an AND circuit 201 for inputting the normal output Q and the inverted clock CLKX, and the inverted output QX and inverted clock CLKX of the flip-flop 101. An AND circuit 211 is provided. When the inverted clock CLKX is “1”, the AND circuit 201 outputs a normal bit (normal output Q of the flip-flop 101) as a signal E1, and the AND circuit 211 outputs a redundant bit (inverted output QX of the flip-flop 101). When the inverted clock CLKX is “0”, the pair signals E1 and EX1 are both “0”. The same applies to the sets of AND circuits 202 and 212 to 20n and 21n corresponding to the flip-flops 102 to 10n of the input register 10.

  A redundant combinational logic circuit 30 is composed of various redundant bit-added logic elements, which will be described later, and receives pair signals E1, E1X to En, EnX from the redundant bit encoder 20 to perform a predetermined logical operation.

  Reference numeral 40 denotes an operation end detection circuit, which is an OR circuit 401 for inputting a normal bit signal F1 and a redundant bit signal F1X output from the redundant combinational logic circuit 30, and similarly, pair signals F2, F2x to OR circuits 402 to 40m for inputting Fn and FnX are provided.

  Reference numeral 50 denotes an output register, which is composed of m flip-flops 501 to 50m, receives normal bit signals F1 to Fm of the redundant combinational logic circuit 30, and the normal clock CLK input to the clock terminal rises to "1". Each time, the retained data is updated.

  Reference numeral 60 denotes a reset circuit composed of a NOR circuit, which sets the reset signal Crst to “1” when all the outputs of the OR circuits 401 to 40m of the calculation end detection circuit 40 are “0”.

  Reference numeral 70 denotes a set circuit composed of an AND circuit, which sets the set signal Cset to “1” when the outputs of the OR circuits 401 to 40m of the calculation end detection circuit 40 are all “1”.

  Reference numeral 80 denotes an SR latch circuit composed of two NOR circuits 801 and 802. When the reset signal Crst output from the reset circuit 60 is "1", the normal clock CLK is set to "0" and the inverted clock CLKX is set. When the set signal Cset output from the set circuit 70 is “1”, the normal clock CLK is set to “1” and the inverted clock CLKX is set to “0”.

  FIG. 2 is an explanatory diagram of a logic element to which redundant bits are added, which is a constituent element of the redundant combinational logic circuit 30. (a) is explanatory drawing of an inverter, the left side is a normal inverter, and the right side is a redundant bit addition inverter 301. In the redundant bit addition inverter 301, the pair signals A0 and A1 are inverted to generate the pair signals Y0 and Y1.

  FIG. 2B is an explanatory diagram of a 2-input OR circuit. The left side is a normal OR circuit, and the right side is a redundant bit addition OR circuit 302. The redundant bit addition OR circuit 302 uses the 2-input AND circuit 3021 and the 2-input OR circuit 3022 to input the pair signals A0, A1 and the pair signals B0, B1 to generate the pair signals Y0, Y1.

  FIG. 2C is an explanatory diagram of a 2-input AND circuit. The left side is a normal AND circuit, and the right side is a redundant bit addition AND circuit 303. The redundant bit addition AND circuit 303 uses a two-input OR circuit 3031 and a two-input AND circuit 3032 and inputs pair numbers A0 and A1 and pair signals B0 and B1 to generate pair signals Y0 and Y1.

  FIG. 3 is an explanatory diagram of a full adder (full adder) 304, which inputs a pair of arithmetic signals A0 and A1, a pair of arithmetic signals B0 and B1, and a pair of carry input signals C0 and C1, and inputs a pair of addition signals. Carry output signals CA0 and CA1 paired with S0 and S1 are generated.

  Each of the redundant bit addition logic elements shown in FIGS. 2 (a) to 2 (c) and FIG. 3 has one of normal bits A0, B0, C0, Y0, etc. in the pair signal of “1” and “0”. In logic, redundant bits A1, B1, C1, and Y1 are the other logic. When the pair of pair signals A0 and A1, B0 and B1, and C0 and C1 are both “0” and “0”, the pair signals Y0 and Y1 are also “0” and “0”. It becomes a combination.

  When the normal clock CLK of the SR latch circuit 80 is “1” and the inverted clock CLKX is “0”, the input register 10 newly holds data input from the previous stage, and the output register 50 is a redundant combinational logic circuit. 30 output data are newly held. Since all the outputs of the AND circuits 201 to 20n and 211 to 21n of the redundant bit encoder 20 are “0”, each redundant bit additional logic element of the redundant combinational logic circuit 30 that receives the output of the redundant bit encoder 20 is The output signals of the pair are all “0”, and the normal bit signals F1 to Fm and the redundant bit signals F1X to FmX are all “0”. As a result, the outputs of the OR circuits 401 to 40m of the calculation end detection circuit 40 are “0”, the reset signal Crst that is the output of the reset circuit 60 is “1”, and the set signal Cset that is the output of the set circuit 70 is It becomes “0”. Therefore, the normal clock CLK of the SR latch circuit 60 is “0” and the inverted clock CLKX is “1”.

  At this time, the input register 10 and the output register 50 do not hold new data. Since the AND circuits 201 to 20n and 211 to 21n of the redundant bit encoder 20 all open the gates, the normal output Q and the inverted output QX of each flip-flop of the input register 10 are passed as they are to the redundant combinational logic circuit 30. Let them enter. Therefore, the redundant combinational logic circuit 30 performs logic processing according to the input data, and one of the normal bit signal F1 and the redundant bit signal F1X, which is one pair output, is “1” and the other is “0”. . The same applies to the other sets of signals F2 and F2X to the sets of signals Fm and FmX. As a result, the outputs of the OR circuits 401 to 40n of the calculation end detection circuit 40 are “1”, the reset signal Crst that is the output of the reset circuit 60 is “0”, and the set signal Cset that is the output of the set circuit 70 is “1”. Therefore, the normal clock CLK of the SR latch circuit 60 is “1”, and the inverted clock CLKX is “0”. Therefore, the output data (normal bit) of the redundant combinational logic circuit 30 is newly held in the output register 50. The input register 10 holds new data.

  The operations as described above are repeated, and input data is calculated and transferred. In the above circuit, the outputs of the OR circuits 401 to 40m of the operation end detection circuit 40 are all "1" and the output of the set circuit 70 is "1" only when the respective operation results in the redundant combinational logic circuit 30 are ready. Since the SR latch circuit 80 is inverted from reset to set, the logical operation is automatically advanced according to the operation speed of the redundant combinational logic circuit 30, thereby enabling high-speed operation. In the conventional example, it is necessary to set the maximum frequency of the clock in consideration of the longest path and the PVT worst, but this is not necessary.

  FIG. 4 is a diagram showing a circuit in a case where an m-bit output ripple carry adder is configured as the redundant combinational logic circuit 30 by using m (3041 to 304m) full adders 304 of FIG. In this circuit, even if the propagation time of the carry signal is slow, the data transfer is performed at an operation speed suitable for the carry signal, and the data transfer is performed at the highest speed that matches the calculation speed of the ripple carry adder.

It is a block diagram of the logic circuit of the Example of this invention. It is explanatory drawing of the redundant bit addition logic element (an inverter, an OR circuit, and AND circuit) used as the component of a redundant combinational logic circuit. It is explanatory drawing of the redundant bit addition full adder used as the component of a redundant combinational logic circuit. It is a block diagram of a logic circuit when a redundant combination logic circuit is a ripple carry adder. It is a block diagram of a conventional logic circuit.

Explanation of symbols

10: Input register 20: Redundant bit encoder 30: Redundant combinational logic circuit 40: Completion detection circuit 50: Output register 60: Reset circuit 70: Set circuit 80: SR latch circuit

Claims (2)

An SR latch circuit that sets the normal output to "1" when the set signal is input and sets the inverted output to "0", and sets the normal output to "0" and the inverted output to "1" when the reset signal is input;
An input register comprising a plurality of flip-flops for holding a signal to be input when the normal output of the SR latch circuit is “1”;
The normal output of each flip-flop of the input register is a normal bit and the inverted output is a redundant bit. A signal composed of the normal bit and the redundant bit is used as a pair signal. A redundant bit encoder that passes when it is “1”, shuts off when “0”, and outputs both as “0”;
Each pair signal output from the redundant bit encoder is input, and when each logic of the input pair signal is different from each other, a plurality of pair signals of a predetermined operation result are output. A redundant combinational logic circuit that outputs a plurality of pair signals of "0" when both are "0";
An operation end detection circuit for outputting a logical OR operation result of each of the pair signals output from the redundant combinational logic circuit;
A reset circuit for sending the reset signal to the SR latch circuit when all output signals of the operation end detection circuit are "0";
A set circuit for sending the set signal to the SR latch circuit when all output signals of the operation end detection circuit are "1";
An output register comprising a plurality of flip-flops for inputting and holding normal bit signals among the pair signals output from the redundant combinational logic circuit when the normal output of the SR latch circuit is "1";
A logic circuit comprising: The logic circuit according to claim 1,
The redundant combinational logic circuit is a ripple carry adder that uses an operation signal, a signal to be operated, a carry input signal, an addition signal, and a carry output signal as the pair signals, respectively.

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