JP2006319010A - MOS type semiconductor device - Google Patents

Abstract

Provided is a MOS semiconductor device used as a high-breakdown-voltage switching power supply IC.
SOLUTION: 1 is a P-type semiconductor substrate, 32 is an N-type extended drain region, 4 is an N-type source region, 5 is a source electrode, 6 is a gate electrode, 34 is an N-type high concentration drain region, and 41 is an isolation oxide film , 38 are interlayer insulating films, 35 is a drain electrode, 11 is a gate oxide film, 45 is a drain contact window, 13 is a source contact window, and 46 is a contact window. The semiconductor substrate 1 has an extended drain region 32 provided with a reverse conductivity type high concentration drain region 34, and the extended drain region 32 has a P-type first impurity region 40 or a P-type second impurity under the isolation oxide film 41. The region 37 is provided in contact with the first impurity region 40, and the second impurity region 37 includes a plurality of columnar or prismatic impurity layers 37 a and 37 b and is disposed perpendicular to the substrate 1. The columnar impurity layers 37a and 37b are arranged alternately. The source electrode 5 and the electrode 42 are electrically connected by metal wiring.
[Selection] Figure 1

Description

  The present invention relates to a MOS type semiconductor device having high breakdown voltage characteristics.

  Hereinafter, a lateral MOS field effect transistor having a high breakdown voltage characteristic between a drain and a source will be described with reference to Patent Document 1.

  FIG. 2 is a sectional view of a lateral MOS field effect transistor.

  In FIG. 2, 1 is a P-type semiconductor substrate, 2 is an N-type extended drain region, 3 is a P-type buried region, 4 is an N-type source region, 5 is a source electrode, 6 is a gate electrode made of polycrystalline silicon, Reference numeral 8 denotes an N-type high-concentration drain region, 9 denotes an interlayer insulating film, 10 denotes a drain electrode, 11 denotes a gate oxide film, 12 denotes a drain contact window, 13 denotes a source contact window, and 14 denotes a channel region.

  As shown in FIG. 2, a high concentration drain region 8 having a conductivity type opposite to that of the semiconductor substrate 1 is formed in the extended drain region 2, and a part of the extended drain region 2 is electrically the same type as the semiconductor substrate 1. Embedded region 3 is formed, and gate electrode 6 is formed on channel region 14 provided between extended drain region 2 and source region 5 via gate oxide film 11.

The heavily doped drain region 8 is connected to the drain electrode 10 at the drain contact window 12, and the N-type source region 4 is connected to the source electrode 5 at the source contact window 13.
JP 2003-86797 A

  The lateral MOS field effect transistor shown in the prior art has a depletion formed at the junction surface between the extended drain region and the buried region in the on state where the gate electrode is applied, and a current flows between the source and the drain in the off state. Due to the effect of the layer, a high breakdown voltage can be obtained between the source and the drain and between the substrate and the drain.

  On the other hand, a switching power supply IC is required to have a high withstand voltage not only with respect to a DC withstand voltage but also with respect to an AC pulse voltage such as a surge voltage.

  However, in order to obtain a high breakdown voltage against such a surge, it is not sufficient to provide an extended drain region and adjust the resistance value. Further, only the depletion layer formed at the junction surface between the extended drain region and the buried region disclosed in Patent Document 1 has insufficient capacity to absorb this surge.

  Therefore, in order to use the lateral MOS field-effect transistor shown in the prior art for a switching power supply IC, an external capacitor of several thousand pF must be provided between the drain and the source.

  However, the use of such external components is not only disadvantageous in terms of cost, but also increases the area as a switching IC.

  Accordingly, in view of the above problems, the present invention provides a MOS semiconductor device that can be used as a high-breakdown-voltage switching power supply IC without requiring an external capacitor.

  In order to solve the above problems, a MOS type semiconductor device according to the present invention includes a second conductivity type source region provided on one surface of a first conductivity type semiconductor substrate, and a second conductivity type provided on one surface of the semiconductor substrate. A second conductivity type extended drain region, a second conductivity type high concentration drain region provided in the extended drain region facing the substrate surface, and a channel provided between the source region and the extended drain region A first gate electrode provided on the channel region via a gate oxide film, a first impurity region of a first conductivity type provided on one surface of the semiconductor substrate, and a first gate electrode provided in the extended drain region. A second impurity region of one conductivity type, a drain electrode connected to the high-concentration drain region and the contact window, a source electrode connected to the source region and the contact window, and a first impurity region connected to the contact window The The second impurity layer and the first impurity region are electrically connected, and the first impurity region and the source region are electrically connected and have the same potential. .

  In the MOS semiconductor device according to the present invention, the second impurity region is more preferably an aggregate in which a plurality of impurity layers having a columnar shape or a prismatic shape are arranged so as to be separated from each other.

  In the MOS type semiconductor device according to the present invention, the MOS type semiconductor device is more preferably a switching power supply IC or LSI.

  In the MOS type semiconductor device of the present invention, a plurality of buried layers are provided in parallel in the extended drain region, and these are set to the same potential as the source potential, thereby eliminating the need for an external capacitor and a switching power supply IC having an excellent surge withstand voltage. Alternatively, it can be used as an LSI.

  Hereinafter, a MOS type semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram showing a configuration of a MOS type semiconductor device according to the present embodiment. FIG. 1A is a cross-sectional view, and FIG. 1B is a plan view showing a part of the structure.

  In FIG. 1, 1 is a P-type semiconductor substrate, 32 is an N-type extended drain region, 4 is an N-type source region, 5 is a source electrode, 6 is a gate electrode made of polycrystalline silicon, 34 is an N-type high-concentration drain region, Reference numeral 41 denotes an isolation oxide film, 38 denotes an interlayer insulating film, 35 denotes a drain electrode, 11 denotes a gate oxide film, 45 denotes a drain contact window, 13 denotes a source contact window, and 46 denotes a contact window.

  In addition, the semiconductor substrate 1 has an extended drain region 32 provided with a high-concentration drain region 34 of a reverse conductivity type, and a gate is formed on the channel region 14 provided between the extended drain region 32 and the source region 4. A gate electrode 6 is formed through the oxide film 11.

  The extended drain region 32 has a P-type first impurity region 40 under the isolation oxide film 41, and a P-type second impurity region 37 is provided in contact with the P-type first impurity region 40. Yes.

  The second impurity region 37 is preferably P-type with a higher concentration than the first impurity region 40.

  Further, as shown in FIG. 1A, the P-type second impurity region 37 includes a plurality of columnar or prismatic impurity layers 37a and 37b (hereinafter referred to as “columnar impurity layers 37a and 37b”). Are arranged perpendicular to the substrate 1.

  Further, as shown in FIG. 1B, the respective columnar impurity layers 37a and 37b are arranged alternately apart from each other.

  In the figure, each of the cylindrical impurity layers 37a and 37b constituting the P-type second impurity region 37 is shown one by one, but actually there are a plurality of cylindrical impurity layers 37a and 37b.

  In addition, the P-type first impurity region 40 is electrically connected to the electrode 42 formed in the opened contact window 46 by partially removing the isolation oxide film 41 and the interlayer insulating film 38.

  The high-concentration drain region 34 is electrically connected to the drain electrode 35 formed in the opened drain contact window 45 by partially removing the isolation oxide film 41 and the interlayer insulating film 38.

  Further, the N-type source region 4 is electrically connected to the source electrode 5 formed in the opened source contact window 13 by partially removing the interlayer insulating film 38.

  The source electrode 5 and the electrode 42 are electrically connected by a metal wiring such as aluminum.

  That is, in the present embodiment, the source region 4, the first impurity region 40, and the second impurity region 37 are at the same potential.

  As described above, the MOS semiconductor device according to the embodiment of the present invention is configured.

  The MOS type semiconductor device is characterized in that the extended drain region 32 includes a first impurity region 40 and a P-type second impurity region 37, and the first impurity region 40 and the P-type second impurity region 37 are The potential is the same as that of the source region 4.

  When a high voltage is applied to the drain region 34, the extended drain region 32 and the semiconductor substrate 1, the P-type second impurity region 37 and the extended drain region 32, the P-type first impurity region 40 and the extended drain region 32 are Each is in a reverse bias state.

  Further, since the second impurity region 37 is composed of a plurality of columnar impurity layers 37a and 37b, for example, each junction between the columnar impurity layer 37a and the extended drain region 32, or the columnar impurity layer 37b and the extended drain. Each depletion layer expands from each junction with the region 32, and each depletion layer becomes continuous, thereby expanding the depletion layer over the entire extended drain.

  In addition, since the depletion layer extends to the junction between the extended drain region 32 and the substrate 1 and the junction between the first impurity region 40 and the extended drain region 32, the depletion formed in the second impurity region 37 and the extended drain region 32 is also performed. Connected to the layer, the depletion layer will expand.

  As described above, the MOS type semiconductor device according to the embodiment of the present invention can obtain further higher withstand voltage characteristics because the depletion layer region at the time of off is larger than the MOS type semiconductor device shown in the prior art. .

  Further, in the reverse bias state, the extended drain region 32 and the semiconductor substrate 1, the P-type second impurity region 37 and the extended drain region 32, and the P-type first impurity region 40 and the extended drain region 32 near the pn junction. Each has a space charge and has a pn junction surface equivalent to a parallel plate capacitor.

  In particular, in the present embodiment, the second impurity region 37 is a plurality of columnar impurity layers 37a and 37b, and the pn junction area is greatly expanded, so that the capacitor capacity can be increased.

  Therefore, even if an external capacitor is not used, the surge can be sufficiently absorbed by the capacitance formed by the pn junction, high breakdown voltage characteristics can be obtained, and a high-performance switching power supply IC or LSI can be realized.

  In addition, according to the present embodiment, since a plurality of P-type second impurity regions 37 are provided in the extended drain region 32 at regular intervals, a small amount of depletion occurs when a voltage is applied to the drain region 34. As described above, the extended drain region 32 is entirely depleted by the extension of the layer. This means that the entire extended drain region 32 is depleted in a short time as compared with the conventional configuration, that is, the switching time at the off time is shortened. As a result, a MOS semiconductor device having a high breakdown voltage and a high-speed response can be obtained.

  Note that the distance between the cylindrical impurity layers 37 constituting the second impurity region 37 is such that when the high reverse bias is applied, the depletion layers are spread and uniformly connected, and high breakdown voltage characteristics can be realized. Each is preferably arranged.

  In addition, the impurity concentration of the second impurity region 37 and the impurity concentration of the extended drain region 32 are preferably set so as to have a junction electric field strength of 30 V / μm or less at which avalanche breakdown occurs.

  The MOS type semiconductor device according to the present invention has a high breakdown voltage characteristic between a source and a drain, and also has an excellent response characteristic for switching on / off of voltage application, and is used for a switching power supply IC or LSI. Useful as a device.

Sectional structure diagram and planar structure diagram of MOS type semiconductor device according to an embodiment of the present invention Cross-sectional structure diagram of MOSFET, which is a conventional semiconductor device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 4 Source region 5 Source electrode 6 Gate electrode 11 Gate oxide film 13 Contact window part 14 Channel region 32 Extension drain region 34 Drain region 35 Drain electrode 37a Impurity layer 37b Impurity layer 37 Impurity region 38 Interlayer insulation film 40 Impurity region 41 Isolation oxide film 42 Electrode 45 Contact window 46 Contact window

Claims (4)

A second conductivity type source region provided on one surface of the first conductivity type semiconductor substrate;
An extended drain region of a second conductivity type provided on one surface of the semiconductor substrate;
A high-concentration drain region of a second conductivity type provided in the extended drain region and on the surface of the semiconductor substrate;
A channel region provided between the source region and the extended drain region;
A gate electrode provided on the channel region via a gate oxide film;
A first impurity region of a first conductivity type provided on a surface of the extended drain region;
A second impurity region of the first conductivity type provided extending in the depth direction from the surface of the extended drain region;
A drain electrode connected to the high-concentration drain region; a source electrode connected to the source region;
An electrode connected to the first impurity region,
The second impurity region and the first impurity region are electrically connected,
The MOS type semiconductor device, wherein the first impurity region and the source region are electrically connected and have the same potential. 2. The MOS semiconductor device according to claim 1, wherein the second impurity region includes a plurality of first conductivity type impurity layers having a columnar shape or a prismatic shape and spaced apart from each other at a predetermined interval. 3. The MOS type semiconductor device according to claim 1, wherein the second impurity region is provided so as to extend from the first impurity region in a depth direction of the extended drain region. A switching power supply IC comprising the MOS type semiconductor device according to any one of claims 1 to 3.

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