JPH1093023A - Semiconductor device - Google Patents

Abstract

(57) [Problem] To reduce the size of a switched capacitor type DC-DC converter. A plurality of trench capacitors and a plurality of lateral MOSFETs for connecting them directly or in parallel are formed in an SOI layer provided on a silicon oxide film.
These element regions are separated by trenches filled with the silicon oxide film 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a structure in which a plurality of capacitors are connected directly or in parallel by switching elements according to conditions.

[0002]

2. Description of the Related Art FIG. 8 shows an equivalent circuit of a DC-DC converter which handles a high voltage of 100 V or more by a conventional switched capacitor method. Here, a case where 150 V is converted to 1/5 of 30 V will be described as an example.

[0003] The DC-DC converter, the capacity and the same five capacitors 91 _{1-91 5,} switches 92 ₁ to connect the capacitors 91 _{1-91 4} in series
And -92 _5, the switch 93 ₁ to 93 ₈ for connecting the capacitor 91 _{1-91 5} in parallel, the capacitor 91 ₁
And a to 91 ₅ switch 95 ₁ to connect to a power source 94 of 150V and 95 _2.

[0004] According to the DC-DC converter configured as described above, the switch 92 ₁ to 92 _5, the switch 95
_1, close the 95 _2, open the switch 93 _{1-93 8,}
After charging the power 94 of 150V to connect the capacitor 91 _{1-91 4} in series, the switch 92 ₁ to 92 _5, opens the switch 95 _1, 95 _2, closing switch 93 _{1-93 8,} capacitor 91 ₁ to 91 _{by 4} connected in parallel, the 150V of 1/5 30 V output voltage V _out of _the
Is obtained.

However, this type of DC-DC converter has the following problems. Now, the output voltage V of 30V
Consider taking 10mA output current at _out , 1MHz
Assuming that for switching, capacity necessary for the capacitor 91 _{1-91 4} becomes high as 3.3 nF.

Conventionally, since the capacitor insulating film of the capacitor 91 _{1-91 4} silicon oxide film is used,
In order to obtain such a large capacity, a large area (capacitor region) of about 0.1 cm ² is required. Therefore,
It has been difficult to integrate a DC-DC converter that handles a high voltage of 100 V or more into a single chip using a conventional switched capacitor method.

[0007] In addition, switch 92 _{1-92 5,} 93 ₁ ~
93 _8, 95 _1, 95 ₂ of the separation, conventionally, because it was performed by pn junction isolation, the area of the switch region is increased, which also has been a cause of difficulty in one chip.

[0008]

As described above, the conventional switched-capacitor high-voltage DC-DC converter requires a large capacitor area to obtain a large capacity, and it has been difficult to integrate it into one chip. Further, since the switch is separated by the pn junction separation, the area of the switch region becomes large, which also makes it difficult to make one chip.

The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor device having a structure effective for miniaturization, in which a plurality of capacitors are connected directly or in parallel according to conditions. Is to provide.

[0010]

[Means for Solving the Problems]

[Summary] In order to achieve the above object, a semiconductor device according to the present invention (claim 1) is provided on an insulating film, and a plurality of capacitor regions and a plurality of switch regions are formed by element isolation grooves reaching the insulating film. A plurality of semiconductor layers, a device isolation insulating film filling the device isolation trenches, a trench capacitor formed in each of the plurality of capacitor regions, and the plurality of switch regions formed in each of the plurality of switch regions. Switching means for connecting the groove type capacitors in series or in parallel according to conditions.

According to another semiconductor device of the present invention (claim 2), in the above-mentioned semiconductor device (claim 1), the groove type capacitor has a plurality of grooves, and the planar pattern is a stripe pattern. It is a pattern repeated in a direction perpendicular to the direction.

In another semiconductor device according to the present invention (claim 3), in the semiconductor device (claim 1), the insulating film is a silicon oxide film, and the capacitor insulating film of the trench type capacitor is a silicon nitride film. Is also an insulating film having a high dielectric constant.

Further, another semiconductor device of the present invention (claim 4) is characterized in that, in the above-mentioned semiconductor device (claim 1), one capacitor electrode of the groove type capacitor is formed of a conductive layer. And

Here, the conductive layer means not a diffusion layer formed in the semiconductor layer but a layer having a small band gap and high conductivity, such as a metal layer such as an Al layer. Further, another semiconductor device of the present invention (claim 5) is characterized in that, in the above-mentioned semiconductor device (claim 1), the switching means is constituted by a lateral MOSFET.

According to another semiconductor device of the present invention (claim 6), in the above-mentioned semiconductor device (claim 5), the thickness of the semiconductor layer below the drain layer of the lateral MOSFET is l.
(Cm), the impurity concentration of the semiconductor layer below the drain layer is N _A (cm ⁻³ ), and the dielectric constant of the semiconductor layer is ε (F / c).
m), when the voltage applied between the drain and the source of the lateral MOSFET is V _SD and the elementary charge is q, ｛(2
and wherein _{ε s · V SD) / (} q · N A)} 1/2 < satisfies: l.

In another semiconductor device of the present invention (claim 7), in the semiconductor device (claim 1), when the switching means connects the plurality of grooved capacitors to a power supply, The groove-type capacitors are connected in series, and when disconnecting the plurality of groove-type capacitors from a power supply, the plurality of groove-type capacitors are connected in parallel.

Here, the above two inventions (Claim 2,
3) should also be applied. According to the present invention (claim 1), a semiconductor layer formed on an insulating film is used as a substrate on which an element is formed,
Since each element (groove type capacitor, lateral MOSFET) region is isolated by an element isolation groove formed in a semiconductor layer and embedded with an element isolation insulating film, a conventional pn is used.
Miniaturization can be performed more easily than in the case of junction separation.

Further, since the planar pattern according to the present invention (claim 2) is a pattern effective for increasing the capacitance of the trench type capacitor, a large capacitance can be obtained without particularly increasing the area of the capacitor region. As a result, miniaturization can be easily performed.

Further, according to the present invention (claim 3), the capacitance of the capacitor can be increased as compared with the conventional structure in which the insulating film below the semiconductor layer and the capacitor insulation of the trench type capacitor are both silicon oxide films. Become.

Further, according to the present invention (claim 4), the resistance can be reduced as compared with the case where both of the capacitor electrodes are formed of a semiconductor. Further, in the present invention (claim 5), considering that the power supply voltage normally used is 200 V or less in many cases, the horizontal M
OSFET is used. That is, in this case, both the breakdown voltage and the switching speed can be satisfied.

Further, according to the present invention (claim 6), the concentration and the film thickness are optimized, and the required breakdown voltage can be secured without using a buried semiconductor layer. Therefore, a buried semiconductor layer becomes unnecessary, and the cost can be reduced. In other words, it is possible to improve the withstand voltage without increasing the cost.

Further, according to the present invention (claim 7), it is possible to realize a switched capacitor type DC-DC converter which is effective for one chip by the operation and effect of the above invention (claim 1).

[0023]

Embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings. In the present embodiment, a groove type (trench) capacitor and a lateral type MOSFET (switch) described below are used in FIG.
The DC-DC converter of the switched capacitor type shown in FIG. Since these elements are suitable for miniaturization as described below, a high-voltage DC-DC converter can be made into one chip.

FIG. 1 is a sectional view showing an element structure of a capacitor used in a switched capacitor type DC-DC converter according to an embodiment of the present invention. However, FIG.
Shows only two capacitors in a simplified manner. Each capacitor is composed of two trench capacitors.

This will be described according to the manufacturing process.
Using a bonding method (lamination method), a bonded SOI substrate including the silicon substrate 1, the silicon oxide film 2, and the SOI layer 3 is formed. The thickness of SOI layer 3 is 7 μm.

Here, the silicon oxide film 2 is preferably as thick as possible. Specifically, the thickness of the silicon oxide film 2 is preferably 1 μm or more. This is for reducing the capacitance of the parasitic capacitor formed by the SOI layer 3 and the silicon substrate 1 from which the element is separated.

Next, after a trench for element isolation reaching the silicon oxide film 2 is formed in the SOI layer 3, the trench is filled with the silicon oxide film 4 to perform element isolation. Since the capacitors are separated from each other by the silicon oxide films 2 and 4, the capacitors can be connected in series and in parallel without generating a parasitic element.

Next, boron is diffused into the SOI layer 3 at a high concentration to make the conductivity type of the SOI layer 3 a p-type with a high concentration.
A 5 μm deep trench of a trench capacitor is formed in the OI layer 3.

Here, the trench of the trench capacitor is formed after forming the trench for element isolation. However, the trench of the trench capacitor may be formed simultaneously when the trench for element isolation is formed. In this case, the trench of the trench capacitor also reaches the silicon oxide film 2.

Next, a silicon nitride film (not shown) having a thickness of 2 μm is formed on the entire surface by a rapid thermal annealing (RTA) method, and then a silicon nitride film having a thickness of 20 nm is formed on the silicon nitride film.
An m ₂ Ta ₂ O ₃ film 5 (Ta ₂ O ₃ has a dielectric constant 30 times higher than silicon) is formed by CVD.

That is, in this embodiment, a capacitor insulating film having a laminated structure having a higher dielectric constant than the silicon nitride film as a whole is used. As a result, a capacitor having a larger capacity than the conventional structure in which the insulating film and the capacitor insulating film constituting the SOI substrate are the same insulating film, that is, a silicon oxide film can be realized. Therefore, a large capacity can be secured without increasing the capacitor area. In other words, if the capacity is the same, a capacitor smaller than the conventional one is sufficient.

Note that Ta is used as a part of the capacitor insulating film.
_{Although the 2} O ₃ film 5 was used, a BSTO film may be used instead. When a high withstand voltage is not required, as shown in FIG. 2, a thin thermally oxidized silicon film (SiO ₂ film) 5a and a silicon nitride film (Si ₃
The same effect can be obtained by using a laminated film with the N ₄ film) 5b. Further, as shown in FIG. 3, the thermally oxidized silicon film 5a
A stacked film of a silicon nitride film 5b and a thermally oxidized silicon film 5a may be used. In this case, the silicon oxide film 2 preferably has a thickness of 1 μm or more.

Next, after performing an annealing process, Ta ₂ O
₃ A TiN film 6 having a thickness of 100 nm is formed on the film 5 by a sputtering method to fill the trench. Finally, unnecessary portions of the silicon nitride film, Ta ₂ O ₃ film 5 and TiN film 6 are removed by etching to complete the capacitor.

Here, in order to effectively increase the capacitance of the capacitor without increasing the area, the planar pattern of the trench capacitor is important. In order to effectively increase the capacitance, for example, as shown in FIG.
Is formed in a stripe shape, and such a stripe-shaped trench 10 is formed in an array of 5 rows and 2 columns, and the longitudinal direction and the column direction of the trench 10 are made to coincide with each other.

The length of the trench 10 in the longitudinal direction (stripe direction) is preferably about 10 to 100 μm, and the length in the direction (width direction) perpendicular to the longitudinal direction of the trench 10 is 7 μm.
m is preferable.

Since the SOI layer 3 is used as a capacitor electrode, boron is doped to reduce its resistance. However, to further reduce the resistance, the Al wiring 11 having a plane pattern as shown in FIG. It is preferable to provide the layer 3.

By using the trenches 10 and the Al wirings 11 having such a plane pattern, a capacitor having a large capacity that operates at a high frequency can be realized without particularly increasing the area.

FIG. 5 is a sectional view showing the element structure of a lateral MOSFET as a switch used in a switched capacitor type DC-DC converter according to an embodiment of the present invention.

The withstand voltage required for the switch when the capacitors are connected in parallel is the output voltage (low voltage) of the switched capacitor, but the withstand voltage required for the switches when the capacitors are connected in series is high.
High breakdown voltage elements are more expensive than low breakdown voltage elements.

Therefore, in the present embodiment, a switch in which two low-voltage lateral MOSFETs are connected in series is used as one switch, and such a lateral MOSFET is formed on the same bonded SOI substrate as the capacitor. I have. The SOI layer 3 is doped with a p-type impurity such as boron, and has a p-type conductivity.

A p-type base layer 21 is selectively formed on the surface of SOI layer 3, and an n-type source layer 22 having a high impurity concentration is selectively formed on the surface of p-type base layer 21. I have. The n-type source layer 22 and the p-type base layer 2
1 is provided with a source electrode 23 that contacts both of them.

An n-type RESURF layer 24 is selectively formed on the surface of the SOI layer 3, and an n-type drain layer 25 having a high impurity concentration is selectively formed on the surface of the n-type RESURF layer 24. Have been. A drain electrode 26 is provided on the n-type drain layer 25.

A gate electrode 25 is provided on the p-type base layer 21 sandwiched between the n-type source layer 22 and the n-type RESURF layer 24 via a gate insulating film (not shown). Here, when both the source potential and the drain potential become higher than the substrate potential and the depletion layer 27 formed below the n-type drain layer 25 reaches the silicon oxide film 2, the on-voltage increases, and the on-resistance increases. Become.

Such an increase in on-resistance is not preferable for the present element in which both the source potential and the drain potential are different from the substrate potential (ground potential) and have a high potential exceeding the withstand voltage of the element. That is, the on-resistance when the element is turned on must be small.

An increase in on-resistance due to the depletion layer 27 reaching the silicon oxide film 2 can be prevented by optimizing the impurity concentration and thickness of the SOI layer 3. This optimization is performed, for example, when the thickness of the depletion layer 27 is
It is determined from the condition that the thickness must be smaller than the thickness 1 (cm) of the lower p-type SOI layer 3. That is, in this optimization, the thickness l (cm) of the SOI layer 3 and the impurity concentration N _A (cm ⁻³ ) of the SOI layer 3 are set so as to satisfy the following expression.

{(2ε _s · V _SD ) / (q · N _A )} ^1/2 <l In the above equation, ε _s is the dielectric constant of silicon (= 1.05 ×
10 ⁻¹² F / cm), q is the elementary charge (= 1.6 × 10 ⁻¹⁹⁾
C) and V _SD are voltages (V) applied between the source and the drain.

In order to increase the breakdown voltage, it is usually necessary to provide a buried semiconductor layer, which causes an increase in cost. However, the above-described optimization makes it possible to increase the breakdown voltage without increasing the cost.

A switch directly connected to a power supply, for example, a switch 9 in the case of a switched capacitor shown in FIG.
5 _1, 95 ₂ need to withstand high voltages. Also in this case, if the impurity concentration and the thickness of the SOI layer 3 are optimized and the on-resistance is sufficiently reduced even when the power supply voltage is applied to the n-type drain layer 25, the withstand voltage of the element can be reduced. Can be secured by reducing the length of. That is, the required breakdown voltage can be ensured only by changing the dimensions of the n-type RESURF layer 24 while keeping the element structure the same. Therefore, horizontal MO
The area of the SFET region (switch region) does not need to be increased.

The connection between the trench capacitor and the lateral MOSFET is made, for example, as shown in FIG.
6 may be formed of TiN and formed integrally with the capacitor electrode (TiN film 6).

FIG. 7 is a sectional view showing an element structure of a lateral MOSFET as a switch used in a switched capacitor type DC-DC converter according to another embodiment of the present invention. Parts corresponding to those in FIG. 5 are denoted by the same reference numerals as in FIG. 5, and detailed description is omitted. As the capacitor, the same trench capacitor as in the previous embodiment is used.

This embodiment is different from the previous embodiment in that
The device structure is formed in the p-type well 31 without using the p-type base layer. That is, the device structure of the above embodiment is generally formed by a DMOS process, but the device structure of the present embodiment can be formed by a CMOS process which is easier in terms of process.

In the case of an n-channel type lateral MOSFET which requires an element breakdown voltage of about 10 V or less, as shown in this embodiment,
A lateral MOSFET without a mold base layer can be used. In this case, for example, an n-channel type lateral MOS
If the withstand voltage of the FET is 5 V and the voltage is to be converted from 150 V to 5 V, a single switch in which 30 n-channel lateral MOSFETs are connected in series to 150 V is used.
Ensure the pressure resistance of

The present invention is not limited to the above embodiment. For example, in the above-described embodiment, a DC-DC converter has been described as a semiconductor device having a structure in which a plurality of trench capacitors are connected directly or in parallel by a lateral MOSFET according to conditions.
The present invention can be applied to other semiconductor devices. For example, a lateral IGBT may be used instead of the lateral MOSFET. In addition, various modifications can be made without departing from the scope of the present invention.

[0054]

As described above in detail, according to the present invention, a structure in which a plurality of capacitors are connected directly or in parallel by switching elements according to conditions is formed in a semiconductor layer provided on an insulating film. Since a trench type capacitor is used as a capacitor and a lateral MOSFET is used as a switching element, and these element regions are separated by element separation / separation grooves, miniaturization can be easily performed.

[Brief description of the drawings]

FIG. 1 is a sectional view of a capacitor used in a switched capacitor type DC-DC converter according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a modification of the trench capacitor of FIG. 1;

FIG. 3 is a sectional view showing another modification of the trench capacitor of FIG. 1;

FIG. 4 is a plan view showing a plane pattern of the trench capacitor of FIG. 1;

FIG. 5 is a sectional view showing an element structure of a lateral MOSFET as a switch used in a switched capacitor type DC-DC converter according to an embodiment of the present invention.

FIG. 6 shows the trench capacitor of FIG. 1 and the lateral MOS of FIG.
Sectional view showing connection method with FET

FIG. 7 is a sectional view showing an element structure of a lateral MOSFET as a switch used in a switched capacitor type DC-DC converter according to another embodiment of the present invention.

FIG. 8 is a conventional switched capacitor type high voltage DC.
-DC converter equivalent circuit

[Explanation of symbols]

1 ... silicon substrate 2 ... silicon oxide film 3 ... SOI layer 4 ... silicon oxide film 5 ... Ta ₂ O ₃ film 6 ... TiN film 10 ... trench 11 ... Al wiring 21 ... p-type base layer 22 ... n-type source layer 23 ... Source electrode 24 ... n-type RESURF layer 25 ... n-type drain layer 26 ... drain electrode 27 ... depletion layer 31 ... p-type well

Claims (7)

[Claims] A semiconductor layer provided on the insulating film and separated into a plurality of capacitor regions and a plurality of switch regions by an element isolation groove reaching the insulating film; and an element isolation insulating film filling the element isolation groove. A groove-type capacitor formed in each of the plurality of capacitor regions; and switching means formed in each of the plurality of switch regions and connecting the plurality of groove-type capacitors in series or in parallel according to conditions. A semiconductor device, comprising: 2. The semiconductor device according to claim 1, wherein said groove type capacitor has a plurality of grooves, and a planar pattern thereof is a pattern in which a stripe pattern is repeated in a direction perpendicular to the stripe direction. . 3. The semiconductor device according to claim 1, wherein said insulating film is a silicon oxide film, and said capacitor insulating film of said trench type capacitor is an insulating film having a higher dielectric constant than a silicon nitride film. 4. The semiconductor device according to claim 1, wherein one of the capacitor electrodes of the trench capacitor is formed of a conductive layer. 5. The switching device according to claim 1, wherein said switching means is a lateral MOSFET.
The semiconductor device according to claim 1, wherein: 6. The semiconductor device according to claim 6, wherein the thickness of the semiconductor layer below the drain layer of the lateral MOSFET is 1 (cm), the impurity concentration of the semiconductor layer is N _A (cm ⁻³ ), and the dielectric constant of the semiconductor layer is ε (F / cm). ), the voltage V _SD is applied between the drain and the source of the lateral MOSFET, the elementary charge when the q (C), {(2ε s · V SD) / (q · N a)} 1/2 The semiconductor device according to claim 5, wherein a condition of <l is satisfied. 7. The switching means connects the plurality of grooved capacitors in series when connecting the plurality of grooved capacitors to a power supply, and connects the plurality of grooved capacitors when disconnecting the plurality of grooved capacitors from a power supply. 2. The semiconductor device according to claim 1, wherein the groove type capacitors are connected in parallel.