JP2006350868A - Signal processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processor which can be efficiently developed. <P>SOLUTION: A controller 140 in a main system 110 of a signal processor 100 converts audio-visual data 136 processed by a processor 120 into a first signal group in a common form capable of being transferred by a transfer unit 150 then the transfer unit 150 transfers it to a developing interface 160. The interface 160 develops the first signal group to a second signal group appropriate for a specified application. The first signal group has a bus width narrower than that of the second signal group. The system 110 and the interface 160 are built in different semiconductor integrated circuits, respectively. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a signal processing apparatus that performs signal processing, specifically, processing for converting data, particularly streaming data, into a signal group suitable for a predetermined application.

  Conventionally, high-rate stream data has been processed by a dedicated hardware processing device having a fixed function. Since these dedicated hardware processing devices depend on the type of data, an input / output interface is prepared for each type of data, and a dedicated pin is also assigned when handling low-speed data.

On the other hand, with the high integration of semiconductors, the performance of general-purpose processing devices with high programmability has advanced, and such general-purpose processing devices can handle streaming data that has been processed by dedicated hardware processing devices. Became possible. In addition, with the generalization of processing devices, it has become possible to handle many types of data with a single device.
In addition, with the further enhancement of performance of general-purpose processing devices, the streaming data to be handled tends to become higher rates, including higher resolution of video and higher frame rate.

Streaming data input / output interfaces such as cameras and displays differ depending on the set specification, and high-speed devices such as storage and network are connected to these input / output interfaces.
On the other hand, general-purpose processing devices such as processors process not only streaming data but also various other data.

Therefore, a main system realized by a processor and a chip set of a general-purpose processing device or a SoC (System on Chip) in which they are integrated requires many pins and the circuit becomes complicated. The general-purpose processing equipment originally has a tendency to increase the scale of the circuit and increase the development scale and development cost as the performance of the general-purpose processing equipment increases. Accelerate further.
Although it is nice to be able to handle many types of data with a single general-purpose processing device, the number of pins required is further increased by preparing a dedicated input / output interface for each data type. End up.

  As a method for separating a general-purpose processing device and an extended portion that differs for each set specification, there is a method of mounting a streaming data processing device on the end of a general-purpose expansion interface such as PCI Express. However, according to a higher data rate. The connection destination device requires a large-capacity buffer for absorbing jitter, the structure of the device itself becomes complicated, and the cost and power consumption increase.

  The present invention has been made in view of such circumstances, and provides a signal processing device that can reduce the burden of development.

  One embodiment of the present invention relates to a signal processing device. This signal processing apparatus inputs data, inputs a conversion transfer unit that converts and outputs the first signal group based on a predetermined conversion rule, and a first signal group output from the conversion transfer unit, An application-specific expansion unit that expands to a second signal group suitable for a specific application, wherein the conversion rule is defined in common for a plurality of applications including the specific application, and the first signal group is a second signal group. The signal transfer group is formed as a signal group having a narrower bus width than the other signal group, and the conversion transfer unit and the application specific development unit are incorporated in a separate semiconductor integrated circuit.

  A signal processing apparatus according to another aspect of the present invention includes a main processor, a main memory that holds data processed by the main processor, and data that is input from the main memory and temporarily stored in the built-in buffer. Based on a predetermined conversion rule, a conversion transfer unit that converts the data into a first signal group and outputs the first signal group output from the conversion transfer unit is input, and a second signal that is suitable for a specific application is input. The conversion rule is defined in common for a plurality of applications including the specific application, and the first signal group has a narrower bus width than the second signal group. The signal transfer unit and the conversion transfer unit and the application-specific development unit are respectively incorporated in separate semiconductor integrated circuits mounted on a single printed circuit board.

  Here, the data input to the signal processing apparatus according to the aspect of the present invention may be, for example, streaming data. “Streaming data” means continuous data requiring low jitter, such as uncompressed or compressed viewing data, input data from a sensor used for real-time control. “Viewing data” means video data, audio data, or the like that can be perceived when played, and generally means what can be perceived visually or auditorily. It may be one that can be sensed by a perception other than hearing.

  According to such an aspect of the present invention, the conversion and transfer unit converts the first signal group into the second signal group having a narrower bus width than the first signal group. The number of signal lines between the separate conversion units can be reduced, and the number of pins used by the conversion transfer unit can be reduced. In addition, since the conversion rule of the conversion / transfer unit is general-purpose, the conversion transfer unit can be shared for different purposes. Furthermore, since the conversion transfer unit and the application-specific conversion unit are separate bodies, another application can be realized by replacing only the application-specific development unit.

  In addition, what substituted the component and expression of this invention between methods, systems, etc. is also effective as an aspect of this invention.

  The present invention is advantageous in the development of a signal processing device.

  Conventional signal processing apparatuses convert an LSI (including a plurality of LSIs arranged in parallel) that acquires and outputs a baseband signal, and a baseband signal according to the application (for example, the type of output destination device). The output interface is directly connected to the output interface. For example, when developing a signal processing apparatus for outputting a signal to device A, an LSI that acquires and outputs a baseband signal, and a baseband signal from the LSI are received and converted according to the type of device A. The conversion interface is designed to match the device A. For device B, an LSI that acquires and outputs a baseband signal and a conversion interface are designed to match device B. Furthermore, even when there is a change in the specification of the output destination device, it may be necessary to redesign the acquisition output LSI or conversion interface in accordance with the new specification of the device. Therefore, it takes time and effort to design and remanufacture the acquisition output LSI and conversion interface for each type of device and for each specification as necessary. Furthermore, as described above, the number of pins of the acquisition output LSI and the conversion interface is large and the structure is complicated in the background of high-speed streaming data including viewing data such as images and sounds and high frame rates. In developing, troublesome problems are further accelerated, and the burden on the developer is increased. Therefore, problems such as higher development cost and longer development period may occur.

  In order to solve the above problem, the present inventor converts a baseband signal between a side that transmits streaming data to be a baseband signal and a conversion interface side that converts the streaming data in accordance with a specific application. Signal processing by providing conversion means for converting based on a conversion rule (hereinafter referred to as a common conversion rule) commonly defined for a plurality of uses including a specific use, and making the streaming data transmission side generalized The following technology is proposed based on the basic idea that the apparatus can be developed by dividing it into a general-purpose processing part and a dedicated processing part. FIG. 1 shows an overview of this technique.

First, a conversion transfer unit 10 corresponding to the conversion means described above is provided. The conversion / transfer unit 10 converts the streaming data into the first signal group according to the common conversion rule.
The application-specific expansion unit 30 that expands the first signal group into a second signal group suitable for a specific application is incorporated in a semiconductor integrated circuit separate from the semiconductor integrated circuit in which the conversion transfer unit 10 is embedded. To provide. Further, the conversion / transfer unit 10 forms the first signal group having a narrower bus width than the second signal group. The first signal group is output to the application development unit 30 via the transfer bus 20.

  FIG. 2 is a flowchart showing an outline of processing by each configuration shown in FIG. As shown in the figure, the streaming data input to the conversion / transfer unit 10 is converted into the first signal group by the conversion / transfer unit 10 according to the common conversion rule (S10, S12). The first signal group is output to the application development unit 30 via the transfer bus 20 (S14), and is converted into a second signal group suitable for the specific application by the application development unit 30 (S16). Then, the second signal group is output to the output destination device, and the process ends (S20).

  That is, according to this configuration, the streaming data is once converted into the first signal group according to the common conversion rule, and then output to the application-specific development unit 30. Here, the specifications of the conversion transfer unit 10 and the application development unit 30 are fixed for one product, and the specifications of the conversion transfer unit 10 and the application development unit 30 are changed when developing another product. Although necessary, since the conversion and transfer unit 10 converts the streaming data according to the common conversion rule, the specification can be easily changed.

Further, when the conversion / transfer unit 10 is configured so that the change can be performed by software, there is no change in the hardware part of the conversion / transfer unit 10 when developing another product, so the product changes. However, it is not necessary to change the hardware part of the conversion transfer unit 10.
Further, since the first signal group has a narrower bus width than the second signal group, the number of pins of the conversion / transfer unit 10 and the application-specific development unit 30 can be reduced.

  Further, since the first signal group has a narrower bus width than the second signal group, the number of signal lines of the transfer bus 20 is small, and the circuit scale can be reduced.

  Furthermore, since the conversion transfer unit 10 and the application development unit 30 are built in separate semiconductor integrated circuits, different applications can be realized by replacing only the application development unit.

  From the above, such a configuration can reduce the burden of developing a signal processing device, and is advantageous in either reducing the development cost or shortening the development period.

The best mode for carrying out the present invention will be described below.
FIG. 3 is a block diagram showing the configuration of the signal processing apparatus 100 according to the embodiment of the present invention. As shown in the figure, the signal processing apparatus 100 of this embodiment includes a main system 110 and a deployment interface 160, and a transfer unit 150 that transfers data is provided between the main system 110 and the deployment interface 160. ing. The main system 110 and the deployment interface 160 are built in separate semiconductor integrated circuits and mounted on a single printed circuit board.

  The signal processing apparatus 100 is a specific example that realizes the configuration shown in FIG. 1. The main system 110, the transfer unit 150, and the expansion interface 160 are the conversion transfer unit 10, the transfer bus 20, and the application-specific expansion unit 30 in FIG. Correspond to each.

  For the sake of simplicity, the transfer unit 150 is shown in the figure, but in the signal processing device 100 of this embodiment, the transfer unit 150, the connection between the transfer unit 150 and the main system 110, the transfer A connection portion between the unit 150 and the development interface 160 is shielded by any component on the printed circuit board, for example, a part of the main system and a part of the development interface 160 so that a signal pattern transferred by the transfer unit 150 is not visible. ing. By doing so, unauthorized use of a signal output from the main system 110 side or a signal transferred by the transfer unit 150 can be prevented and security can be improved.

  The main system 110 includes a processor 120, a main memory 130, and a controller 140. The processor 120 performs the following processing.

  1. Software such as a multimedia application is executed to obtain streaming data suitable for a specific application, for example, viewing data 136 such as image data and audio data. Note that the signal processing apparatus 100 of the present embodiment handles real-time viewing data, and the viewing data 136 is hereinafter referred to as real-time data 136.

  2. The controller 140 is controlled to generate control data 134 for processing performed by the controller 140, and the real-time data 136 is encapsulated with the control data 134.

  The main memory 130 holds control data 134 and real time data 136 obtained by the processor 120.

  The controller 140 includes a sequencer 144 and a buffer 146, acquires control data 134 from the main memory 130 according to the control of the processor 120, and reads real-time data 136 from the main memory 130 based on the control data 134. Here, the control data 134 created by the processor 120 is related to the process in which the controller 140 reads data from the main memory 130, such as the address and size in the main memory 130 of the real-time data 136 to be read by the controller 140. Information related to the process for the controller 140 to output the real-time data 136 to the expansion interface 160, such as information specifying the control command to be transmitted to the controller 140, the timing for transmitting the real-time data 136 read from the main memory 130, and the transfer rate. There is something to do. The sequencer 144 of the controller 140 reads the real time data 136 from the main memory 130 based on the control data 134 and temporarily stores it in the buffer 146. The sequencer 144 interleaves the real-time data 136 stored in the buffer 146 and the control command specified by the control data 134 and is specified for the real-time data 136 in a format that can be transferred by the transfer unit 150. The data is output to the transfer unit 150 at the same timing or transfer rate.

Hereinafter, for convenience of explanation, a signal group sent from the controller 140 is referred to as a first signal group.
Here, since the controller 140 temporarily stores the real-time data 136 in the buffer 146, it is possible to absorb jitter generated in the memory interface or the internal bus. That is, the first signal group is one in which jitter is absorbed.

The first signal group output from the controller 140 is transferred to the expansion interface 160 by the transfer unit 150, and the expansion interface 160 expands the first signal group and outputs it to the output destination device. Hereinafter, the signal group obtained by the expansion interface 160 is referred to as a second signal group.
Here, the details of the transfer unit 150 will be described, and the operation of the sequencer 144 of the controller 140 and the details of the first signal group will be described.

  FIG. 4 shows a configuration example of the transfer unit 150. The transfer unit 150 includes a CLK signal line 152 (152a: CLK +, 152b: CLK−) for transferring a normal phase and a reverse phase clock signal CLK for synchronization, a data bus 154 for transferring a data signal, and a CTRL signal. CTRL signal line 156 for transferring, and INT signal line 158 for transferring interrupt signal INT. Of the signals transferred by the transfer unit 150, only the INT signal is transmitted from the slave side, here the expansion interface 160 side, to the master side, here the main system 110 side.

  FIG. 5 is a diagram for explaining signals transferred by each bus of the transfer unit 150. Here, as an example, the data signal is 16 bits, and the data bus 154 also has a bus width of 16 bits. However, for example, the number of bits of the data signal may be 8 bits.

CLK is a clock signal for synchronization as described above, and is supplied from, for example, an external clock generator (not shown).
The data signal is a DDR (Double Data Rate) signal that includes real-time data and a control command and changes at the rising edges of the clock signals CLK + and CLK−.

  The CTRL signal indicates whether the signal flowing through the data bus 154 is a control command or real-time data. When the CTRL signal is 1 or 0, it indicates that the signal is a control command or real-time data.

As shown in FIG. 5, the INT signal is a high-active signal for notifying the main system 110 when a predetermined event occurs on the development interface 160 side.
Here, the first signal group described above includes a CLK signal, a data signal, and a CTRL signal, and the sequencer 144 of the controller 140 converts the real-time data 136 into the first signal group based on the control data 134. Convert.

  FIG. 6 shows a timing chart in which these signals are transferred when 16-bit image data is taken as an example of real-time data. As shown, when the data signal changes at the rising edge of the clock signal CLK and the CTRL signal is 0, RGB data is transmitted, and when the CTRL signal is 1, a control command is transmitted.

  The control command is determined for each image, sound, and other real-time data, and differs depending on the type of the real-time data. Here, in the signal processing apparatus 100 of the present embodiment, the control command is determined in common for all the real-time data. The control command given will be described.

FIG. 7 illustrates various commands commonly defined for real-time data.
The “No Operation” command is used to instruct that no operation is performed and to adjust the timing. In the data of this command, the most significant bit is 0, and data of other bits is arbitrary.

  The “Change Channel” command indicates that the data string having the number designated by “channel” (b) in the command is output by the number of cycles designated by “size”. Since the signal processing apparatus 100 of the present embodiment transfers real-time data having a plurality of channels via one 16-bit data bus 154, a number is assigned to each channel of real-time data and the number is designated. Reserve real-time channel to send by. That is, a “virtual channel” in which real-time data of a plurality of channels is transmitted by a single bus is realized by switching and transmitting the data of each channel of real-time data having a plurality of channels.

  During the cycle designated by “size” in this command, the bandwidth of the data bus 154 is reserved for the designated channel (number). In this embodiment, this command is valid only when the bandwidth is not reserved for any channel. By doing so, it is possible to transmit real-time data of a default channel using channel 0 by defining that channel 0 is selected when a band is not reserved. When transmission of the data of the channel reserved by this command is completed for the designated cycle, the state returns to the state where the band is not reserved, that is, the channel 0 is selected.

  The “Set upper Address” command, although not shown, sets an upper address of this register when a register for control is mounted on the expansion interface 160. For example, the upper 12 bits of the address space of the register can be set by “address” (a) in this command.

  The “Write register” command instructs to write data to the register specified by “data” in the lower 12-bit area specified by the “Set upper Address” command and “address” described above. Here, the 12 bits are set because the bus width of the data bus 154 is only 16 bits.

  The “Assert Single” command is a command for asserting the control signal designated by “singal” in the command, that is, a command for setting the value of the control signal to 1.

  The “Deassert Single” command is a command for deasserting the designated control signal by “singal” in the command, that is, a command for setting the value of the control signal to 0.

  The control signal specified by “singal” in the “Assert Singal” command and the “Deassert Singal” command differs depending on the type of real-time data. For example, in the case of image data, the control signal includes a “VSYSNC” signal, “HSYNC” signal, and “HSYNC” signal. ”Signal and the like, and in the case of audio data, there is an example of a“ MUTE ”signal as the control signal.

In the foregoing, examples of commands commonly defined for real-time data have been described. Of course, other commands such as providing a user reserve command may be defined.
Real-time data is transmitted when the CTRL signal is deasserted, that is, when its value is zero.

  Different types of real-time data are handled depending on the product. In any product, real-time data is converted according to a common conversion rule of conversion into a first signal group consisting of a CLK signal, a data signal, and a CTRL signal. The transfer format is different. FIG. 8 exemplifies formats for transferring each type of image data. According to these formats, any bandwidth data can be transferred via the data bus 154 having a 16-bit bus width.

  For example, in the case of RGB data having 9 to 16 bits, the transfer format is R → G → B. Since the bus width of the data bus 154 is 16 bits, when the number of bits of the image data is less than 16, the lower bits are truncated on the receiving side, here, the development interface 160 side. For example, when the number of bits of RGB data is 12 bits, the expansion interface 160 truncates the lower 4 bits of each received R, G, B signal.

  On the other hand, when the image data is 8-bit RGB data, taking two pixels (R1G1B1 and R2G2B2) as an example, the transfer format is “R1G1” → “B1” → “R2G2” → “B2”. Can do. Of course, when this transfer format is used, since the lower 8 bits of B are truncated, the bus width of the data bus 154 is used more effectively by using a transfer format such as “R1G1” → “B1R2” → “G2B2”. However, the transfer efficiency may be improved.

  For example, when the image data is YCrCb (Y: Cr: Cb = 4: 2: 2) data of 9 bits or more and 16 bits or less, it can be transferred as “Y” → “CrCb”. When transferring CrCb, the lower 8 bits and the upper 8 bits of the data bus 154 may be assigned to Cr and Cb, respectively. As in the case of RGB data, when the number of bits is less than 16 bits, the corresponding lower-order bits may be discarded on the development interface 160 side.

  On the other hand, when the image data is 8-bit YCrCb data, one pixel can be transferred at a time, such as “YCrCb”.

The format of the “Assert Single” command and the “Deassert Single” command when transferring image data can be, for example, as follows:
bit0: VSYNC
bit1: HSYNC
bit2: CSYNC
bit3: VBLANK
bit4: HBLANK
bit5: FLD0 (Field Out Single)
bit6-12: reserved

  In this embodiment, the sequencer 144 in the controller 140 on the main system 110 side synchronizes the audio data with the image data, and then outputs it to the transfer unit 150. Since jitter generated after the transfer unit 150 is very small, it is not necessary to use a signal for synchronization control when transferring audio data.

  Also, when transferring audio data, for example, 8-bit, left and right channel data may be transferred all at once, but in this embodiment, audio data is transferred channel by channel. For example, audio data is 8 bits, and 2-channel data is assigned with a number (virtual channel) assigned to each channel. By doing so, for example, multi-channel audio data having more than two channels can be multiplexed and output from the array speaker.

  In addition, the transfer format of the “Assert Single” command and the “Deassert Single” when transferring the audio data can be “bit 0: mute, bit 1-15: Reserved”.

  The sequencer 144 of the controller 140 converts any type of real-time data into a first signal group that can be transferred by the same transfer unit 150 and outputs the first signal group to the transfer unit 150 in this way. Since the controller 140 is provided with a buffer 146 that temporarily stores the viewing data 136, the sequencer 144 uses the “No Operation” command described above when a signal timing shift, that is, jitter occurs. By transmitting dummy data, the timing can be adjusted and jitter can be absorbed.

  The expansion interface 160 expands the signal transmitted via the transfer unit 150 into a second signal group suitable for the application, and outputs the second signal group to the output destination device.

  FIG. 9 is a block diagram showing the configuration of the deployment interface 160. The expansion interface 160 includes a expansion unit 164 that expands the first signal group transmitted via the transfer unit 150 into a second signal group, and a pin that outputs each signal included in the second signal group. 168. In the illustrated example, the development interface 160 uses the development unit 164 to develop the first signal group into image signals Y, Cr, Cb, and audio signals L (left) and R (right), and corresponding pins 168a. (Y), 168b (Cr), 168c (Cb), 168d (L), and output to 168e (R). These pins 168 are provided in accordance with the output destination device, and by connecting to the corresponding pins in the output destination device, each signal can be output to the output destination device.

  As described above, according to the signal processing apparatus 100 of the present embodiment, the main system 110 converts the viewing data 136 into 16-bit data and interlaces with the control command to obtain the first signal group. The first signal group is output to the expansion interface 160 via the transfer unit 150. The expansion interface 160 expands the received first signal group into a format suitable for the output destination device and outputs the first signal group. Since the main system 110 and the expansion interface 160 are connected by the transfer unit 150 having a general-purpose format, the main system 110 and the expansion interface 160 can be designed and developed separately.

In addition, since the first signal group has already absorbed jitter and is suitable for a specific application, for example, an output destination device, the deployment interface 160 can be realized by a small amount of buffer and a simple conversion circuit. it can.
Further, when there is a change in the type of the output destination device, it is necessary to change the hardware such as the output pin of the expansion interface in accordance with the output destination device, but the sequencer of the controller 140 in the main system 110 Since the operation of 144 can be changed by software, it is easy to change the specifications of the entire signal processing apparatus.

  Although one embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and various changes, increases / decreases, and improvements in details can be added without departing from the spirit of the present invention. it can.

  For example, in order to make the gist of the present invention easier to understand, the signal processing apparatus 100 of the embodiment shown in FIG. 3 includes a sequencer 144 of the controller 140, a transfer unit 150, and a deployment unit 164 of the deployment interface 160. Although only one set (physical channel) is provided, a plurality of physical channels may be provided. By doing so, wideband image data can be transferred separately for each image data processing unit, for example, for each pixel, and high frame rate transfer can be realized. Here, as an example, the processing unit of image data is a pixel, and each pixel is transferred in order in separate physical channels. However, the processing unit of image data is a line or a frame, and a plurality of lines or frames are paralleled. Then, it may be transferred. Furthermore, the image area represented by the image data may be divided into blocks, the processing unit of the image data may be a block, and a plurality of blocks may be transferred in parallel.

  Of course, a signal processing apparatus provided with a plurality of physical channels can be effective not only for transferring wideband data at a high frame rate, but also for various uses. As an example, the main system transfers in parallel block image data to be displayed in different areas of the display screen of one image playback device, and the development interface transfers the received data of each block image to the image playback device. Output to the corresponding area and display in the corresponding area, it is possible to realize multi-screen display by an image reproducing device such as a monitor or a television set.

  Furthermore, by adjusting the number of physical channels for transferring each block image, the update frequency of different block images on one display screen can be made different. For example, assuming that the display screen of a game fighting on the stage is composed of the stage area and a description of the game or a simple background area, the image of the stage area has a high update frequency. The image of the area such as does not need a high update frequency. In this case, for example, the image data of the area such as the background may be transferred using one physical channel, and the image data of the stage area may be transferred using two or more physical channels.

  Further, the main system divides the image area represented by the image data into blocks and transfers a plurality of blocks in parallel, and the development interface outputs the received data of each block to different image reproduction apparatuses. In this way, one piece of image data can be divided and displayed on a plurality of image reproduction apparatuses.

  In the signal processing apparatus 100 of the embodiment shown in FIG. 3, the main system 110 and the expansion interface 160 have only a transmission / reception channel for viewing data transmitted from the main system 110 to the expansion interface 160. A transmission / reception channel for viewing data transmitted to the main system may be further provided. By doing so, it is possible to realize a system capable of bidirectional transfer in which viewing data from a device connected to the development interface can also be transferred to the main system through the development interface.

  In addition, in the signal processing apparatus 100 shown in FIG. 3, in order to improve security, the transfer unit 150 and the connection between the transfer unit 150 and other parts so that the pattern of the signal transferred by the transfer unit 150 is not visible. Although the portion is shielded by components on the same printed circuit board, the transfer unit or the like may not be shielded if it is intended for use in an environment where security is not particularly considered.

  In order to further enhance security, the main system 110 may encrypt and output the signal group to be output, that is, the first signal group.

  In the signal processing apparatus 100 shown in FIG. 3, the main system 110 and the development interface 160 are mounted on the same printed circuit board and are connected by a transfer unit 150 including signal lines such as a data bus 154. Alternatively, the main system 110 and the deployment interface 160 may be mounted on separate printed circuit boards, and both may be connected by a connector. When the connector is used for connection, the security is lower than that of the signal processing apparatus 100 shown in FIG. 3, but the deployment interface can be replaced more easily. Of course, in this case as well, security may be improved by encrypting a signal group output from the main system side.

Of course, specific control commands and transfer formats of image data and audio data are not limited to those exemplified above.
Further, the signal processing device according to the present invention can exert its effect particularly in the processing of streaming data that requires low jitter, but the processing target of the signal processing device of the present invention is not limited to streaming data, Any kind of data may be used.

It is a figure which shows the outline | summary of embodiment concerning this invention. It is a flowchart which shows the outline | summary of the process by each structure shown in FIG. It is a block diagram which shows the structure of the signal processing apparatus by embodiment of this invention. It is a figure which shows the structural example of the transfer part in the signal processing apparatus shown in FIG. It is a figure which shows the detail of the signal transferred by the transfer part shown in FIG. FIG. 5 is a diagram illustrating a timing chart of signals transferred by a transfer unit illustrated in FIG. 4. It is a figure which shows the example of a control command. It is a figure which shows the example of the transfer format of image data. It is a block diagram which shows the structure of the expansion | deployment interface in the signal processing apparatus shown in FIG.

Explanation of symbols

10 conversion transfer unit, 20 transfer bus, 30 development unit according to application, 100 signal processing device, 110 main system, 120 processor, 130 main memory, 134 control data, 136 viewing data, 140 controller, 144 sequencer, 146 buffer, 150 transfer Part, 160 unfolding interface 164 unfolding part, 168 pins.

Claims (9)

A conversion transfer unit that inputs data, converts the data into a first signal group based on a predetermined conversion rule, and outputs the first signal group;
An application-specific development unit that inputs the first signal group output from the conversion transfer unit and develops the first signal group into a second signal group suitable for a specific application;
The conversion rule is defined in common for a plurality of applications including the specific application, the first signal group is formed as a signal group having a narrower bus width than the second signal group, and
A signal processing apparatus, wherein the conversion transfer unit and the application-specific development unit are built in separate semiconductor integrated circuits.   The signal processing device according to claim 1, wherein the data is streaming data.   3. The signal processing apparatus according to claim 1, wherein the conversion transfer unit includes a built-in buffer, and once the data is input to the built-in buffer, the conversion processing to the first signal group is performed. Signal processing device.   4. The signal processing apparatus according to claim 1, wherein the separate semiconductor integrated circuit is mounted on a single printed circuit board. 5.   5. The signal processing apparatus according to claim 1, comprising a plurality of sets of conversion transfer units and application-specific development units.   6. The signal processing device according to claim 5, wherein the plurality of application-specific development units included in the plurality of sets share processing for the same application.   The signal processing device according to claim 6, wherein the plurality of conversion and transfer units included in the plurality of sets divide the image data into predetermined processing units and output the data in parallel, A signal processing apparatus that receives a processing unit and converts it into a second signal group.   8. The signal processing device according to claim 7, wherein the processing unit corresponds to a display unit of image data. A main processor;
A main memory for storing data processed by the main processor;
A conversion transfer unit that inputs data from the main memory and temporarily stores the data in the built-in buffer, and then converts the data into a first signal group based on a predetermined conversion rule;
An application-specific development unit that inputs the first signal group output from the conversion transfer unit and develops the first signal group into a second signal group suitable for a specific application;
The conversion rule is defined in common for a plurality of applications including the specific application, the first signal group is formed as a signal group having a narrower bus width than the second signal group, and
A signal processing apparatus, wherein the conversion transfer unit and the application-specific development unit are respectively built in separate semiconductor integrated circuits mounted on a single printed circuit board.

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