JP2004072344A - Data transmission system with multiplexed LVDS interface - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the number of physical signal lines on an interface by converting a signal whose frequency is < 20MHz by using an element utilizing LVDS technology to transmit the signals in the interface between image processors or the like. <P>SOLUTION: An LVDS transmitter part 12 in a data transmitter 10 multiplexes and converts signals such as a reference clock signal, a synchronizing signal and a data signal from an interface control part 11 by LVDS transfer clocks generated from an LVDS transfer clock generation part 13 into LVDS signals of which the number of signal lines is reduced and transfers the LVDS signals, and converts the LVDS transfer clocks as a group of LVDS signals and transfers the LVDS signal group. An LVDS receiver part 21 in a data receiver 20 demodulates the multiplexed LVDS signals sent from the LVDS transmitter part 12 by using the LVDS transfer exclusive clocks sent from the LVDS transmitter part 12 and sends the demodulated LVDS signals to an interface control part 22. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data transmission system using an LVDS (Low Voltage Differential Signaling) technology for an interface between devices that transmit and receive electronic data, and more particularly, to an image processing device such as a copy, fax, printer, or digital lab. Device-to-device interface, PCI (Peripheral Component Interconnect) bus, PCMCIA (Personal Computer Memory Card International Association) bus; LVDS technology for transmitting and receiving circuits With utilizing device, to a data transmission system with a reduced physical number of signal lines on the interface.
[0002]
[Prior art]
In order to transfer data at an interface between image processing apparatuses such as copy, fax, printer, and digital labs at high speed and with low power consumption, many electronic devices that employ LVDS (Low Voltage Differential Signaling) technology have been developed. ing. LVDS is a standard for signals transmitted between a central processing unit and an image display device, and is standardized as IEEE1596.3. In general, by reducing the number of physical signal lines of an interface connecting electronic devices, lower power consumption, lower EMI, and smaller size of the device can be realized, and the cost can be reduced. In an interface using the LVDS technology, an element for reducing the number of physical signal lines of the interface has been developed to simplify the configuration.
[0003]
FIG. 4 is a schematic circuit diagram of a typical device for converting a TTL / CMOS signal to an LVDS signal and a typical device for converting an LVDS signal to a TTL / CMOS signal. FIG. FIG. 4B is a circuit diagram of a transmitter (transmitter), and FIG. 4 (B) is a circuit diagram of a receiver (receiver). are doing. The transmitter shown in FIG. 4A generates an internal clock from the clock (CLOCK) of 20 MHz to 65 MHz by an internal PLL, and uses the internal clock to generate 6 bits of red (R) data and 6 bits of green (G) data. Bit, blue (B) data 6 bits, horizontal synchronization (HSYNC) 1 bit, vertical synchronization (VSYNC) 1 bit, data enable (DATA ENABLE) signal 1 bit, a total of 21 TTL / CMOS level signals, This is an element that performs parallel-to-serial conversion into three sets of LVDS level signals S1 to S3 and converts an input clock (CLOCK) into one set of LVDS level signals S4. The receiver shown in FIG. 4B performs serial-to-parallel conversion of the multiplexed three sets of LVDS-level signals S1 to S3 using the received clock S4, and sets 21 TTL / CMOS-level signals. Restore to signal.
[0004]
Japanese Patent Application Laid-Open No. 2000-152130 discloses a flat panel display system using elements similar to the elements shown in FIG. This flat panel display system reduces the effects of EMI and noise by converting TTL signals such as image data transmitted in the flat panel display system into LVDS signals, and also reduces the number of signal lines to reduce the number of components. And the number of wirings are reduced, enabling cost reduction.
[0005]
Generally, these elements are used for a high-speed interface for transmitting and receiving image data between a central processing unit and an image display device, and assume a high frequency clock of 20 MHz to 30 MHz or more (a reference clock of a signal to be transmitted). It is made. The frequency of this clock tends to increase with the advance of device technology.
[0006]
[Problems to be solved by the invention]
However, if the frequency of the reference clock of the signal transmitted between the devices is less than the clock frequency of the LVDS, for example, less than 20 MHz, the LVDS cannot be used.
[0007]
The present invention relates to an interface between image processing apparatuses such as copy, facsimile, printer, and digital lab, which converts a signal having a reference clock frequency of less than 20 MHz into a LVDS signal using an element utilizing the LVDS technology. And a data transmission system in which the number of physical signal lines on the interface is reduced.
[0008]
Further, the present invention has a problem that, when a reference clock of a signal to be transmitted is multiplexed with a signal other than the reference clock and transferred, the number of logical signals that can be transferred is reduced by the number of reference clocks. It is an object of the present invention to provide a data transmission system that solves the above.
[0009]
Further, the present invention has a problem that, when multiplexing and demodulating a signal to be transmitted, the multiplexed signal cannot be demodulated unless the signal is multiplexed using a clock having a frequency twice or more the maximum frequency of the signal to be transmitted. It is an object of the present invention to provide a data transmission system that solves such a problem.
[0010]
[Means for Solving the Problems]
The present invention is a data transmission system configured to transmit a plurality of signals, a data reception device receiving a signal transmitted from the data transmission device, and a data transmission system including an interface connecting the devices. An interface control unit for controlling an interface, an LVDS transmitter unit for multiplexing a plurality of signals from the interface control unit to reduce the number of signal lines and converting the number of signal lines to an LVDS signal level; An LVDS transfer-dedicated clock generator that generates an LVDS transfer-dedicated clock that can correspond to the input clock frequency of the LVDS transmitter, separately from a reference clock from a controller; From the multiplexed LVDS signal sent from The LVDS transfer dedicated clock transmitted from the serial data transmitting apparatus, characterized by comprising the LVDS receiver for demodulating the original signal, and an interface control unit for controlling the interface.
[0011]
Further, the data receiving apparatus includes a reference clock reproducing unit that reproduces a reference clock by dividing the frequency of an LVDS transfer dedicated clock from the LVDS receiver.
[0012]
Further, among the plurality of signals, a signal having a high frequency is transmitted through a signal path different from the LVDS transmission path.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a block diagram showing a configuration of an interface unit for explaining an embodiment of the present invention. In the figure, reference numeral 10 denotes a data transmission device for transmitting image data and the like, and reference numeral 20 denotes a data transmission device for transmitting data from the data transmission device 10. A data receiving device 30 for receiving the received image data and the like is an LVDS interface connecting these devices. The LVDS transmitter unit 12 of the data transmission device 10 converts a plurality of signals (hereinafter, referred to as “interface signals”) from the interface control unit 11 that controls the interface into an LVDS signal in which the number of signal lines is reduced. . Further, the LVDS transfer dedicated clock generation unit 13 generates an LVDS transfer dedicated clock which is an input clock of the LVDS transmitter unit 12. The LVDS transfer dedicated clock is a clock different from the reference clock of the interface signal from the interface control unit 11, and is set to the input clock frequency of the LVDS transmitter unit 12 (generally, 20 MHz or more or 30 MHz or more, and the frequency differs depending on the element). It is a clock of the corresponding frequency. The LVDS receiver unit 21 of the data receiving device 20 demodulates the LVDS signal sent from the LVDS transmitter unit 12 into an original signal by the LVDS transfer dedicated clock sent from the LVDS transmitter unit 12, and controls the interface. Send to interface control unit 22.
[0014]
The LVDS transmitter section 12 can be constituted by one or more transmitters such as DS90C363 and DS90C383 (manufactured by National Semiconductor), and the LVDS receiver section 21 is constituted by one or more receivers such as DS90CF364 and DS90CF384 (manufactured by National Semiconductor). Can be configured.
[0015]
Hereinafter, DS90C363 is provided in the LVDS transmitter section 12 and DS90CF364 is provided in the LVDS receiver section 21 one by one. The interface signals (reference clock signal, synchronization signal, data signal, etc.) from the interface control section 11 are 21 or less (signal lines) Is 21 or less).
[0016]
TTL / CMOS level parallel data signals such as a reference clock signal, a synchronization signal, and a data signal generated by the interface control unit 11 are input to the LVDS transmitter unit 12. The LVDS transmitter section 12 samples the parallel data signal every cycle of the LVDS transfer dedicated clock and converts it into three sets of LVDS serial signals, and converts the LVDS transfer dedicated clock into one set of LVDS signals. , To the data receiving device 20.
[0017]
The LVDS receiver unit 21 demodulates the three sets of LVDS serial signals sent from the LVDS transmitter unit 12 into the original parallel data signal by the LVDS transfer dedicated clock sent from the LVDS transmitter unit 12, and demodulates the interface control unit. Send to 22.
[0018]
FIG. 2 is a block diagram showing a configuration of an interface unit for explaining another embodiment of the present invention. Hereinafter, the above-mentioned DS90C363 and DS90CF364 are respectively provided in the LVDS transmitter unit 12 and the LVDS receiver unit 21. The case where interface signals (reference clock signal, synchronization signal, data signal, etc.) are 21 or less in total (21 or less signal lines) will be described as an example.
[0019]
A parallel data signal such as a synchronization signal and a data signal generated by the interface control unit 11 excluding the reference clock signal is input to the LVDS transmitter unit 12 together with the LVDS transfer dedicated clock in synchronization with the LVDS transfer dedicated clock. . The LVDS transmitter section 12 samples the parallel data signal every cycle of the LVDS transfer dedicated clock, converts it into three sets of LVDS serial signals, and converts the LVDS transfer dedicated clock into one set of LVDS signals. And transfer.
[0020]
The LVDS receiver unit 21 demodulates the three sets of LVDS serial signals sent from the LVDS transmitter unit 12 into the original parallel data signal by the LVDS transfer dedicated clock sent from the LVDS transmitter unit 12, and demodulates the interface control unit. 22. The LVDS transfer dedicated clock converted to the TTL / CMOS level by the LVDS receiver 21 is input to the reference clock reproducer 23. The reference clock reproducing unit 23 reproduces a reference clock signal by frequency division or PLL based on the input LVDS transfer dedicated clock, and inputs the reproduced signal to the interface control unit 22.
[0021]
If the skew between the reference clock signal reproduced by the reference clock reproducing unit 23 and the parallel data signal demodulated by the LVDS receiver unit 21 increases, the skew is reproduced again in the interface control unit 22. The parallel data signal may be fetched in synchronization with the reference clock signal.
[0022]
FIG. 3 is a block diagram showing a configuration of an interface unit for explaining still another embodiment of the present invention. Hereinafter, the above-described DS90C363 and DS90CF364 will be described in the LVDS transmitter unit 12 and the LVDS receiver unit 21, respectively. , The LVDS driver 14 and the LVDS receiver 24 are provided with one DS90LV047 and one DS90LV048 of National Semiconductor, respectively. Note that the DS90LV047 is a driver that converts a TTL / CMOS level signal into an LVDS signal for each signal, and is an element on which drivers for four circuits are mounted, and the DS90LV048 is a receiver element corresponding to this driver. .
[0023]
A parallel data signal such as a data signal excluding a high-frequency signal such as a reference clock among parallel data signals from the interface control unit 11 is input to the LVDS transmitter unit 12. The LVDS transmitter section 12 samples the input parallel data signal every cycle of the LVDS transfer dedicated clock, converts it into three sets of multiplexed LVDS serial signals, and also converts the LVDS transfer dedicated clock into one set of LVDS serial signals. Convert to signal and transfer.
[0024]
The LVDS receiver section 21 demodulates the three sets of LVDS serial signals sent from the LVDS transmitter section 12 with the LVDS transfer dedicated clock sent from the LVDS transmitter 12, converts them into parallel data signals, and converts them into parallel data signals. Transfer to
[0025]
Among the parallel data signals from the interface control unit 11, a high-frequency parallel data signal such as a reference clock is converted into an LVDS signal by the LVDS driver unit 14 for each signal and transferred. The LVDS receiver 24 returns the LVDS signal sent from the LVDS driver 14 to a TTL / CMOS level signal for each signal, and transfers the signal to the interface controller 22.
[0026]
The skew between a signal path for multiplexing and demodulating a signal excluding a high-frequency signal such as a reference clock and transmitting the same and a signal path for transmitting a high-frequency signal such as a reference clock without multiplexing and demodulating becomes a problem. In this case, the parallel data signal may be fetched again in the interface control unit 22 in synchronization with the received reference clock signal.
[0027]
In FIGS. 1 to 3, the data transmission device 10 is provided with a transmission circuit such as the LVDS transmitter unit 12 and the data reception device 20 is provided with a reception circuit such as the LVDS receiver unit 21. However, data transfer in the reverse direction is required. The case can be realized by further providing a receiving circuit in the data transmitting device 10 and a transmitting circuit in the data receiving device 20.
[0028]
【The invention's effect】
According to the present invention, it is possible to convert a signal whose transmission frequency is less than 20 MHz into an LVDS signal having a physically small number of signal lines and transmit the LVDS signal, thereby reducing power consumption and EMI of the device. It is possible to reduce the size and cost.
[0029]
In addition, since it is not necessary to multiplex a reference clock of a signal to be transmitted with a signal other than the reference clock and transfer the signal, the number of logical signals that can be transferred can be increased by the number of reference clocks.
[0030]
Further, the frequency of the clock of the element using the LVDS technology can be kept low, and the EMI of the device and the interface can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an interface unit for explaining an embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of an interface unit for explaining another embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of an interface unit for explaining still another embodiment of the present invention.
FIG. 4 is a schematic circuit diagram of a typical element that converts a TTL signal into an LVDS signal and a typical element that converts an LVDS signal into a TTL signal.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Data transmission apparatus, 11 ... Interface control part, 12 ... LVDS transmitter part, 13 ... LVDS transfer dedicated clock generation part, 14 ... LVDS driver part, 20 ... Data receiving apparatus, 21 ... LVDS receiver part, 22 ... Interface control part , 23... A reference clock reproducing unit, 24... An LVDS receiver unit, 30.

Claims (3)

A data transmission device configured to transmit a plurality of signals, a data reception device receiving a signal transmitted from the data transmission device, and an interface connecting the devices; Comprises: an interface control unit for controlling an interface; an LVDS transmitter unit for multiplexing a plurality of signals from the interface control unit to reduce the number of signal lines and converting the number of signal lines to an LVDS signal level; An LVDS transfer-dedicated clock generator that generates an LVDS transfer-dedicated clock that can correspond to the input clock frequency of the LVDS transmitter, separately from the reference clock; The multiplexed LVDS signal is converted to the data A data transmission system having a multiplexed LVDS interface, comprising: an LVDS receiver section for demodulating an original signal by an LVDS transfer dedicated clock sent from a communication device; and an interface control section for controlling an interface. . The multiplexed LVDS interface according to claim 1, wherein the data receiving device includes a reference clock reproducing unit that reproduces a reference clock by dividing a clock dedicated to LVDS transfer from an LVDS receiver unit. Data transmission system. The data transmission system according to claim 1, wherein a signal having a high frequency among the plurality of signals is transmitted through a signal path different from the LVDS transmission path.

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