JP2006261414A - Solid-state imaging device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To sufficiently suppress the occurrence of an image defect even if transistors included in a pixel portion and a peripheral circuit portion are simultaneously formed on the same substrate by applying a CMOS logic process, and can cope with pixel miniaturization. A solid-state imaging device excellent in image characteristics and a method for manufacturing the same are provided.
A solid-state imaging device in which a pixel unit and a peripheral circuit unit disposed around the pixel unit are formed on the same substrate. Each pixel includes first and second transistors, and the peripheral circuit unit 19 includes a plurality of third transistors. At least the residual stress below the transfer gate electrode 23a constituting the first transistor and below the gate electrode 23b constituting the second transistor is 37 MPa or less.
[Selection] Figure 1

Description

  The present invention relates to a solid-state imaging device and a manufacturing method thereof, and more particularly to a solid-state imaging device having an amplification MOS sensor and a manufacturing method thereof.

  A solid-state imaging device having an amplification type MOS sensor (hereinafter referred to as a MOS type solid-state imaging device) amplifies a signal detected by a photodiode for each pixel by a transistor, and has a feature of high sensitivity. FIG. 8 is a circuit diagram showing a configuration of a general MOS type solid-state imaging device. In FIG. 8, the MOS type solid-state imaging device includes a pixel unit 7 in which a plurality of pixels 6 are arranged in a matrix, and a peripheral circuit unit arranged around the pixel unit 7. Each pixel 6 constituting the pixel unit 7 is transferred with a photodiode 1 for accumulating charges according to the amount of received light, a transfer transistor 2 for transferring signal charges generated by the photodiode 1, and a reset transistor 3 for resetting signal charges. Amplifying transistor 4 that amplifies the signal charge and has a connection portion 8 to an external power supply, and a selection transistor 5 that selects a line for reading a signal.

  The peripheral circuit section includes a vertical selection section 9 that supplies a row selection signal, a load transistor group 10, a row signal storage section 11 that includes a switch transistor for capturing one row of signals, and a horizontal selection section that supplies a column selection signal 12 is included. A selection transistor control line 13, a reset transistor control line 14, and a transfer transistor control line 15 for connecting to each pixel 6 are wired in the vertical selection unit 9. The selection transistor control line 13 is connected to the gate electrode of the selection transistor 5 and determines a row from which a signal is read. The reset transistor control line 14 is connected to the gate electrode of the reset transistor 3, and the transfer transistor control line 15 is connected to the gate electrode of the transfer transistor 2. One end of a vertical signal line 16 for connection to each pixel 6 is wired in the load transistor group 10, and the other end of the vertical signal line 16 is coupled to the row signal storage unit 11. The vertical signal line 16 is connected to the source electrode of the selection transistor 5. Further, the signals accumulated in the row signal accumulation unit 11 are sequentially output by the selection pulse supplied from the horizontal selection unit 12.

As described above, in the MOS type solid-state imaging device, the pixel portion 7 and the peripheral circuit portion are formed on the same substrate. In such a MOS type solid-state imaging device, in recent years, a configuration in which a plurality of MOS type transistors having a CMOS (Complementary Metal-Oxide-Semiconductor) structure are arranged in the peripheral circuit unit has been applied for the purpose of improving the performance of the peripheral circuit unit. (For example, Patent Document 1). In such a MOS type solid-state imaging device, since a plurality of MOS type transistors included in the pixel unit 7 and the peripheral circuit unit have an on-chip structure, by adding a process of forming a photodiode to the CMOS logic process, A transistor included in the pixel portion 7 and a transistor included in the peripheral circuit portion can be formed at the same time. Therefore, there are advantages that the development period can be shortened, the cost can be reduced, and the power consumption can be reduced.
JP 2002-190586 A

  However, a MOS type solid-state imaging device manufactured by a method in which a process for forming a photodiode is added to a CMOS logic process does not sufficiently suppress image defects due to white scratches or dark current variations (dark roughness). There is a problem.

  Therefore, Patent Document 1 proposes a technique in which a gate electrode of a transistor included in each pixel 6 has a single layer structure of polycrystalline silicon and a gate electrode of a CMOSFET included in a peripheral circuit portion has a stacked structure. However, in such a method, there is a problem that a gate electrode having a silicide structure, which is being used for the purpose of suppressing leakage current, cannot be applied to each pixel 6 with the recent miniaturization of the pixel 6. The gate electrode having a silicide structure is a laminated film in which a silicide film such as a tungsten silicide (WSi) film is formed on a polycrystalline silicon film, and is a film compared to a gate electrode having a single-layer structure of polycrystalline silicon. This is because the residual stress of itself is large and affects the photodiode 1 and the like to deteriorate the image characteristics.

  In addition, with the miniaturization of the pixel 6 described above, in particular, in a MOS type solid-state imaging device having a fine structure of 0.25 μm or less, an element isolation region (STI structure isolation region) formed by an STI (Shallow Trench Isolation) method ( (Hereinafter referred to as STI), and the thickness of the gate insulating film constituting each transistor is reduced to 10 nm or less. Such an STI or a thinned gate insulating film is likely to generate residual stress due to a heat treatment performed after the formation of the gate electrode, specifically, a heat treatment performed in the step of forming the impurity diffusion layer in the peripheral circuit portion. Therefore, there is a problem that the residual stress on the photodiode 1 is large and it is difficult to suppress image defects.

  Therefore, in order to reduce the residual stress on the photodiode 1, a method of limiting the processing temperature during the heat treatment is used. Generally, a heat treatment method called RTA (Rapid Thermal Annealing) is applied to such a heat treatment, and the optimum heat treatment is performed by performing the heat treatment under a temperature condition not exceeding 900 ° C. in this RTA. It is planned. However, even with such a method, it cannot be said that a sufficient image defect suppression effect has been obtained.

  Therefore, the present invention can sufficiently suppress the occurrence of image defects even when the transistors included in the pixel portion and the peripheral circuit portion are simultaneously formed on the same substrate by applying the CMOS logic process, and the pixel can be miniaturized. It is an object of the present invention to provide a solid-state imaging device excellent in image characteristics and a method for manufacturing the same.

  The invention that solves the above-described problems is directed to a solid-state imaging device in which a pixel portion in which a plurality of pixels are two-dimensionally arranged and a peripheral circuit portion that is arranged around the pixel portion are formed on the same semiconductor substrate. It has been. In this solid-state imaging device, each pixel includes a first transistor and a second transistor. The first transistor is formed on a main surface of the semiconductor substrate adjacent to the transfer gate electrode and a transfer gate electrode formed on the main surface of the semiconductor substrate via a gate insulating film, and accumulates electric charges according to the amount of incident light. A first diffusion layer; and a second diffusion layer formed on the main surface of the semiconductor substrate adjacent to the transfer gate electrode on the side opposite to the first diffusion layer. The second transistor includes a first gate electrode formed on the main surface of the semiconductor substrate via a gate insulating film, and third and fourth electrodes formed on the main surface of the semiconductor substrate adjacent to the first gate electrode. And a diffusion layer. The peripheral circuit portion includes a second gate electrode formed on the main surface of the semiconductor substrate via a gate insulating film, and fifth and fifth gate electrodes formed on the main surface of the semiconductor substrate adjacent to the second gate electrode. A plurality of third transistors having six diffusion layers. The residual stress at least under the transfer gate electrode and under the first gate electrode is 37 MPa or less. By setting it as such a structure, the image defect in a pixel part can be suppressed. Here, the first diffusion layer specifically includes a photodiode.

  The first, second, and third transistors may be isolated from each other by an element isolation region having an STI structure, and the thickness of the gate insulating film that constitutes each transistor may be 10 μm or less. This structure is particularly applied to a solid-state imaging device having a fine structure of 0.25 μm or less. Even in such a solid-state imaging device, image characteristics are suppressed and image characteristics are improved. be able to.

  Specifically, the transfer gate electrode and the first gate electrode are formed of a laminated film of a silicon film and a refractory metal silicide film, and the film thickness ratio of the refractory metal silicide film to the silicon film is 0.7 or less. Thus, the residual stress under the gate electrode can be regulated to the above value. Examples of such a refractory metal silicide film include those formed of tungsten silicide.

  Alternatively, the residual stress under the gate electrode can be reduced by forming the transfer gate electrode and the first gate electrode with a laminated film of a silicon film and a refractory metal silicide film made of titanium silicide or cobalt silicide. The value can be regulated. Since the residual stress of titanium silicide or cobalt silicide is relatively small compared to the above-described tungsten silicide, the laminated film can obtain a desired residual stress without being limited to the above-described film thickness ratio, and further Thin film can be realized.

  In the present invention, the residual stress under the second gate electrode may be 37 MPa or less. With such a configuration, it is possible to suppress the occurrence of leakage current in the peripheral circuit portion, and thus it is possible to realize a solid-state imaging device with more excellent circuit characteristics. Further, the third transistor may be a CMOS transistor or may be composed of only an N-channel transistor.

  In addition, the present invention provides a solid-state imaging device in which a pixel unit in which a plurality of pixels are arranged two-dimensionally and a peripheral circuit unit arranged around the pixel unit are formed on the same semiconductor substrate. Also directed to the method. There are the following methods for manufacturing such a solid-state imaging device. First, a first diffusion layer for accumulating signal charges corresponding to the amount of incident light is formed on the main surface of the semiconductor substrate. Next, a gate insulating film is formed on the main surface of the semiconductor substrate. Next, a laminated film is formed by sequentially forming a silicon film and a refractory metal silicide film on the gate insulating film. Next, the transfer gate electrode and the first and second transistors are formed by selectively etching the laminated film. Next, a second diffusion layer is formed in the semiconductor substrate adjacent to the transfer gate electrode to form a first transistor. Next, third and fourth diffusion layers are formed in the semiconductor substrate adjacent to the first gate electrode to form a second transistor. Further, fifth and sixth diffusion layers are formed in the semiconductor substrate adjacent to the second gate electrode to form a third transistor. Here, when forming the laminated film, the silicon film and the refractory metal silicide film are formed so that the film thickness ratio of the refractory metal silicide film to the silicon film is 0.7 or less. When forming the laminated film, it is preferable to form a refractory metal silicide film made of tungsten silicide.

  With such a configuration, the residual stress under the transfer gate electrode and the first gate electrode included in the pixel portion can be 37 MPa or less, and the pixel portion and the peripheral circuit portion can be formed using a CMOS logic process. The included MOS transistor can be formed at the same time, and a solid-state imaging device having excellent image characteristics can be realized.

  The solid-state imaging device of the present invention having excellent image characteristics can also be realized by the following method. First, a first diffusion layer for accumulating signal charges corresponding to the amount of incident light is formed on the main surface of the semiconductor substrate. Next, a gate insulating film is formed on the main surface of the semiconductor substrate. Next, a silicon film is formed over the gate insulating film. Next, the transfer gate electrode and the first and second gate electrodes are formed by selectively etching the silicon film. Next, a second diffusion layer is formed in the semiconductor substrate adjacent to the transfer gate electrode to form a first transistor. Next, third and fourth diffusion layers are formed in the semiconductor substrate adjacent to the first gate electrode to form a second transistor. Next, fifth and sixth diffusion layers are formed in the semiconductor substrate adjacent to the second gate electrode to form a third transistor. Next, a titanium film or a cobalt film that covers at least the transfer gate electrode and the first gate electrode is formed. Then, the titanium film or the cobalt film is silicided.

  Even with such a configuration, the residual stress under the gate electrode included in the pixel portion can be set to 37 MPa or less, and the MOS transistors included in the pixel portion and the peripheral circuit portion can be simultaneously formed using the CMOS logic process. A solid-state imaging device having excellent image characteristics can be realized.

  Further, in each of the manufacturing methods described above, after the impurity implantation into the semiconductor substrate for forming the first diffusion layer, heat treatment is performed by furnace annealing under the conditions of 850 ° C. to 900 ° C. and within 60 minutes. Anyway. By performing such a furnace annealing process, it is possible to further suppress image defects in the pixel portion and realize a solid-state imaging device having excellent image characteristics.

  The solid-state imaging device of the present invention having excellent image characteristics can also be realized by the following method. First, a first diffusion layer for accumulating signal charges corresponding to the amount of incident light is formed on the main surface of the semiconductor substrate. Next, a gate insulating film is formed on the main surface of the semiconductor substrate. Next, a silicon film is formed over the gate insulating film. Next, the transfer gate electrode and the first and second gate electrodes are formed by selectively etching the silicon film. Next, a second diffusion layer is formed in the semiconductor substrate adjacent to the transfer gate electrode to form a first transistor. Next, third and fourth diffusion layers are formed in the semiconductor substrate adjacent to the first gate electrode to form a second transistor. Then, heat treatment is performed by furnace annealing under conditions of 850 ° C. or more and 900 ° C. or less and within 60 minutes to form fifth and sixth diffusion layers inside the semiconductor substrate adjacent to the second gate electrode. A third transistor is formed.

  In the solid-state imaging device having such a configuration, the transfer gate electrode and the first gate electrode are formed of a silicon film having a relatively small residual stress, and the third transistor is formed by furnace annealing that has a small influence on the photodiode. Since the diffusion layer to be formed is formed, a solid-state imaging device having excellent image characteristics can be realized even if the MOS transistors included in the pixel portion and the peripheral circuit portion are simultaneously formed using a CMOS logic process.

  In the above three manufacturing methods, an element isolation region having an STI structure may be formed on the main surface of the semiconductor substrate prior to the step of forming the gate insulating film. The film thickness may be 10 nm or less. Even a solid-state imaging device having such a fine structure can be made excellent in image characteristics by a manufacturing method using a CMOS logic process.

  As described above, according to the present invention, the MOS transistor included in the pixel portion and the peripheral circuit portion are applied by applying the CMOS logic process by regulating the residual stress under the transfer gate electrode and under the gate electrode included in the pixel portion. Even if the MOS transistors included in are simultaneously formed on the same semiconductor substrate, the occurrence of image defects can be suppressed, and a solid-state imaging device having excellent image characteristics can be realized. Further, the heat treatment performed when forming the diffusion layer of the MOS transistor included in the pixel portion or the peripheral circuit portion is furnace annealing performed under specific temperature and time conditions instead of RTA, thereby further increasing the pixel Residual stress under the transfer gate electrode and under the gate electrode included in the portion can be relaxed, and a solid-state imaging device with excellent image characteristics can be realized.

(First embodiment)
The solid-state imaging device according to the first embodiment of the present invention will be described below. Since the solid-state imaging device according to the present embodiment has the same configuration as the circuit diagram shown in FIG. 8 described in the conventional example, components having the same configuration are described with the same reference numerals. FIG. 1 is a cross-sectional view showing the in-process state of the solid-state imaging device according to this embodiment. In FIG. 1, the solid-state imaging device includes a pixel unit 7 and a peripheral circuit unit 19, and a MOS transistor included in the pixel unit 7 and a plurality of CMOS transistors included in the peripheral circuit unit 19 are on the same silicon substrate 20. It has an integrated circuit formed.

  The pixel unit 7 includes a plurality of pixels arranged two-dimensionally, more specifically in a matrix. In FIG. 1, the pixel portion 7 shows a part of a single pixel, and more specifically shows a part of the first and second transistors. The first transistor is the transfer transistor 2, and includes a transfer gate electrode 23a, an N-type signal charge storage region 25 as a first diffusion layer formed on the main surface of the silicon substrate 20 adjacent to the transfer gate electrode 23a, and the first transistor. 2 and an N-type drain region 24a as a diffusion layer. The N-type signal charge accumulation region 25 includes the photodiode 1 as a sensor unit, and accumulates charges generated by the photodiode 1 according to the amount of incident light. The N-type drain region 24 a carries the charge accumulated in the N-type signal charge accumulation region 25. The transfer gate electrode 23a serves as a switch for moving the accumulated charge to the N-type drain region 24a.

  The second transistor includes a gate electrode 23b as a first gate electrode, and a source diffusion layer (not shown) as a third diffusion layer formed on the main surface of the silicon substrate 20 adjacent to the gate electrode 23b. And a drain diffusion layer (not shown) as a fourth diffusion layer. Specifically, the second transistor refers to the reset transistor 3, the amplification transistor 4, the selection transistor 5, and the like. Here, the gate electrode 23b constituting the reset transistor 3 and the selection transistor 5 is formed on the STI 21. It is shown as an extended gate electrode wiring. This is for convenience, and the gate electrode 23b is formed on the gate insulating film 22 in the same manner as the transfer gate electrode 23a depending on the portion illustrated.

  The peripheral circuit portion 19 shows a part of a plurality of third transistors provided. Here, the third transistor is a CMOS transistor, and a gate electrode 23c as a second gate electrode and N as a fifth diffusion layer formed on the main surface of the silicon substrate 20 adjacent to the gate electrode 23c. And a P-type diffusion layer (Pwell) 27 as a sixth diffusion layer. LDD (Lightly Doped Drain) layers 24b and 24c are formed on the main surfaces of the N-type diffusion layer (Nwell) 26 and the P-type diffusion layer (Pwell) 27, respectively.

  The silicon substrate 20 that serves as a base for forming the first, second, and third transistors is a silicon substrate that is formed of a P-type semiconductor. On the main surface of the silicon substrate 20, an STI 21 for isolating each transistor is formed. The gate insulating film 22 is made of a silicon oxide film, and insulates the silicon substrate 20 from the first to third transistors. The STI 21 is mainly applied to a fine structure of 0.25 μm or less, and in the solid-state imaging device having such a fine structure, the thickness of the gate insulating film 22 is 10 nm or less.

  Here, the first and second transistors included in the pixel unit 7, which is a characteristic part of the present embodiment, will be described. The present inventor has found that there is a correlation between the residual stress under the transfer gate electrode 23a and the gate electrode 23b included in the pixel unit 7 and the number of image defects in the solid-state imaging device, and actually, under the transfer gate electrode 23a. The relationship between the residual stress under the gate electrode 23b and the number of image defects was examined.

FIG. 2 is a graph showing the relationship between the residual stress (MPa) under the transfer gate electrode 23a and the gate electrode 23b and the number of image defects (pieces) generated in the solid-state imaging device. The transfer gate electrode 23a and the gate electrode 23b have a silicide structure in which a WSi film and a polycrystalline silicon film are stacked, and the number of image defects is obtained by visually measuring the number of crystal defects. As shown in FIG. 2, when the residual stress under the transfer gate electrode 23a and under the gate electrode 23b increases, the image defect increases. In particular, when the residual stress under the transfer gate electrode 23a and the gate electrode 23b exceeds 37 MPa, the image defect It is clear that the increase in is significant. In addition to the transfer gate electrode 23a and the gate electrode 23b having a silicide structure, this tendency is caused by an impurity-doped polycrystalline silicon film (hereinafter referred to as a DPS film), a silicide film using cobalt silicide (CoSi ₂ ), or the like. It is confirmed that the same applies to the formed transfer gate electrode 23a and gate electrode 23b.

  Therefore, in the present embodiment, image defects are suppressed by setting the residual stress below at least the transfer gate electrode 23a and the gate electrode 23b included in the pixel portion 7 to 37 MPa or less. This configuration is particularly effective in a solid-state imaging device having a miniaturized structure. In the miniaturized solid-state imaging device, each transistor is isolated by the STI 21 and the thickness of the gate insulating film 22 is as thin as 10 μm or less. Therefore, there is a problem that the residual stress on the photodiode 1 is large and it is difficult to suppress image defects. However, in the solid-state imaging device having such a fine structure, by applying the configuration according to the present embodiment, it is possible to reduce the residual stress on the photodiode 1 and suppress the occurrence of image defects.

  Factors that affect the residual stress under the transfer gate electrode 23a and the gate electrode 23b are the heat treatment performed when the diffusion layers are formed in the first to third transistors, and the transfer gate electrode 23a and the gate electrode 23b. There are various factors such as materials. For example, in FIG. 2, when the residual stress is about 68 MPa and when the residual stress is about 45 MPa, the film compositions constituting the transfer gate electrode 23a and the gate electrode 23b are the same, but the transfer gate electrode 23a and The heat treatment performed after the formation of the gate electrode 23b is different. The heat treatment when the residual stress is about 68 MPa is RTA, and the heat treatment when the residual stress is about 45 MPa is furnace (electric furnace) annealing. Although the residual stress under the transfer gate electrode 23a and the gate electrode 23b can also be reduced by changing the heat treatment in this way, it cannot be said that the effect sufficient to sufficiently suppress the image defect is obtained. In FIG. 2, when the residual stress is 38 MPa or less, furnace annealing is applied and the thickness ratio of the silicide film is changed.

  Therefore, the residual stress under the transfer gate electrode 23a and under the gate electrode 23b is reduced to 37 MPa or less by combining the film materials constituting the transfer gate electrode 23a and the gate electrode 23b, heat treatment, and the like as necessary. The solid-state imaging device according to the embodiment can be realized. Details of the factors that affect the residual stress under the transfer gate electrode 23a and the gate electrode 23b will be specifically described in the following embodiments.

  In the solid-state imaging device configured as described above, various MOS transistors included in the pixel unit 7 and the peripheral circuit unit 19 can be simultaneously formed on the same semiconductor substrate by a manufacturing method using a CMOS logic process. it can. In such a manufacturing method, after the heat treatment performed at the time of forming the diffusion layer in the first to third transistors, specifically, ion implantation into the silicon substrate 20 for forming the photodiode 1, In an activation annealing process performed either after ion implantation into the silicon substrate 20 for forming source and drain regions or after ion implantation into a potential fixing contact such as a well, RTA having a high temperature of 850 ° C. or higher Is done. In particular, RTA performed after the formation of the transfer gate electrode 23a and the gate electrodes 23b and 23c is likely to generate residual stress in the STI 21 and the gate insulating film 22 having a thin film structure. When the photodiode 1 is affected by this residual stress. Image defects are likely to occur.

  Therefore, in the present embodiment, in order to regulate the residual stress below the transfer gate electrode 23a and the gate electrode 23b to 37 MPa or less, heat treatment performed at the time of forming the diffusion layer in the first to third transistors, in particular, the transfer gate It is preferable to apply furnace (electric furnace) annealing instead of RTA for the heat treatment performed after forming the electrode 23a and the gate electrodes 23b and 23c. Furnace annealing has a moderate temperature rise compared to RTA. Therefore, as described above, the load on the STI 21 and the gate insulating film 22 is alleviated, the residual stress applied to the photodiode 1 is reduced, and further image defects are reduced. Suppression can be achieved.

  In the present embodiment, the transfer gate electrode 23a, the gate electrode 23b, and the gate electrode 23c included in the pixel unit 7 and the peripheral circuit unit 19 are simultaneously formed using the above-described CMOS logic process, so that the peripheral circuit unit is formed. The residual stress under the gate electrode 23c included in 19 can also be set to 37 MPa or less. As a result, not only the above-described image defect suppression effect but also the effect of suppressing the occurrence of leakage current in the peripheral circuit unit 19 can be obtained, and a solid-state imaging device having excellent peripheral circuit characteristics can be realized.

(Second Embodiment)
In the present embodiment, a solid-state imaging device in which the transfer gate electrode 23a and the gate electrode 23b included in the pixel unit 7 are formed of a laminated film of a silicon film and a refractory metal silicide film (hereinafter referred to as a polycide film). A method for reducing the residual stress of the transfer gate electrode 23a and the gate electrode 23b will be described. Here, a DPS film formed by a CVD method is taken as an example of the silicon film, and a WSi film having a relatively large residual stress is taken as an example of the refractory metal silicide film.

  FIG. 3 is a graph showing the relationship between the film thickness ratio of the WSi film to the DPS film constituting the polycide film (WSi film / DPS film) and the residual stress (MPa) under the transfer gate electrode 23a and the gate electrode 23b. is there. As described above, the residual stress under the transfer gate electrode 23a and under the gate electrode 23b can be greatly reduced by furnace annealing, and therefore, here, the transfer gate electrode 23a and the gate electrode 23b Data for those subjected to furnace annealing under conditions within 60 minutes are shown. As apparent from FIG. 3, the residual stress under the transfer gate electrode 23a and under the gate electrode 23b increases as the thickness of the WSi film increases. In order to set the residual stress under the transfer gate electrode 23a and the gate electrode 23b to 37 MPa or less, the film thickness ratio of the WSi film to the DPS film (WSi / DPS) may be 0.7 or less. By forming the transfer gate electrode 23a and the gate electrode 23b with the polycide film having such a configuration, as described in the first embodiment, image defects generated in the solid-state imaging device can be suppressed. In addition, when the above-described furnace annealing is not performed on the transfer gate electrode 23a and the gate electrode 23b, the film thickness ratio (WSi / DPS) of the WSi film to the DPS film is further reduced by less than 0.7. It is possible to obtain a desired residual stress.

  In addition, when the gate electrode 23c of the third transistor included in the peripheral circuit unit 19 is also formed of a polycide film in which the film thickness ratio of the WSi film to the DPS film is 0.7 or less as described above, the peripheral circuit unit It is possible to suppress the occurrence of a leak current at 19 and improve the performance of the peripheral circuit unit 19.

  Hereinafter, a method for manufacturing the solid-state imaging device according to the present embodiment will be described with reference to FIGS. FIG. 4 is a cross-sectional view of the substrate and its upper surface at each stage in the process of manufacturing the solid-state imaging device according to the present embodiment. FIG. 4A shows a state in which the DPS film 17 for forming the transfer gate electrode 23a and the gate electrodes 23b and 23c is formed on the surface of the substrate. In order to obtain such a substrate in progress, first, the STI 21 is formed inside the P-type silicon substrate 20. Next, the STI 21 is filled with a silicon oxide film, and the substrate surface is planarized by CMP. Next, the active region where the N channel MOS transistor is to be formed is covered with a resist using a lithography technique, and N-type impurities such as phosphorus are implanted into the active region where the P channel MOS transistor is to be formed by ion implantation or the like. . As a result, an N-type signal charge accumulation region 25 including a photodiode is formed on the main surface of the silicon substrate 20. Similarly, third and fourth diffusion layers not shown are formed.

  Next, an N-type diffusion layer 26 is formed by introducing N-type impurities into the P-channel MOS transistor formation region in the peripheral circuit portion 19 by ion implantation, and then the N-channel MOS transistor formation in the peripheral circuit portion 19 is performed. A P-type diffusion layer 27 is formed by introducing P-type impurities into the region by ion implantation. A silicon oxide film as the gate insulating film 22 is formed to a thickness of about 10 nm by a thermal oxidation method or a CVD method so as to cover the entire surface of the silicon substrate 20 configured as described above. Next, a polycrystalline silicon film is formed on the gate insulating film 22 by a CVD (Chemical Vapor Deposition) method or the like. Then, the DPS film 17 is formed by doping the polycrystalline silicon film with impurities.

  FIG. 4B shows a state in which the WSi film 18 is formed on the DPS film 17. In order to obtain a substrate in such a state, first, a W film (not shown) is formed on the DPS film 17 by a CVD method or the like. Then, by performing heat treatment on the W film, silicide is formed at the portion where the DPS film 17 and the W film are in contact with each other, and the WSi film 18 is formed. The WSi film 18 is a substance having a relatively high resistance among refractory metal silicides, and in order to reduce the resistance of the transfer gate electrode 23a and the gate electrodes 23b and 23c to a practical level, the WSi film 18 may be 90 nm or less. preferable. In the present embodiment, the WSi film 18 is formed with such a film thickness, and the film thickness ratio with respect to the DPS film 17 is 0.7 or less. For example, if the thickness of the DPS film 17 is 75 nm, the thickness of the WSi film 18 is 53 nm or less. As a result, the residual stress under the transfer gate electrode 23a and the gate electrode 23b made of the polycide film can be reduced to 37 MPa or less, and the residual stress in the N-type signal charge storage region 25, that is, the residual stress in the photodiode 1 can be reduced. It is possible to relax and suppress image defects such as crystal defects.

  FIG. 4C shows a state in which the transfer gate electrode 23 a and the gate electrodes 23 b and 23 c are formed on the main surface of the silicon substrate 20. The polycide film in which the DPS film 17 and the WSi film 18 are laminated at the film thickness ratio as described above is patterned into a desired shape using photolithography and RIE (Reactive Ion Etching) technology. As a result, the transfer gate electrode 23 a and the gate electrode 23 b included in the pixel unit 7 and the gate electrode 23 c included in the peripheral circuit unit 19 are simultaneously formed on the main surface of the silicon substrate 20. Residual stresses under the transfer gate electrode 23a, the gate electrode 23b, and the bottom 23c thus obtained are all 37 MPa or less, and a solid-state imaging device in which image defects are suppressed can be realized even when a CMOS logic process is applied.

  Next, an N-type drain region 24a is formed adjacent to the transfer gate electrode 23a using photolithography and ion implantation, and an N-type LDD region is formed in the N-type diffusion layer 26 of the N-channel MOS transistor in the peripheral circuit portion 19. A P-type LDD layer 24c is formed on the P-type diffusion layer 27 of the P-channel MOS transistor.

  Even with the above configuration alone, it is possible to suppress image defects and improve the image characteristics. However, in order to further improve the image characteristics, it is necessary to perform the process when forming the diffusion layers in the first to third transistors. Heat treatment, more preferably heat treatment performed after formation of the transfer gate electrode 23a, gate electrodes 23b and 23c, and more preferably activation annealing treatment for the N-type diffusion layer 26 and the P-type diffusion layer 27 in the peripheral circuit portion 19 Is preferably furnace annealing under predetermined conditions instead of RTA. As described above, since the heat treatment by RTA is a heat treatment accompanied by a rapid temperature rise, high heat is also applied to the STI 21, the transfer gate electrode 23 a, and the gate electrode 23 b included in the pixel portion 7, resulting in a large residual stress. This is to cause it to occur.

  In this embodiment, the conditions for performing furnace annealing are preferably 850 ° C. or higher and 900 ° C. or lower and 60 minutes or less. Under such conditions, the residual stress under the transfer gate electrode 23a and the gate electrode 23b included in the pixel portion 7 can be further reduced, and a solid-state imaging device in which image defects are further suppressed can be realized.

  The details will be described below with specific examples. FIG. 5 is a diagram showing the substrate and the state of the upper surface for explaining each processing step performed after the processing step shown in FIG. FIG. 5A shows a state in which the main surface of the substrate that has undergone the processing steps shown in FIG. The silicon nitride film 28 is formed by an atmospheric pressure CVD method or the like, and its film thickness is 30 nm.

  FIG. 5B shows a state in which a silicon oxide film 29 is formed on the silicon nitride film 28 and a resist pattern 30 for patterning these films into a desired shape is formed. The silicon oxide film 29 is formed to a thickness of 85 nm by a low pressure CVD method or the like so as to cover the entire surface of the silicon nitride film 28. Next, a resist is applied on the silicon oxide film 29 to form a resist film (not shown). By selectively removing the obtained resist film by photolithography, a resist pattern 30 patterned into a desired shape is formed above the N-type signal charge storage region 25.

  FIG. 5C shows a state after the silicon nitride film 28 and the silicon oxide film 29 are etched. Specifically, the silicon nitride film 28 and the silicon oxide film 29 are dry-etched using the resist pattern 30 as a mask and using the RIE technique. By this etching process, side walls 32 are formed on the side walls of the transfer gate electrode 23a and the gate electrodes 23b and 23c, and a silicide block layer 31 patterned in a desired shape is formed on the N-type signal charge storage region 25. Is done. The resist pattern 30 after the etching process is removed.

  In this step, it is necessary to prevent the WSi constituting the transfer gate electrode 23a and the gate electrodes 23b and 23c from being exposed by the dry etching process. This is because if WSi is exposed, W not only becomes a contamination source for the subsequent process, but also abnormal oxidation of the WSi surface occurs.

FIG. 5D shows a state in which the P ⁺ -type surface shield region 33 is formed on the main surface of the N-type signal charge storage region 25 and the source / drain regions 34 a and 34 b are formed in the peripheral circuit portion 19. First, the surface shield region 33 is formed on the surface of the N-type signal charge storage region 25 in the pixel portion 7 by using a photolithography method and an ion implantation method. By forming the surface shield region 33, the P ⁺ NP type embedded photodiode 1 is formed in the pixel portion 7. Here, the surface shield region 33 shields the Si / SiO ₂ interface on the surface of the photodiode 1 from the N-type signal charge storage region 25, and the depletion layer formed by the N-type signal charge storage region 25 is the Si / SiO ₂ interface. It plays the role of preventing the spread to Therefore, the surface shield region 33 can suppress the occurrence of leakage current due to the Si / SiO ₂ interface state.

On the other hand, in the peripheral circuit portion 19, source / drain regions 34a and 34b are formed in the element region. Here, N-type high concentration ion implantation is performed to form the source / drain region 34a in the N channel MOS region, and P type high concentration ion implantation is performed to form the source / drain region 34b in the P channel MOS region. Done. This high-concentration ion implantation is not shown, but in order to take the potentials of the N-type diffusion layer 26 and the P-type diffusion layer 27, an N ⁺ contact region and a P ⁺ contact to be formed on the respective wells. Implantation into the region is also included.

FIG. 5E shows a state in which a metal silicide film is formed in the source / drain regions 34 a and 34 b included in the peripheral circuit portion 19. In order to obtain a substrate in such a state, first, ions are implanted into the source / drain regions 34a and 34b, and an activation annealing process is performed. If the activation annealing process is a normal fine CMOS logic process, RTA is used to form a shallow PN junction. However, since RTA is a process in which the temperature rises rapidly in a short time as described above, it is easy to induce crystal defects in the silicon substrate 20 due to the residual stress accompanying this temperature change, and due to the temperature change described above. The residual stress generated in the STI 21, the transfer gate electrode 23a, the gate electrodes 23b and 23c is likely to affect the photodiode 1, and the P ⁺ type surface shield region 33 is a very high concentration ion implantation layer. In addition to the occurrence of a large amount of defects due to the temperature change described above, there is a problem that, when an insufficient activation annealing treatment is performed, the defects grow greatly to generate secondary defects.

  Therefore, in the present embodiment, furnace annealing is performed instead of RTA as the above-described activation annealing treatment. Furnace annealing does not cause a rapid increase in temperature. For example, if annealing is performed at 850 ° C. for 45 minutes, sufficient heat treatment can be performed without causing the above-described various problems. Is possible. In the present embodiment, the furnace annealing is preferably performed under conditions of 850 ° C. or higher and 900 ° C. or lower and within 60 minutes.

The activation annealing for the P ⁺ type surface shield region 33 needs to be performed immediately after the formation of the surface shield region 33 when using RTA. Therefore, RTA for the surface shield region 33 and RTA after ion implantation for the source / drain regions 34a and 34b are performed separately. However, if furnace annealing is applied as in the present embodiment, defects in the surface shield region 33 are unlikely to occur, and therefore activation annealing on the surface shield region 33 and the source / drain regions 34a and 34b can be performed collectively. It becomes possible. However, furnace annealing can be performed immediately after the surface shield region 33 is formed.

Next, pre-processing of metal silicidation processing is performed on a transfer gate electrode 23a and gate electrodes 23b and 23c described later. Specifically, preamorphized ions are implanted into a predetermined region of the main surface of the silicon substrate 20 excluding at least the N-type signal charge storage region 25 and the N-type drain region. The pre-amorphization ion implantation is performed using As ions under the conditions of an acceleration voltage of 20 KeV and a dose of 3.0E14 / cm ² , for example.

  Next, a metal film (not shown) for forming a silicide is formed on the entire surface of the silicon substrate 20 by sputtering or the like. As the metal film, for example, a W film having a thickness of 40 nm is formed. Next, RTP (Rapid Thermal Processing) is performed in a nitrogen atmosphere under conditions of, for example, 675 ° C. and 30 seconds. As a result, silicon contained in the silicon substrate 20 reacts with W in the silicide metal film in a region where the element region of the silicon substrate 20 and the silicide forming metal film are in direct contact, and the metal is silicided. A WSi film (not shown) is formed.

Next, an unreacted remaining metal film is selectively formed on the silicide block layer 31 made of the silicon nitride film 28 and the silicon oxide film by using an H ₂ SO ₄ + H ₂ O ₂ solution, an HCl + H ₂ O ₂ solution, or the like. Remove and remove. Further, for example, RTP heat treatment is performed under conditions of 850 ° C. and 10 seconds. By such processing, the WSi film 35 is formed on the main surface of the silicon substrate 20 that is not covered with the silicide block layer 31 or the like.

  FIG. 5F shows a state in which aluminum (Al) wirings 37 are formed on the surface of the substrate that has been subjected to the planarization process. In order to obtain a substrate in such a state, first, a silicon oxide film as an interlayer insulating film 36 is deposited by an oxidation / CVD method so as to cover the entire surface of the silicon substrate 20 on which the metal silicide film is formed. Next, a planarization process such as a CMP (Chemical Mechanical Polish) process is performed on the surface of the interlayer insulating film 36. Next, an aluminum (Al) film (not shown) is deposited on the surface of the interlayer insulating film 36 subjected to the planarization process by sputtering or the like, and this Al film is patterned into a desired shape. As a result, an Al wiring 37 is formed on the surface of the interlayer insulating film 36. The Al wiring 37 serves as a signal line or connection wiring in the pixel unit 7 and a connection wiring in the peripheral circuit unit 19. In the solid-state imaging device, the multilayer wiring is further provided on the upper layer of the Al wiring 37, but the process for forming the subsequent multilayer wiring is the same as the conventional process, and the description thereof is omitted.

  In the solid-state imaging device configured as described above, the transfer gate electrode 23a is formed by setting the film thickness ratio (WSi film / DPS film) of the silicide films constituting the transfer gate electrode 23a and the gate electrode 23b to 0.7 or less. The residual stress under the gate electrode 23b and under the gate electrode 23b can be set to 37 MPa or less. Further, activation annealing is performed when the source / drain implantation of the MOS transistor and the surface shield region 33 on the N-type signal charge storage region 25 are formed. By using furnace annealing, residual stress under the transfer gate electrode 23a and under the gate electrode 23b can be further reduced, and image defects can be further prevented from occurring. As a result, even in a fine MOS solid-state imaging device having a size of 0.25 μm or less manufactured using CMOS logic technology, image defects such as white scratches and dark current variations (dark roughness) are suppressed, and imaging characteristics are poor. It can be solved.

  In the above description, the DPS film has been described as an example of the silicon film. However, the present invention is not limited to this, and a polycrystalline polysilicon film not doped with impurities is also applicable. Further, the WSi film has been described as an example of the refractory metal silicide film, but the present invention is not limited to this, and a molybdenum silicide film or the like can also be applied.

(Third embodiment)
In the present embodiment, titanium silicide (TiSi ₂ ) or CoSi ₂ having a lower residual stress than the WSi film is used as the refractory metal silicide constituting the transfer gate electrode 23a, the gate electrodes 23b and 23c described in the second embodiment. The solid-state imaging device used will be described. Since the DPS film using TiSi ₂ or CoSi ₂ has a smaller residual stress than the DPS film using WSi, the film thickness of each film constituting the silicide film should be defined as in the second embodiment. The residual stress under the gate electrode can be relaxed.

Below, the manufacturing method of the solid-state imaging device concerning this embodiment is explained. The manufacturing method of the solid-state imaging device according to the present embodiment is almost the same as that shown in FIGS. 4 and 5 described in the first embodiment, and will be described with reference to both drawings. First, the DPS film 17 is formed on the surface of the silicon substrate 20 in the same manner as the process shown in FIG. Next, in the process described with reference to FIG. 4B, a TiSi ₂ film or a CoSi ₂ film is formed instead of the WSi film 18. The polycide structure using the TiSi ₂ film or the CoSi ₂ film has a smaller residual stress than the polycide structure using the WSi film 18 described in the second embodiment. And the resistance of the transfer gate electrode 23a and the gate electrode 23b can be reduced. Generally, the residual stress under the transfer gate electrode 23a and the gate electrode 23b having a polycide structure using a TiSi ₂ film or a CoSi ₂ film is about 30 to 40 MPa. Therefore, if the polycide film laminated as described above is patterned in the same manner as the process described with reference to FIG. 4C, at least the residual stress under the transfer gate electrode 23a and the gate electrode 23b is related to the second embodiment. The residual stress under the transfer gate electrode 23a and the gate electrode 23b can be relaxed.

After the transfer gate electrode 23a and the gate electrodes 23b and 23c are formed, the solid-state imaging device according to the present embodiment can be realized by sequentially performing the steps shown in FIGS. In the step shown in FIG. 5E, it is also possible to form a CoSi ₂ film by forming a Co film instead of forming a Ti film.

As described above, in the solid-state imaging device according to the present embodiment, the transfer gate electrode 23a and the gate electrode 23b having a polycide structure using a TiSi ₂ film or a CoSi ₂ film are applied, so that transfer is performed more than in the second embodiment. The residual stress under the gate electrode 23a and the gate electrode 23b can be relaxed. When the residual stress below the transfer gate electrode 23a and the gate electrode 23b exceeds 37 MPa, the film thickness ratio of the polycide structure is adjusted, or in the ion activation annealing performed in the process shown in FIG. Instead, the residual stress under the transfer gate electrode 23a and the gate electrode 23b can be reduced to 37 MPa or less by using a method such as performing furnace annealing alone or in combination. Thereby, even if it is a MOS type solid-state imaging device manufactured using a fine CMOS logic technology of 0.25 μm or less, a solid-state imaging device with excellent imaging characteristics in which image defects such as white scratches are suppressed can be realized.

(Fourth embodiment)
In the second and third embodiments, an example in which the transfer gate electrode 23a and the gate electrode 23b have a polycide structure has been described. However, even if the resistance of the transfer gate electrode 23a and the gate electrode 23b is relatively high, the solid-state imaging device If the above characteristics are allowed, a solid-state imaging device having a transfer gate electrode 23a and a gate electrode 23b made of only a silicon film may be used. For example, in the case of a solid-state imaging device having a film thickness of 0.2 μm and a residual stress under the transfer gate electrode 23a and under the gate electrode 23b of 50 MPa, the furnace annealing described above is applied in the silicide formation step. The residual stress under the transfer gate electrode 23a and under the gate electrode 23b can be reduced to about 27 MPa.

  In the case where the transfer gate electrode 23a and the gate electrode 23b are formed using only a silicon film, the step of forming the silicide block layer 31 is not necessary. The configuration according to the present embodiment can also be applied to a solid-state imaging device having the transfer gate electrode 23a and the gate electrode 23b that are configured not only by the silicon film but also only by the DPS film.

(Fifth embodiment)
In each of the above embodiments, the solid-state imaging device in which the peripheral circuit unit 19 is configured by a CMOS transistor has been described. In the present embodiment, a solid-state imaging device in which the peripheral circuit unit 19 is configured by only an N-channel MOS transistor will be described. . 6 and 7 show a substrate at each stage in the process of manufacturing a solid-state imaging device in which the peripheral circuit portion 19 is composed only of N-channel MOS transistors and the impurity diffusion layer is composed only of the P-type diffusion layer 27, and It is sectional drawing of an upper surface.

  FIG. 6A shows a state in which the DPS film 17 for forming the transfer gate electrode 23a and the gate electrodes 23b and 23c is formed on the surface of the substrate. In order to obtain such an in-process substrate, the STI 21N type signal charge storage region 25 and the third and third unillustrated regions in the silicon substrate 20 are formed in the same manner as in the step shown in FIG. A fourth diffusion layer is formed. Next, a P-type diffusion layer 27 is formed by introducing P-type impurities into the N channel MOS transistor formation region in the peripheral circuit portion 19 by ion implantation. Then, the gate insulating film 22 and the DPS film 17 are formed as in the step shown in FIG.

  FIG. 6B shows a state in which the WSi film 18 is formed on the DPS film 17. The WSi film 18 is formed in the same manner as the step shown in FIG. FIG. 6C shows a state in which the transfer gate electrode 23a and the gate electrodes 23b and 23c are formed on the main surface of the substrate. The transfer gate electrode 23a and the gate electrodes 23b and 23c are formed in the same manner as the step shown in FIG. Then, using photolithography and ion implantation, an N-type drain region 24a is formed in the adjacent portion of the transfer gate electrode 23a, and a P-type LDD layer 24c is formed in the P-type diffusion layer 27 in the peripheral circuit portion 19, respectively.

  FIG. 7A shows a state in which the main surface of the substrate that has undergone the processing step shown in FIG. 6 is covered with the silicon nitride film 28 in the same manner as the step shown in FIG. 7B, in the same manner as the process shown in FIG. 5B, a silicon oxide film 29 is formed on the silicon nitride film 28, and a resist pattern 30 for patterning these films into a desired shape. The state which formed is shown. FIG. 7C shows a state after etching the silicon nitride film 28 and the silicon oxide film 29 in the same manner as the process shown in FIG.

FIG. 7D shows a state in which a P ⁺ -type surface shield region 33 is formed on the main surface of the N-type signal charge storage region 25 and source / drain regions 34 a and 34 b are formed in the peripheral circuit portion 19. Here, the processing in the pixel portion 7 is the same as the process shown in FIG. 5D, but in the peripheral circuit portion 19, N-type high-concentration ion implantation is performed toward the P-type diffusion layer 27, and the gate electrode Source / drain regions 34a and 34b in 23c are formed. Although the high concentration ion implantation here is not shown, in order to take the potential of the P-type diffusion layer 27, the implantation into the P ⁺ contact region to be formed on the main surface of the P-type diffusion layer 27 is also included.

  FIG. 7E shows a state in which a metal silicide film is formed in the source / drain regions 34 a and 34 b included in the peripheral circuit portion 19. In order to obtain a substrate in such a state, first, ions are implanted into the source / drain regions 34a and 34b, and an activation annealing process is performed. Also in this activation annealing treatment, it is preferable to perform furnace annealing as in the second embodiment. However, in this embodiment, the peripheral circuit portion 19 is composed only of N-channel MOS transistors. As in the second embodiment, the process margin can be widened as compared with the solid-state imaging device in which the peripheral circuit unit 19 is configured by a CMOS transistor. This is because the peripheral circuit portion 19 is composed only of an N-channel MOS transistor, and boron is oozed from the gate electrode of the P-channel MOS transistor to the gate insulating film 22 by furnace annealing after the transistor is formed. This is because it is not necessary to determine the annealing conditions in consideration of occurrence of threshold voltage fluctuations. Thereby, for example, the heat treatment step after the gate formation step of the MOS transistor can include an annealing step in a high temperature region of 15 minutes or more at a temperature not exceeding 900 ° C., and the activation of the source / drain regions 34a and 34b. It becomes possible to make it more reliable.

  In the N-channel MOS transistor according to the present embodiment, when furnace annealing similar to that of the second embodiment is performed, transistor characteristics such as threshold voltage, saturation current, and subthreshold characteristics slightly vary. However, this can be dealt with by performing threshold adjustment ion implantation or source / drain implantation.

Next, in the same manner as in the step shown in FIG. 5 (e), pre-processing of metal silicidation processing, formation of metal film, silicidation processing of metal film, formation of silicide block layer 31, and formation of TiSi ₂ film 35 Continue to do.

  FIG. 7F shows a state in which aluminum (Al) wirings 37 are formed on the surface of the substrate that has been subjected to the planarization process in the same manner as FIG. Thereby, the solid-state imaging device according to the present embodiment is obtained.

  As described above, according to the embodiment of the present invention, it is possible to suppress the relaxation of various residual stresses applied to the photodiode 1 and the generation of crystal defects without considering the deterioration of the threshold voltage of the transistor. In addition, even in a fine MOS solid-state imaging device of 0.25 μm or less manufactured using CMOS logic technology, it is possible to solve imaging characteristic defects such as white scratches and dark current variations (dark darkness).

  In the above description, an example in which furnace annealing is applied to activation annealing of the source / drain regions 34a and 34b in the peripheral circuit portion 19 has been described. However, the present invention is not limited to this, and the furnace annealing is not limited thereto. The annealing can be performed at least once after ion implantation for forming the photodiode, after ion implantation that constitutes the source / drain of the MOS transistor, and after ion implantation to the potential fixing contact such as a well. It is also possible to perform more than one.

  As described above in each embodiment, the image characteristics can be further improved by using the structure according to the first embodiment and furnace annealing in the annealing process after forming the gate electrode.

  In each of the above embodiments, the STI is described as an example of the element isolation structure of each transistor. However, the present invention is not limited to this, and an element isolation structure by the LOCOS method is also applicable.

  The solid-state imaging device according to the present invention relieves the residual stress under the gate electrode of the MOS transistor included in the pixel portion even if the MOS transistor included in the pixel portion and the peripheral circuit portion is simultaneously formed using the CMOS logic process. Therefore, it can be suitably used for a MOS solid-state imaging device having a fine structure of 0.25 μm or less to which an element isolation structure by the STI method is applied. Specifically, it can be suitably used for a solid-state imaging device used for a mobile phone with a camera, a video camera, a digital still camera, etc., a line sensor used for a printer, a CCD, and the like.

Sectional drawing which shows the structure of the solid-state imaging device which concerns on the 1st Embodiment of this invention. Graph showing the dependence of image defects on residual stress under the gate electrode The graph which shows the relationship between the residual stress under the gate electrode which concerns on the 2nd Embodiment of this invention, and the thickness ratio of the WSi film with respect to a DPS film Sectional drawing which shows the manufacturing process of the solid-state imaging device concerning the embodiment Sectional drawing which shows the manufacturing process of the solid-state imaging device concerning the embodiment Sectional drawing which shows the manufacturing process of the solid-state imaging device concerning the 5th Embodiment of this invention. Sectional drawing which shows the manufacturing process of the solid-state imaging device concerning the embodiment Plan view showing circuit configuration of MOS type solid-state imaging device

Explanation of symbols

20 Silicon substrate 21 STI
22 Gate insulating film 23a Transfer gate electrode 23b, 23c Gate electrode 24a N-type drain region 24b, 24c LDD layer 25 N-type signal charge storage region 26 N-type diffusion layer 27 P-type diffusion layer 28 Silicon nitride film 29 Silicon oxide film 30 Resist Pattern 31 Silicide block layer 32 Side wall 33 Surface shield region 34a, 34b Source / drain region 35 WSi film 36 Interlayer insulating film 37 Al wiring

Claims (15)

A solid-state imaging device in which a pixel unit in which a plurality of pixels are two-dimensionally arranged and a peripheral circuit unit arranged around the pixel unit are formed on the same semiconductor substrate,
Each said pixel is
A transfer gate electrode formed on the main surface of the semiconductor substrate via a gate insulating film;
A first diffusion layer formed on the main surface of the semiconductor substrate adjacent to the transfer gate electrode and storing charges according to the amount of incident light;
A first transistor having a second diffusion layer formed on a main surface of the semiconductor substrate adjacent to the transfer gate electrode on the side opposite to the first diffusion layer; and
A first gate electrode formed on the main surface of the semiconductor substrate via the gate insulating film;
A second transistor having third and fourth diffusion layers formed on a main surface of the semiconductor substrate adjacent to the first gate electrode;
The peripheral circuit section is
A second gate electrode formed on the main surface of the semiconductor substrate via the gate insulating film;
A plurality of third transistors having fifth and sixth diffusion layers formed on the main surface of the semiconductor substrate adjacent to the second gate electrode;
A solid-state imaging device, wherein a residual stress at least under the transfer gate electrode and under the first gate electrode is 37 MPa or less.   The solid-state imaging device according to claim 1, wherein the first diffusion layer includes a photodiode. The first, second, and third transistors are each isolated by an element isolation region having an STI structure,
The solid-state imaging device according to claim 1, wherein a film thickness of the gate insulating film constituting each of the transistors is 10 μm or less.   The transfer gate electrode and the first gate electrode are made of a laminated film of a silicon film and a refractory metal silicide film, and a film thickness ratio of the refractory metal silicide film to the silicon film is 0.7 or less. The solid-state imaging device according to claim 1, wherein:   The solid-state imaging device according to claim 4, wherein the refractory metal silicide film is formed of tungsten silicide.   2. The solid according to claim 1, wherein the transfer gate electrode and the first gate electrode are made of a laminated film of a silicon film and a refractory metal silicide film formed of titanium silicide or cobalt silicide. Imaging device.   The solid-state imaging device according to claim 1, wherein a residual stress under the second gate electrode is 37 MPa or less.   The solid-state imaging device according to claim 1, wherein the third transistor is a CMOS transistor.   The solid-state imaging device according to claim 1, wherein the third transistor includes only an N-channel transistor. A method for manufacturing a solid-state imaging device in which a pixel unit in which a plurality of pixels are two-dimensionally arranged and a peripheral circuit unit arranged around the pixel unit are formed on the same semiconductor substrate,
Forming a first diffusion layer on the main surface of the semiconductor substrate for accumulating signal charges according to the amount of incident light;
Forming a gate insulating film on the main surface of the semiconductor substrate;
Forming a laminated film by sequentially forming a silicon film and a refractory metal silicide film on the gate insulating film;
Forming a transfer gate electrode, first and second gate electrodes by selectively etching the laminated film;
Forming a first transistor by forming a second diffusion layer in the semiconductor substrate adjacent to the transfer gate electrode;
Forming a second transistor by forming third and fourth diffusion layers in the semiconductor substrate adjacent to the first gate electrode;
Forming a third transistor by forming fifth and sixth diffusion layers inside the semiconductor substrate adjacent to the second gate electrode,
The step of forming the stacked film is characterized in that the silicon film and the refractory metal silicide film are formed so that a film thickness ratio of the refractory metal silicide film to the silicon film is 0.7 or less. A method for manufacturing a solid-state imaging device.   11. The method for manufacturing a solid-state imaging device according to claim 10, wherein the step of forming the laminated film forms a refractory metal silicide film made of tungsten silicide. A method for manufacturing a solid-state imaging device in which a pixel unit in which a plurality of pixels are two-dimensionally arranged and a peripheral circuit unit arranged around the pixel unit are formed on the same semiconductor substrate,
Forming a first diffusion layer on the main surface of the semiconductor substrate for accumulating signal charges according to the amount of incident light;
Forming a gate insulating film on the main surface of the semiconductor substrate;
Forming a silicon film on the gate insulating film;
Forming a transfer gate electrode, first and second gate electrodes by selectively etching the silicon film;
Forming a first transistor by forming a second diffusion layer in the semiconductor substrate adjacent to the transfer gate electrode;
Forming a second transistor by forming third and fourth diffusion layers in the semiconductor substrate adjacent to the first gate electrode;
Forming fifth and sixth diffusion layers in the semiconductor substrate adjacent to the second gate electrode to form a third transistor;
Forming a titanium film or a cobalt film covering at least the transfer gate electrode and the first gate electrode;
And a step of silicidating the titanium film or the cobalt film.   The method further includes a step of performing heat treatment by furnace annealing under conditions of 850 ° C. to 900 ° C. and within 60 minutes after impurity implantation into the semiconductor substrate for forming the first diffusion layer. A method for manufacturing a solid-state imaging device according to claim 10 or 12. A method for manufacturing a solid-state imaging device in which a pixel unit in which a plurality of pixels are two-dimensionally arranged and a peripheral circuit unit arranged around the pixel unit are formed on the same semiconductor substrate,
Forming a first diffusion layer on the main surface of the semiconductor substrate for accumulating signal charges according to the amount of incident light;
Forming a gate insulating film on the main surface of the semiconductor substrate;
Forming a silicon film on the gate insulating film;
Forming a transfer gate electrode, first and second gate electrodes by selectively etching the silicon film;
Forming a first transistor by forming a second diffusion layer in the semiconductor substrate adjacent to the transfer gate electrode;
Forming a second transistor by forming third and fourth diffusion layers in the semiconductor substrate adjacent to the first gate electrode;
A heat treatment is performed by furnace annealing under conditions of 850 ° C. to 900 ° C. and within 60 minutes to form fifth and sixth diffusion layers inside the semiconductor substrate adjacent to the second gate electrode. And a step of forming a third transistor. A method for manufacturing a solid-state imaging device. Prior to the step of forming the gate insulating film, the method further includes a step of forming an element isolation region having an STI structure on the main surface of the semiconductor substrate,
15. The manufacturing of the solid-state imaging device according to claim 10, wherein the gate insulating film is formed with a thickness of 10 nm or less in the step of forming the gate insulating film. Method.

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