JP2006128148A - Semiconductor device manufacturing method and semiconductor manufacturing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology for suppressing generation of abnormal products in a process for removing a resist film into which n-type impurities are introduced. <P>SOLUTION: A resist film 16 is formed on a polysilicon film 15 and subjected to exposure/development thus patterning the resist film 16. Patterning is performed such that an opening 17 is formed in the gate electrode forming region of the polysilicon film 15. Subsequently, phosphor is injected into the polysilicon film 15 exposed from the opening 17. Phosphor is also injected into the resist film 16 and a cured layer 16a is formed. Thereafter, the cured layer 16a and the resist film 16 are removed by introducing oxygen gas and forming gas. Volume ratio of forming gas to the mixture gas of oxygen gas and forming gas is set in the range of 5-30%. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique effective when applied to a step of removing a resist film formed on a semiconductor wafer (hereinafter simply referred to as a wafer).

Japanese Patent Application Laid-Open No. 10-098026 (Patent Document 1) describes a technique for improving the ashing rate of a resist film after ion implantation and suppressing the etching of the underlying silicon oxide film. Specifically, when ashing while heating a wafer placed in a processing vessel with a halogen lamp, hydrogen gas (H ₂ ), nitrogen gas (N ₂ ), oxygen gas (O ₂ ), and fluorocarbon gas ( A mixed gas composed of CF ₄ ) is supplied. That is, the resist film formed on the wafer is ashed using a mixed gas composed of hydrogen gas (H ₂ ), nitrogen gas (N ₂ ), oxygen gas (O ₂ ), and fluorocarbon gas (CF ₄ ). Technology is disclosed.
JP-A-10-098026

  Some MISFETs (Metal Insulator Semiconductor Field Effect Transistors) use a polysilicon film doped with conductive impurities as a gate electrode. Such a gate electrode is formed as follows, for example.

  After forming a gate insulating film on the semiconductor substrate, a polysilicon film is formed on the gate insulating film. Subsequently, after forming a resist film on the polysilicon film, the resist film is patterned by performing exposure and development processing. The patterning is performed so as to open a region for forming the gate electrode. Subsequently, an n-type impurity such as phosphorus is introduced into the polysilicon film exposed from the opening by using an ion implantation method. At this time, phosphorus is mainly introduced into the polysilicon film exposed from the opening, but phosphorus is also introduced into the patterned resist film. When phosphorus is introduced into the resist film, the resist film is altered, and a hardened layer with poor peelability is formed on the surface of the resist film.

  Next, after removing the patterned resist film by an ashing process, the polysilicon film is processed using a photolithography technique and an etching technique. As a result, a gate electrode made of a polysilicon film into which phosphorus is introduced can be formed.

  The resist film used as a mask when introducing phosphorus is removed by ashing as described above, and oxygen gas is used in this ashing. That is, the resist film is removed using a chemical reaction between oxygen gas and the resist film. However, the ashing process using only oxygen gas cannot remove the hardened layer formed on the resist film. For this reason, the resist film under the hardened layer expands due to the heating in the ashing process, and the resist film breaks through the hardened layer. Resist residues resulting from this rupture are not removed and remain on the wafer as foreign matter.

  Therefore, not only oxygen gas but also forming gas is introduced in the ashing process of the resist film in which phosphorus is implanted to form a hardened layer. The forming gas is a mixed gas of nitrogen gas and hydrogen gas. By introducing the forming gas, the cured layer formed on the resist film can be removed.

  However, when the ratio of the forming gas is increased, there is a problem that an abnormal product made of silicon oxide is generated on the polysilicon film. That is, when removing the resist film, phosphorus, forming gas, and oxygen gas contained in the resist film react to generate phosphoric acid. In addition, the polysilicon film exposed by removing the resist film reacts with nitrogen gas to form a silicon nitride film. Then, the phosphoric acid and the silicon nitride film chemically react to generate a silicon oxide film. In this way, silicon oxide, which is an abnormal product, is formed on the polysilicon film exposed by removing the resist film.

  When the removal of the resist film is completed, the polysilicon film is then processed to form a gate electrode. The gate electrode is formed by first forming a resist film on the polysilicon film and then patterning the resist film so that the resist film remains only on the gate electrode formation region. Subsequently, the polysilicon film is etched using the patterned resist film as a mask to form a gate electrode.

  Etching at this time is performed with a high etching selectivity between the polysilicon film and the gate insulating film (silicon oxide film). Here, as described above, on the polysilicon film, there is a region where silicon oxide which is an abnormal product is formed. In this region, a problem arises that etching is not sufficiently performed because silicon oxide, which is an abnormal product, becomes a mask during etching. That is, if silicon oxide, which is an abnormal product, is present in a region other than the gate electrode formation region, the polysilicon film that should be etched remains without being sufficiently etched. Then, a normal MISFET is not formed.

  An object of the present invention is to provide a technique capable of suppressing the generation of abnormal products in the step of removing a resist film introduced with n-type impurities.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  One invention disclosed in the present application includes (a) a step of forming a gate insulating film on a semiconductor substrate, (b) a step of forming a silicon film on the gate insulating film, and (c) on the silicon film. Forming a resist film on the substrate, (d) forming an opening in the resist film, (e) introducing an n-type impurity into the silicon film exposed from the opening, and (f) fluorine. A step of removing the resist film using a mixed gas containing no hydrogen, and (g) a step of processing the silicon film to form a gate electrode, wherein in the step (f) The volume ratio of the forming gas contained in the mixed gas is 5% or more and 30% or less.

  One invention disclosed in the present application is a semiconductor manufacturing apparatus that removes a resist film formed on a wafer by using an oxygen gas and a forming gas, and (a) the semiconductor film is formed on the wafer. A chamber for removing the resist film; (b) a first mass flow controller for adjusting the flow rate of the oxygen gas introduced into the chamber; and (c) a flow rate of the forming gas introduced into the chamber. A second mass flow controller; and (d) a control unit that inputs the flow rate value of the oxygen gas from the first mass flow controller and inputs the flow rate value of the forming gas from the second mass flow controller. The oxygen gas and the forming gas based on the flow rate value of the oxygen gas and the flow rate value of the forming gas. The volume ratio of the forming gas with respect to the entire mixed gas containing the liquid is calculated, and the wafer is processed when the calculated volume ratio is in the range of 5% to 30%, while the calculated volume ratio is 5%. When it is out of the range of 30% or less, the processing of the wafer is stopped.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Since the resist film into which the n-type impurity is introduced is removed in a state where the volume ratio of the forming gas to the entire mixed gas is 5% or more and 30% or less, generation of abnormal products can be suppressed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a schematic diagram showing a schematic configuration of a resist film removing apparatus (semiconductor manufacturing apparatus) in the first embodiment. In FIG. 1, a resist film removing apparatus 1 according to the first embodiment includes a chamber 2, a mass flow controller (first mass flow controller) 3, a mass flow controller (second mass flow controller) 4, and a control unit 5.

  The chamber 2 is a sealed container for causing a physical or chemical reaction therein. In the first embodiment, the resist film for ion implantation formed on the wafer is removed in the chamber 2.

The mass flow controller 3 can adjust the flow rate of oxygen gas (O ₂ gas) introduced into the chamber 2. Similarly, the mass flow controller 4 is configured to adjust the flow rate of the forming gas (mixed gas of H ₂ gas and N ₂ gas) introduced into the chamber 2. Thus, oxygen gas and forming gas whose flow rates are adjusted by the mass flow controllers 3 and 4 are introduced into the chamber 2. Then, using the introduced oxygen gas and forming gas, the resist film for ion implantation is removed.

  The control unit 5 is configured to control the gas ratio between the oxygen gas and the forming gas introduced into the chamber 2. Specifically, the control unit 5 is connected to the mass flow controller 3 and the mass flow controller 4, and can input the flow rate value of oxygen gas from the mass flow controller 3 and can input the flow rate value of forming gas from the mass flow controller 4. It is like that. And the control part 5 calculates the volume ratio of the forming gas with respect to the whole mixed gas which combined oxygen gas and forming gas from the input flow rate value. The control unit 5 is connected to a host computer 6 and is configured so that process information can be input from the host computer 6. The process information refers to information indicating which process is performed.

  In the resist film removing apparatus 1, a wafer is taken out from the wafer lot 7 and the taken out wafer is transferred into the chamber 2.

  The resist film removing apparatus 1 according to the first embodiment aims to remove the ion implantation resist film formed on the silicon film. For this reason, the process in which the resist film removing apparatus 1 according to the first embodiment is used is, for example, for a mask formed on a polysilicon film after introducing phosphorus into the gate electrode formation region of the polysilicon film. This is a step of removing the resist film.

  FIG. 2 is a flowchart showing a part of a manufacturing process of an n-channel type MISFET (Metal Insulator Semiconductor Field Effect Transistor). As shown in FIG. 2, after forming a gate insulating film (S11), a polysilicon film is formed on the gate insulating film (S12). Then, an ion implantation resist film is formed on the polysilicon film (S13), and then the ion implantation resist film is patterned (S14). Next, phosphorus is implanted into the gate electrode formation region of the polysilicon film using the patterned ion implantation resist film as a mask (S15). Then, the ion implantation resist film used as a mask is removed (S16). Subsequently, after washing (S17) and annealing (S18), the polysilicon film is etched to form a gate electrode (S19). In this way, the gate electrode of the n-channel type MISFET is formed. Of the steps shown in FIG. 2, the step in which the resist film removing apparatus 1 is used is S16 for removing the ion implantation resist film used as a mask.

  In the resist film for ion implantation used in the above process, a hardened layer is formed on the surface of the resist film by ion implantation of phosphorus.

  Usually, oxygen gas is used to remove the resist film. However, as described above, a cured layer in which the resist film is altered is formed on the surface of the resist film for ion implantation. This hardened layer cannot be sufficiently removed by ashing with oxygen gas. Therefore, a forming gas made of a mixed gas of hydrogen gas and nitrogen gas is introduced into the chamber 2. By introducing the forming gas, the hardened layer formed on the surface of the resist film is removed, and the resist residue can be reduced.

  However, when the ratio of the forming gas is increased, the hardened layer can be effectively removed in the resist film introduced with phosphorus, while an abnormal product made of silicon oxide is formed. This abnormal product is considered to be formed in the following process. First, the resist film for ion implantation formed on the polysilicon film is removed by ashing with oxygen gas and forming gas. At this time, phosphoric acid is formed by the reaction of phosphorus, oxygen gas, and hydrogen gas introduced into the resist film. On the other hand, a silicon nitride film is formed on the surface of the polysilicon film by reaction with nitrogen gas. Then, the phosphoric acid and the silicon nitride film react to form an abnormal product made of silicon oxide. In this process of removing the resist film introduced with phosphorus, an abnormal product made of silicon oxide is formed.

  Thereafter, the polysilicon film is processed to form a gate electrode. In the step of forming the gate electrode, the polysilicon film is etched in a state with a high selectivity with respect to the silicon oxide film. Therefore, if there is an abnormal product made of silicon oxide on the polysilicon film, the abnormal product serves as a mask, and the polysilicon film in the region to be originally etched is not sufficiently etched. Does not form normally.

  Therefore, in the first embodiment, by forming the volume ratio of the forming gas with respect to the entire mixed gas of oxygen gas and forming gas to 5% or more and 30% or less, the resist residue is removed and abnormal products made of silicon oxide are removed. Occurrence is suppressed.

  FIG. 3 is a graph showing the relationship between the volume ratio of the forming gas to the entire mixed gas of oxygen gas and forming gas, and the resist residue ratio and abnormal product ratio. That is, the graph shows the relationship between the amount of forming gas added during ashing of the resist film for ion implantation, the resist residue ratio, and the abnormal product ratio. In FIG. 3, the horizontal axis indicates the volume ratio of the forming gas, and the vertical axis indicates the resist residue ratio and the abnormal product ratio. Moreover, the square plot in the graph shows the resist residue ratio, and the diamond plot shows the abnormal product ratio.

  The resist residue ratio is a numerical value when the resist residue is 1 when no forming gas is added (when the volume ratio of the forming gas is 0%). The abnormal product ratio is a numerical value when the number of abnormal products is 1 when the volume ratio of the forming gas is 50%.

  As shown in FIG. 3, it can be seen that the resist residue ratio decreases when the volume ratio of the forming gas is increased. For example, it can be seen that when the volume ratio of the forming gas is 0%, the resist residue ratio is 1, but when the volume ratio of the forming gas is 5%, the resist residue ratio is reduced to about 0.15. Further, it can be seen that when the volume ratio of the forming gas is 10%, the resist residue ratio is about 0.05, and when the volume ratio of the forming gas is 20%, the resist residue ratio is extremely small. This shows that the resist residue can be sufficiently removed by increasing the amount of forming gas added to the oxygen gas.

  On the other hand, it can be seen that the ratio of abnormal products generated by introducing the forming gas increases as the volume ratio of the forming gas increases. For example, when the volume ratio of the forming gas is 10% or less, the abnormal product ratio is almost 0, and when the volume ratio of the forming gas is 30%, the abnormal product ratio is about 0.15. Further, when the volume ratio of the forming gas is 40%, the abnormal product ratio is about 0.5, and when the volume ratio of the forming gas is 50%, the abnormal product ratio is 1. This shows that the generation of abnormal products can be suppressed as the amount of forming gas added to oxygen gas is decreased.

  Thus, from the viewpoint of removing resist residues, it is desirable to increase the volume ratio of the forming gas. On the other hand, from the viewpoint of suppressing the occurrence of abnormal products, it is desirable to reduce the volume ratio of the forming gas. Therefore, extremely increasing or decreasing the volume ratio of the forming gas is not preferable in consideration of both viewpoints. Considering both aspects, it is necessary to limit the volume ratio of the forming gas to a specific range. As shown in FIG. 3, when the volume ratio of the forming gas is 5% or more and 30% or less, the resist residue can be effectively removed and the generation of abnormal products can be suppressed. Specifically, the resist residue ratio and the abnormal product ratio can be reduced to 0.2 or less by setting the volume ratio of the forming gas to 5% or more and 30% or less. More desirably, the resist residue ratio and the abnormal product ratio can be made 0.1 or less by setting the volume ratio of the forming gas to 10% or more and 20% or less.

  Next, a first operation example of the resist film removal apparatus 1 according to the first embodiment will be described with reference to FIGS. First, the control unit 5 shown in FIG. 1 inputs process information from the host computer 6 (S101). Based on the process information, it is determined whether the process to be performed is a phosphorus ion implantation resist film removal process (S102). When the step to be performed is not the step of removing the resist film for phosphorus ion implantation, the control unit 5 does not monitor the volume ratio of the forming gas (S103). On the other hand, when the step to be performed is a step of removing the resist film for phosphorus ion implantation, the control unit 5 uses the flow rate value of the oxygen gas sent from the mass flow controller 3 and the flow rate value of the forming gas sent from the mass flow controller 4. Enter. Then, the volume ratio of the forming gas is calculated based on the input flow rate value (S104).

  Subsequently, the control unit 5 determines whether the calculated volume ratio of the forming gas is 5% or more and 30% or less (S105). If the calculated volume ratio of the forming gas is outside the range of 5% to 30%, the apparatus is stopped (S106). Thereby, processing of the wafer in a state where a resist residue or an abnormal product is generated is suppressed. Therefore, it is possible to prevent the formation of a defective wafer, and it is possible to improve yield and product reliability.

  On the other hand, if the calculated volume ratio of the forming gas is in the range of 5% to 30%, the wafer is processed. That is, the phosphorus ion implantation resist film formed on the wafer is removed. At this time, since the volume ratio of the forming gas is 5% or more and 30% or less, the generation of resist residues and abnormal products can be suppressed. Therefore, it is possible to improve yield and product reliability.

  Next, a second operation example of the resist film removing apparatus 1 according to the first embodiment will be described with reference to FIGS. Since the second operation example is almost the same as the first operation example, only different parts will be described. In the second operation example, the difference from the first operation example is processing when the volume ratio of the forming gas is outside the range of 5% to 30%. In this case, in the first operation example, the resist film removing apparatus 1 is stopped. On the other hand, in the second operation example, the resist film removing apparatus 1 is not stopped. That is, when the volume ratio of the forming gas is outside the range of 5% to 30%, the control unit 5 adjusts the mass flow controllers 3 and 4 so that the volume ratio of the forming gas introduced into the chamber 2 is 5 It should be within the range of 30% to 30%. Accordingly, the wafer can be processed within a range where the volume ratio of the forming gas is always 5% or more and 30% or less without stopping the resist film removing apparatus 1. According to the second operation example, the same effect as in the first operation example can be obtained, and the resist film removing apparatus 1 is not stopped. Therefore, throughput can be improved and TAT (Turn Around Time) can be shortened.

  Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to the drawings. In the first embodiment, for example, a manufacturing process of a CMISFET (Complementary Metal Insulator Semiconductor Field Effect Transistor) will be described.

  As shown in FIG. 6, a semiconductor substrate (wafer) 10 is prepared. The semiconductor substrate 10 is made of p-type single crystal silicon, and an element isolation region 11 is formed on the main surface thereof. The element isolation region 11 is made of silicon oxide and is formed by, for example, an STI (Shallow Trench Isolation) method or a LOCOS (Local Oxidization Of Silicon). FIG. 6 shows the element isolation region 11 formed by the STI method. That is, FIG. 6 shows an element isolation region 11 formed by forming a groove in the semiconductor substrate 10 and then embedding a silicon oxide film in the groove.

Next, the active regions separated by isolation regions 11 formed on the semiconductor substrate 10, i.e., to form a p-type well 12 in the region for forming the n-channel type MISFET Q _1. The p-type well 12 is formed by introducing boron (B) or boron fluoride (BF ₂ ), for example, by ion implantation. Similarly, to form the n-type well 13 in the region for forming the p-channel type MISFET Q _2. The n-type well 13 is formed by introducing phosphorus (P) or arsenic (As) by, for example, ion implantation.

  Subsequently, as shown in FIG. 7, a gate insulating film 14 is formed on the semiconductor substrate 10. The gate insulating film 14 is made of, for example, a thin silicon oxide film, and can be formed using, for example, a thermal oxidation method.

Next, as shown in FIG. 8, a polysilicon film 15 is formed on the gate insulating film 14. The polysilicon film 15 can be formed by, for example, a CVD (Chemical Vapor Deposition) method. Thereafter, a resist film 16 is applied on the polysilicon film 15. Then, the resist film 16 is patterned by exposing and developing the resist film 16. Patterning, as shown in FIG. 9, performed to form an opening 17 in the gate electrode formation region of the n-channel type MISFET Q _1.

Subsequently, as shown in FIG. 10, phosphorus is ion-implanted using the patterned resist film 16 as a mask. As a result, phosphorus is injected into the polysilicon film 15 exposed from the opening 17 and phosphorus is also injected into the surface of the resist film 16. In the step of implanting phosphorus ions, phosphorus is introduced into the gate electrode formation region made of the polysilicon film 15, but phosphorus is also implanted into the resist film 16 used as a mask. At this time, the surface of the resist film 16 is altered by ion implantation of phosphorus, and a hardened layer 16a is formed. Note that phosphorus is introduced in an amount of 5 × 10 ¹⁴ / cm ² or more.

  Next, in order to remove the resist film 16 including the hardened layer 16a used as a mask, the semiconductor substrate 10 is carried into the resist film removing apparatus 1 according to the first embodiment. Then, as shown in FIG. 11, after heating the semiconductor substrate 10, the mixed gas 18 of oxygen gas and forming gas (for example, a mixed gas of 3% hydrogen gas and 97% nitrogen gas) is converted into plasma to form on the resist film 16 To introduce. Then, the resist film 16 including the hardened layer 16a is removed. Here, the volume ratio of the forming gas to the entire mixed gas 18 of oxygen gas and forming gas is 5% or more and 30% or less. Further, the flow rate of the forming gas is, for example, in the range of 100 sccm to 10,000 sccm. Specifically, for example, when the total flow rate of oxygen gas and forming gas is 4000 sccm, the flow rate of forming gas can be 400 sccm. At this time, the volume ratio of the forming gas is 10%. For this reason, when removing the hardened layer 16a and the resist film 16 containing phosphorus, the resist residue can be sufficiently removed, and generation of abnormal silicon oxide-based products due to phosphorus is also suppressed.

  Here, conventionally, in order to remove the resist film 16 including the hardened layer 16a, a fluorine-based gas may be introduced in addition to the oxygen gas and the forming gas. However, the fluorine-based gas has a problem of etching the underlying polysilicon film. Therefore, when the resist film 16 is removed using a fluorine-based gas, the polysilicon film 15 exposed from the opening 17 is etched by the fluorine-based gas. On the other hand, the polysilicon film 15 covered with the resist film 16 is not etched. For this reason, a level difference occurs in the polysilicon film 15 after the resist film 16 is removed. However, the first embodiment has an advantage that no step is generated in the polysilicon film 15 because no fluorine-based gas is used.

After removing the resist film 16 including the hardened layer 16a, cleaning and annealing are performed, so that the polysilicon film 15 is exposed as shown in FIG. Here, although not shown in FIG. 12, phosphorus is implanted into the gate electrode formation region of the n-channel MISFET Q _{1 in} the polysilicon film 15.

Subsequently, as shown in FIG. 13, after a resist film 19 is formed on the polysilicon film 15, the resist film 19 is exposed and developed to be patterned. Patterning is performed to form an opening 20 in the p-channel type MISFET Q ₂ of the gate electrode forming region. Thereafter, boron (B) is implanted into the polysilicon film 15 exposed from the opening 20 by ion implantation using the patterned resist film 19 as a mask. At this time, boron is also implanted into the surface of the resist film 19 functioning as a mask, and a hardened layer 19 a is formed on the surface of the resist film 19.

  Next, as shown in FIG. 14, a mixed gas of oxygen gas and forming gas is introduced onto the resist film 19. Then, the resist film 19 including the hardened layer 19a is removed. Here, boron, not phosphorus, is implanted into the resist film 19. When removing the resist film 19 into which boron is implanted with the mixed gas 21 of oxygen gas and forming gas, no abnormal product is generated. Therefore, the volume ratio of the forming gas need not be in the range of 5% to 30%. That is, when removing the resist film 19 implanted with boron, it is not necessary to consider the generation of abnormal products, and the volume ratio of the forming gas may be determined from the viewpoint that the resist residue can be sufficiently removed. . That is, the abnormal product is generated when the resist film 16 implanted with phosphorus is removed, and is not generated when the resist film 19 implanted with boron is removed.

By removing the resist film 19 and then performing cleaning and annealing, the polysilicon film 15 is exposed as shown in FIG. Here, although not shown in FIG. 15, phosphorus is implanted into the gate electrode formation region of the n-channel type MISFET Q _{1 in} the polysilicon film 15. Similarly, boron is implanted into the gate electrode formation region of the p-channel type MISFET Q _{2 in} the polysilicon film 15.

  Next, the polysilicon film 15 is processed using a photolithography technique and an etching technique to form gate electrodes 22a and 22b as shown in FIG. Here, in the first embodiment, since the silicon oxide-based abnormal product is hardly generated on the polysilicon film 15, the gate electrodes 22a and 22b can be formed normally. That is, it is possible to prevent the abnormal product from being sufficiently etched by using the abnormal product as a mask.

The gate electrode 22a becomes a gate electrode of the n-channel type MISFET Q _1, the gate electrode 22b becomes a gate electrode of the p-channel type MISFET Q _2.

  Subsequently, as shown in FIG. 17, by introducing n-type impurities such as phosphorus and arsenic on both sides of the gate electrode 22a using a photolithography technique and an ion implantation method, a low-concentration n-type impurity diffusion region 23, 24 is formed. Similarly, low-concentration p-type impurity diffusion regions 25 and 26 are formed by introducing p-type impurities such as boron on both sides of the gate electrode 22b using a photolithography technique and an ion implantation method.

  Next, after forming a silicon oxide film on the semiconductor substrate 10, side walls 27 are formed on the side walls of the gate electrodes 22 a and 22 b by performing anisotropic etching. Then, as shown in FIG. 18, high-concentration n-type impurity diffusion regions 28 and 29 are formed by introducing n-type impurities such as phosphorus and arsenic using a photolithography technique and an ion implantation method. Similarly, high-concentration p-type impurity diffusion regions 30 and 31 are formed by introducing p-type impurities such as boron by using a photolithography technique and an ion implantation method.

  Next, after exposing the surfaces of the high-concentration n-type impurity diffusion regions 28 and 29 and the high-concentration p-type impurity diffusion regions 30 and 31, a cobalt (Co) film is formed on the semiconductor substrate 10 by using, for example, a CVD method. Deposit. Then, a cobalt silicide film 32 is formed by performing heat treatment. Thereby, the gate electrodes 22a and 22b made of the polysilicon film 15 and the cobalt silicide film 32 can be formed. Further, a cobalt silicide film 32 can be formed in the high concentration n-type impurity diffusion regions 28 and 29 and the high concentration p-type impurity diffusion regions 30 and 31.

In this way, the low concentration n-type impurity diffusion region 23, the source region of the n-channel type MISFET Q ₁ is formed by high concentration n-type impurity diffusion regions 28 and cobalt silicide film 32, the low-concentration n-type impurity diffusion regions 24, high a drain region of the n-channel type MISFET Q ₁ is formed by the concentration n-type impurity diffusion regions 29 and cobalt silicide film 32. Similarly, the source region of the p-channel MISFET Q ₂ is formed by the low-concentration p-type impurity diffusion region 25, the high-concentration p-type impurity diffusion region 30, and the cobalt silicide film 32, and the low-concentration p-type impurity diffusion region 26, high-concentration p The drain region of the p-channel type MISFET Q ₂ is formed by the type impurity diffusion region 31 and the cobalt silicide film 32.

  Here, for example, when forming the high-concentration n-type impurity diffusion regions 28 and 29, phosphorus ions are implanted using the resist film as a mask. At this time, phosphorus is also implanted into the resist film used as a mask. Then, after the high-concentration n-type impurity diffusion regions 28 and 29 are formed, the resist film used as a mask is removed. For removing the resist film, oxygen gas and forming gas are used. Depending on the volume ratio of the forming gas, abnormal silicon oxide-based products are formed as described above. If this abnormal product is formed on the high-concentration p-type impurity diffusion regions 30 and 31 covered with, for example, a resist film, the silicon oxide formed on the high-concentration p-type impurity diffusion regions 30 and 31 The film thickness is thicker than other areas. Then, when the surfaces of the high concentration p-type impurity diffusion regions 30 and 31 are exposed to form the cobalt silicide film 32, the surfaces of the high concentration p-type impurity diffusion regions 30 and 31 are not exposed, and the cobalt silicide film 32 is formed. There is a risk that it will not be formed. Therefore, when removing the resist film into which phosphorus has been implanted, it is desirable that the volume ratio of the forming gas to the entire mixed gas of oxygen gas and forming gas is 5% or more and 30% or less.

In this way, I am possible to form the n-channel type MISFET Q ₁ and p-channel type MISFET Q _2.

  Next, the wiring process will be described with reference to FIG. On the semiconductor substrate 10, an insulating film 40 to be an interlayer insulating film is deposited using, for example, a CVD method. Thereafter, a contact hole 41 penetrating the insulating film 40 is formed by using a photolithography technique and an etching technique. At the bottom of contact hole 41, cobalt silicide film 32 formed in high concentration n-type impurity diffusion regions 28 and 29 and high concentration p-type impurity diffusion regions 30 and 31 is exposed.

  Next, a plug 43 in which a titanium / titanium nitride film 42a and a tungsten film 42b are embedded in the contact hole 41 is formed. The plug 43 can be formed as follows, for example. First, a titanium / titanium nitride film 42a is formed on the insulating film 40 including the inside of the contact hole 41 by using, for example, a sputtering method, and then a tungsten film 42b is embedded in the contact hole 41 by using, for example, a CVD method. To form. Then, the unnecessary titanium / titanium nitride film 42a and the tungsten film 42b formed on the insulating film 40 are removed by using a CMP method or an etch back method, thereby forming the plug 43.

  Subsequently, a titanium / titanium nitride film 44a, an aluminum film 44b, and a titanium / titanium nitride film 44c are sequentially formed on the insulating film 40 on which the plug 43 is formed. These films can be formed using, for example, a sputtering method. Then, using the photolithography technique and the etching technique, the titanium / titanium nitride film 44a, the aluminum film 44b, and the titanium / titanium nitride film 44c are patterned to form the wiring 45.

  According to the first embodiment, when removing the resist film implanted with phosphorus, the volume ratio of the forming gas to the entire mixed gas of oxygen gas and forming gas is set to 5% or more and 30% or less. While being able to remove enough, generation | occurrence | production of an abnormal product can be suppressed. Therefore, it is possible to improve product yield and reliability.

  In the first embodiment, the example in which the polysilicon film is formed on the base of the resist film into which phosphorus is implanted has been described. However, the present invention is not limited to this. For example, the base is formed of a single crystal silicon film or an amorphous silicon film. It can be applied even if it is.

(Embodiment 2)
In the first embodiment, the example in which oxygen gas and forming gas are used when removing the resist film implanted with phosphorus has been described. In the second embodiment, an example in which the process of removing the resist film implanted with phosphorus is in two stages will be described.

  Since the CMISFET manufacturing method according to the second embodiment is substantially the same as that of the first embodiment, only different parts will be described. 6 to 11 are the same as those in the first embodiment.

  As shown in FIG. 11, the hardened layer 16a and the resist film 16 into which phosphorus has been implanted are removed by introducing a mixed gas 18 of oxygen gas and forming gas (first stage). At this time, the volume ratio of the forming gas to the entire mixed gas is 5% or more and 30% or less. Subsequently, when the resist film 16 is removed and the underlying polysilicon film begins to be exposed, a mixed gas 47 of oxygen gas, forming gas, and fluorine-based gas is introduced as shown in FIG. The resist residue 46 is removed (second stage). As described above, in the second embodiment, the gas used for removing the hardened layer 16a and the resist film 16 is basically oxygen gas and forming gas, but the removal of the resist residue 46 from the hardened layer 16a is accelerated. In order to achieve this, fluorine-based gas is used. Thereby, the hardened layer 16a and the resist film 16 can be quickly removed.

When the fluorine-based gas is used, the underlying polysilicon film 15 is scraped. In order to suppress the amount of scraping, for example, SF ₆ gas is used as the fluorine-based gas. Here, when SF ₆ gas is used from the first stage of removing the resist film 16 (the stage shown in FIG. 14), the removal of the resist film 16 proceeds and the polysilicon film exposed from the opening 17 of the resist film 16 15 will be cut off. For this reason, a step is formed between the polysilicon film 15 covered with the resist film 16 and the polysilicon film 15 exposed from the opening 17.

Therefore, in the second embodiment, a mixed gas 18 of oxygen gas and forming gas is used in the first stage of removing the resist film 16. Then, SF ₆ gas is used when the resist film 16 is removed and the underlying polysilicon film begins to be exposed. In this case, the polysilicon film 15 is shaved to some extent, but the same degree of shaving occurs on the entire polysilicon film 15, so that it is covered with the polysilicon film 15 exposed from the opening 17 and the resist film 16. There is no step between the polysilicon film 15. That is, the SF ₆ gas is added to accelerate the removal of the resist residue 46 made of the hardened layer 16a after the resist film 16 serving as a mask disappears, so that the above-described problem does not occur.

FIG. 21 is a graph showing the relationship between the amount of removal of the polysilicon film (nm) and the amount of SF ₆ gas added (%). Here, the amount of SF ₆ gas shows a flow ratio of SF ₆ gas to the total amount of the forming gas and SF ₆ gas. As shown in FIG. 21, when the amount of SF ₆ gas added is increased from 1% to 2%, the amount of the polysilicon film is also increased from 1 nm to 5 nm. That is, it can be seen that the amount of shaving of the polysilicon film increases as the amount of SF ₆ gas added increases. Therefore, in order to suppress the abrasion of the polysilicon film serving as an underlying, it is necessary to minimize the proportion of SF ₆ gas to the total flow rate of the forming gas and SF ₆ gas, for example, it is desirable to below 2%.

According to the second embodiment, in the first stage of removing the resist film 16, only the oxygen gas and the forming gas are used, and the volume ratio of the forming gas is set to 5% or more and 30% or less. While being able to remove enough, generation | occurrence | production of the abnormal product resulting from phosphorus can be suppressed. Further, since SF ₆ gas is added in the second stage of removing the resist residue made of the hardened layer 16a, the resist residue can be removed quickly.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The semiconductor device manufacturing method and the semiconductor manufacturing apparatus of the present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

It is the schematic diagram which showed schematic structure of the resist film removal apparatus of this invention. 6 is a flowchart showing a part of a manufacturing process of an n-channel type MISFET. It is the graph which showed the relationship between the volume ratio of the forming gas with respect to the whole mixed gas of oxygen gas and forming gas, and a resist residue ratio and an abnormal product ratio. It is the flowchart which showed the 1st operation example of the resist film removal apparatus. It is the flowchart which showed the 2nd operation example of the resist film removal apparatus. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 6; FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 7; FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 8; FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 9; FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 10; FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 11; FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 12; FIG. 14 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 13; FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 14; FIG. 16 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 15; FIG. 17 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 16; FIG. 18 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 17; FIG. 19 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 18; 11 is a cross-sectional view showing a manufacturing step of the semiconductor device in the second embodiment. FIG. Is a graph showing the relationship between the flow rate ratio of the wear amount and SF ₆ gas of the polysilicon film.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Resist film removal apparatus 2 Chamber 3 Mass flow controller 4 Mass flow controller 5 Control part 6 Host computer 7 Wafer lot 10 Semiconductor substrate 11 Element isolation region 12 P-type well 13 N-type well 14 Gate insulating film 15 Polysilicon film 16 Resist film 16a Hardened layer Reference Signs List 17 opening 18 mixed gas 19 resist film 19a hardened layer 20 opening 21 mixed gas 22a gate electrode 22b gate electrode 23 low concentration n-type impurity diffusion region 24 low concentration n-type impurity diffusion region 25 low concentration p-type impurity diffusion region 26 low Concentration p type impurity diffusion region 27 Side wall 28 High concentration n type impurity diffusion region 29 High concentration n type impurity diffusion region 30 High concentration p type impurity diffusion region 31 High concentration p type impurity diffusion region 32 Cobalt silicide film 40 Insulating film 41 Contact hole 42a titanium / titanium nitride film 42b tungsten film 43 plugs 44a titanium / titanium nitride film 44b an aluminum film 44c titanium / titanium nitride film 45 wirings 46 resist residues 47 mixed gas

Claims (6)

(A) forming a gate insulating film on the semiconductor substrate;
(B) forming a silicon film on the gate insulating film;
(C) forming a resist film on the silicon film;
(D) forming an opening in the resist film;
(E) introducing phosphorus into the silicon film exposed from the opening;
(F) removing the resist film using a mixed gas containing at least oxygen gas and forming gas and not containing fluorine;
(G) processing the silicon film to form a gate electrode,
In the step (f), the volume ratio of the forming gas contained in the mixed gas to the entire mixed gas is 5% or more and 30% or less. (A) forming a gate insulating film on the semiconductor substrate;
(B) forming a silicon film on the gate insulating film;
(C) forming a resist film on the silicon film;
(D) forming an opening in the resist film;
(E) introducing phosphorus into the silicon film exposed from the opening;
(F) removing the resist film using a mixed gas containing at least oxygen gas and forming gas and not containing fluorine;
(G) processing the silicon film to form a gate electrode,
In the step (f), the volume ratio of the forming gas contained in the mixed gas to the entire mixed gas is 10% or more and 20% or less. (A) forming a gate insulating film on the semiconductor substrate;
(B) forming a silicon film on the gate insulating film;
(C) forming a resist film on the silicon film;
(D) forming an opening in the resist film;
(E) introducing phosphorus into the silicon film exposed from the opening;
(F) removing the resist film;
(G) processing the silicon film to form a gate electrode,
In the step (f), after using a first mixed gas composed of at least oxygen gas and forming gas and not containing fluorine, the resist film is removed using a second mixed gas containing fluorine, and the first mixed gas is removed. The method for manufacturing a semiconductor device, wherein a volume ratio of the forming gas contained in the gas to the entire first mixed gas is 5% or more and 30% or less. (A) forming a gate insulating film on the semiconductor substrate;
(B) forming a silicon film on the gate insulating film;
(C) forming a resist film on the silicon film;
(D) forming an opening in the resist film;
(E) introducing phosphorus into the silicon film exposed from the opening;
(F) removing the resist film;
(G) processing the silicon film to form a gate electrode,
In the step (f), after using a first mixed gas composed of at least oxygen gas and forming gas and not containing fluorine, the resist film is removed using a second mixed gas containing fluorine, and the first mixed gas is removed. The method for manufacturing a semiconductor device, wherein a volume ratio of the forming gas contained in the gas to the entire first mixed gas is 10% or more and 20% or less. A semiconductor manufacturing apparatus for removing a resist film formed on a wafer by using an oxygen gas and a forming gas,
(A) a chamber for removing the resist film formed on the wafer;
(B) a first mass flow controller that adjusts the flow rate of the oxygen gas introduced into the chamber;
(C) a second mass flow controller that adjusts the flow rate of the forming gas introduced into the chamber;
(D) a control unit that inputs a flow value of the oxygen gas from the first mass flow controller and inputs a flow value of the forming gas from the second mass flow controller;
The control unit calculates a volume ratio of the forming gas to the entire mixed gas including the oxygen gas and the forming gas based on the flow rate value of the oxygen gas and the flow rate value of the forming gas, and the calculated volume ratio A semiconductor manufacturing apparatus that performs processing of the wafer when the value is within a range of 5% to 30%, and stops processing the wafer when the calculated volume ratio is outside the range of 5% to 30%. A semiconductor manufacturing apparatus for removing a resist film formed on a wafer by using an oxygen gas and a forming gas,
(A) a chamber for removing the resist film formed on the wafer;
(B) a first mass flow controller that adjusts the flow rate of the oxygen gas introduced into the chamber;
(C) a second mass flow controller for adjusting the flow rate of the forming gas introduced into the chamber;
(D) a control unit that inputs a flow value of the oxygen gas from the first mass flow controller and inputs a flow value of the forming gas from the second mass flow controller;
The control unit calculates a volume ratio of the forming gas to the entire mixed gas including the oxygen gas and the forming gas based on the flow rate value of the oxygen gas and the flow rate value of the forming gas, and the calculated volume ratio Is outside the range of 5% or more and 30% or less, a semiconductor manufacturing apparatus that controls the first mass flow controller and the second mass flow controller to set the volume ratio to 5% or more and 30% or less.

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