JP2006172030A - Method for obtaining time data in digital processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the load of a CPU substantially by shortening the control time of the CPU substantially for obtaining time data from a clock device connected to the CPU through an I2C bus. <P>SOLUTION: In a device which directly controls an I2C bus by the software processing of an CPU 11, and performs digital processing based on the time data obtained from a clock IC device (RTC) 15 connected to the I2C bus, the time data is obtained from the clock device through the I2C device at the time of start-up of the device and is stored in an internal memory 13. At each interrupt of a constant frequency from an internal timer 11A, the time data stored in the internal memory is incremented by the time corresponding to the frequency, and the time data stored in the internal memory is read out when it is needed. The present invention includes an acquirement of time data from the clock device at regular time intervals or at a specified time, and rewriting of the time data stored in the internal memory with the acquired time data. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method of acquiring time data of a clock device to the CPU side of the digital processing device via the I2C bus in a digital processing device connected with input / output devices via the I2C bus.

  The I2C bus (trade name) was proposed by Philips in the 1980s, and it is more or less between devices that are relatively close by two signal lines SCL (Serial Clock) and SDA (Serial Data). This is a serial interface for transmitting information. It has a master / slave relationship and can be connected with only two signal lines. It has the characteristics that multiple devices can be connected. Conventionally, it has been developed mainly for home appliances. Yes.

  Devices connected to the I2C bus include a wide variety of devices such as memories, LCD (liquid crystal) drivers, and switches, and one of them is a clock IC (RTC). The clock IC mainly processes date / time data, and the date / time data is acquired and set via the I2C bus.

  As shown in FIG. 5, the I2C bus connects the I2C bus controller IC1 as a master of the bus and other devices 2, 3, 4, 5,. In general, various data are input and output (see, for example, Non-Patent Document 1).

However, there is a method in which the I2C bus controller IC1 is omitted and the I2C bus is directly controlled by software processing of a CPU mounted on the digital processing device main body 6 in recent years when a cheaper product is required.
Internet URL (http://jp.semiconducters.philips.com/buses/i2c/facts/index.html), search date (September 10, 2004).

  When the I2C bus controller that omits the I2C bus controller and is simply connected directly to the CPU is configured to control the bus by software, there are the following problems.

  Generates a clock signal (SCL) with a width defined by the I2C bus (usually several μs depending on the bus speed) and outputs / acquires data (SDA). In this case, a signal control time of about several tens of μs per byte is required, and as the number of input / output data increases, the control time also increases in proportion.

  When I2C bus control is executed by software to acquire time data from the RTC, multiple bytes of data (for example, 7 bytes if the year, month, day, hour, minute, second and day of the week are 1 byte each) are input and output. In addition, a control time of several tens μs to several hundreds μs is required.

  For a high-performance CPU in recent years, the signal control time over several tens of μs to several hundreds of μs is too much time to be used only for acquiring time data from the RTC, and is also a waste of processing. Further, data such as date / time information is data that should be constantly updated, and if the date / time data that is constantly advanced is frequently acquired from the RTC, the waste of the above-described processing increases in proportion.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a time data acquisition method capable of greatly reducing the control time of a CPU and greatly reducing the load for acquiring time data from a clock device connected via an I2C bus to the CPU. It is in.

  In order to solve the above-mentioned problems, the present invention accesses the timepiece device connected via the I2C bus only once at the time of starting the apparatus, stores the time data obtained at this time in the internal memory, and thereafter Each time an internal timer of the CPU interrupts the CPU at a certain period, the time data stored in the internal memory is incremented for a time corresponding to the period, and is acquired from the internal memory when the CPU needs the time data. This is characterized by the following method.

(1) The I2C bus is directly controlled by software processing of a CPU mounted on the digital processing apparatus main body, data is input / output to / from a device connected to the I2C bus, and the clock device that is one of the devices In a digital processing apparatus that performs digital processing based on time data acquired via an I2C bus,
The CPU
Acquiring time data from the timepiece device via the I2C bus at the time of activation of the digital processing device;
Storing the time data acquired in the process in an internal memory of the digital processing device;
A process of incrementing time data stored in the internal memory for a time corresponding to the period each time an interrupt of a certain period from the built-in timer,
Reading the time data stored in the internal memory when the time data is needed;
It is provided with.

(2) The I2C bus is directly controlled by software processing of a CPU mounted on the digital processing apparatus main body, data is input to and output from a device connected to the I2C bus, and the clock device that is one of the devices In a digital processing apparatus that performs digital processing based on time data acquired via an I2C bus,
The CPU
Acquiring time data from the timepiece device via the I2C bus at the time of activation of the digital processing device;
Storing the time data acquired in the process in an internal memory of the digital processing device;
A process of incrementing time data stored in the internal memory for a time corresponding to the period each time an interrupt of a certain period from the built-in timer,
Reading the time data stored in the internal memory when the time data is needed;
Obtaining time data from the clock device via the I2C bus at regular time intervals or at a specified time, and rewriting the time data stored in the internal memory with the time data;
It is provided with.

  As described above, according to the present invention, the clock device connected via the I2C bus is accessed only once when the device is started up, and the time data acquired at this time is stored in the internal memory, after which the CPU The time data stored in the internal memory is incremented by the time corresponding to the period every time the CPU interrupts the CPU by a certain period, and the CPU acquires the time data from the internal memory when the time data is needed. Therefore, it is possible to greatly reduce the control time of the CPU and greatly reduce the load for acquiring time data from the clock device to the CPU.

  Furthermore, by acquiring time data from the clock device at regular time intervals or at a specified time, and rewriting the time data stored in the internal memory with the time data, the time data shift due to the error of the internal timer It can be corrected.

(Embodiment 1)
FIG. 1 is a block diagram of a digital processing apparatus showing an embodiment of the present invention, which is applied to a digital relay.

  The basic configuration of the digital relay is as follows: a digital operation unit 10 that performs a protection relay operation in a microcomputer configuration; an analog input unit 20 that acquires a current and voltage signal from a protection target as digital data; and a set value for protection operation and protection The digital input / output unit 30 for trip output of the target circuit breaker and the transmission control unit 40 for data communication with the host computer or the like are connected by a system bus, and the operation state of the protection target as an external device A panel display device 50 for displaying is connected.

  As shown in the configuration example of the CPU board in the figure, the digital arithmetic unit 10 connects a CPU 11, a flash ROM 12 that stores a protection arithmetic program, and a memory (RAM) 13 that stores internal data via an internal bus. The CPU 11 includes a non-volatile memory 14 that stores setting values and the like, a RTC (clock IC) 15 that performs a time data stepping operation, an LCD (liquid crystal) driver, a switch, and other devices via a directly connected I2C bus. Data input / output with the device 16 is enabled.

  In the digital relay having the basic configuration described above, in this embodiment, time data is obtained by executing time data acquisition control software stored as a program in the flash ROM 12 or the like using resources such as the timer 11A built in the CPU 11. To get.

  The above time data acquisition control software has a configuration corresponding to the flowchart shown in FIG. In the figure, when the digital relay is activated, initialization necessary for each unit and various devices such as clearing the memory 13 is performed (S1). Next, the time data is read from the RTC 15 to the CPU 11 side via the I2C bus by executing the instruction of the CPU 11, and the time data is stored in the memory 13 (S2). Thereafter, the original processing of the digital relay such as relay data acquisition and relay calculation by the CPU 11 is executed (S3). In this process (S3), when the time data is necessary, the time data stored in the memory 13 is read instead of being acquired from the RTC 15.

  Here, the time data stored in the memory 13 is updated by an interruption to the CPU 11 by the internal timer 11A (S4). For example, the internal timer 11A generates an interrupt to the CPU 11 at a constant cycle such as 1 second, and the CPU 11 updates time data stored in the memory 13 by this interrupt (time data such as hour / minute / second is updated at a fixed cycle time. Increment by a value corresponding to minutes).

  Therefore, the access to the RTC 15 is performed only once in the first process (S2), and the acquired time data is expanded in the memory 13, and then the interrupt process is executed by the internal timer 11A of the CPU 11, and the memory 13 The developed time data is advanced in software. And when CPU11 acquires time data, it acquires from the time data of the said memory 13. FIG.

  For comparison with the flowchart of the present embodiment shown in FIG. 2, a flowchart of a conventional time data acquisition process is shown in FIG. In FIG. 3, as one of repeated processes, the CPU 11 accesses the RTC 15 to acquire time data and store it in the memory 13 (S3B). When time data is required for relay calculation or the like, processing is performed using the time data stored in the memory 13 (S3A). Repeated access to the RTC 15 (S3B) requires a signal control time of several tens of μs to several hundreds of μs for one reading as described above, and increases the load on the CPU.

  As described above, in the present embodiment, it is not necessary to perform access except for the initial setting of the time data to the RTC 15 and the first reading, and thus the access frequency and the number of times to the RTC 15 via the I2C bus can be set. As much as possible, the control time of the CPU 11 can be greatly reduced and useless processing can be eliminated.

(Embodiment 2)
A flowchart of this embodiment is shown in FIG. 4, and in addition to the processing of the first embodiment, the time data is acquired from the RTC at a fixed cycle and the time data in the internal memory is rewritten.

  In the first embodiment, except for the case of setting time data, access is performed only once at the time of initialization. However, in this embodiment, a certain time (for example, one hour) is waited (S5), and at this time The time data is read from the RTC 15 only once and expanded again in the memory 13 expanded at initialization (S6).

  According to the present embodiment, it is possible to correct a time data shift due to an error of the internal timer 11A at a constant cycle (or at the end of a specific process in the CPU 11).

  Although the above embodiments show the case where the present invention is applied to a digital relay, the present invention can be applied to other digital processing devices that require time data to obtain the same effect. For example, the present invention can be applied to a remote monitoring and control device that acquires monitoring information at regular intervals, a programmable controller or an automatic control device that switches control contents and processing contents of devices based on time data.

The digital relay basic composition and CPU board example which show Embodiment 1 of this invention. 5 is a flowchart of a time data acquisition method according to the first embodiment. The flowchart of the example of the conventional RTC access. The flowchart of the time data acquisition method in Embodiment 2 of this invention. The connection structural example of an I2C bus.

Explanation of symbols

10 arithmetic unit 11 CPU
11A Internal timer 12 Flash ROM
13 Internal memory (RAM)
14 Nonvolatile memory 15 RTC (clock IC device)
16 Other devices

Claims (2)

The I2C bus is directly controlled by software processing of the CPU mounted on the digital processing apparatus main body, data is input / output to / from the device connected to the I2C bus, and the clock device that is one of the devices passes through the I2C bus. In a digital processing apparatus that performs digital processing based on time data acquired in
The CPU
Acquiring time data from the timepiece device via the I2C bus at the time of activation of the digital processing device;
Storing the time data acquired in the process in an internal memory of the digital processing device;
A process of incrementing time data stored in the internal memory for a time corresponding to the period each time an interrupt of a certain period from the built-in timer,
Reading the time data stored in the internal memory when the time data is needed;
A time data acquisition method in a digital processor characterized by comprising: The I2C bus is directly controlled by software processing of the CPU mounted on the digital processing apparatus main body, data is input / output to / from the device connected to the I2C bus, and the clock device that is one of the devices passes through the I2C bus. In a digital processing apparatus that performs digital processing based on time data acquired in
The CPU
Acquiring time data from the timepiece device via the I2C bus at the time of activation of the digital processing device;
Storing the time data acquired in the process in an internal memory of the digital processing device;
A process of incrementing time data stored in the internal memory for a time corresponding to the period each time an interrupt of a certain period from the built-in timer,
Reading the time data stored in the internal memory when the time data is needed;
Obtaining time data from the clock device via the I2C bus at regular time intervals or at a specified time, and rewriting the time data stored in the internal memory with the time data;
A time data acquisition method in a digital processor characterized by comprising:

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