JP2006140300A - Semiconductor device, wafer and method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a multilayer wiring structure, a wafer, and a method for manufacturing the semiconductor device by forming an overlay accuracy measurement mark capable of measuring a pattern overlay state with high accuracy.
A semiconductor layer, a first wiring layer provided on the semiconductor layer, an interlayer insulating film provided on the first wiring layer, and a first wiring layer provided on the interlayer insulating film. A mark is formed in the mark formation region of the second wiring layer, and the mark formation region of the first wiring layer is not substantially affected when the mark is recognized. Provided is a semiconductor device characterized in that a plurality of dummy patterns having a size are provided.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device, a wafer, and a method for manufacturing the semiconductor device, and more particularly, a semiconductor device, a wafer, and a semiconductor device manufactured using a mask having a multilayer wiring structure and the like and provided with an alignment mark pattern. Regarding the method.

  In order to manufacture a semiconductor device, a magnetic element, an optical integrated circuit, a SAW (surface acoustic wave) device, etc., it is necessary to superimpose a multilayer circuit pattern on a substrate with high accuracy. When aligning and transferring a mask pattern to a pattern already formed on the substrate, the position of the alignment mark formed on the substrate is first detected, and the mask pattern is transferred from this detection result. The position is determined and overlay exposure is executed.

  In this case, as a method for detecting the alignment mark position, the alignment mark on the substrate is detected using laser light, white light, etc., and the mark edge position is detected from the obtained detection signal to obtain the alignment position, There is a method of obtaining an alignment mark position by comparing a two-dimensional detection image of a mark pattern with a reference mark stored in advance in a detection system.

  Thereafter, in order to inspect whether the resist pattern formed by exposure is accurately overlaid on the lower circuit pattern, the position of the overlay accuracy measurement mark is measured by the overlay accuracy measuring device. The overlay accuracy is measured by using the overlay accuracy measurement mark formed on the lower substrate as the main measure, and using the resist pattern mark formed by exposure as the sub measure. Obtained as a coordinate difference between positions. Since this measurement is normally performed by image recognition, if another pattern exists below the overlay accuracy measurement mark, the overlay accuracy measurement apparatus may misrecognize the other pattern as an overlay accuracy measurement mark. is there. In order to avoid this, a proposal has been disclosed in which the overlay accuracy measurement mark is formed in an “other pattern prohibited area” in which a pattern other than the mark is not disposed, and no other pattern is disposed in the lower layer.

  In the present specification, the “overlay accuracy measurement mark” includes an alignment mark.

  However, in a semiconductor device having a multilayer wiring structure, if there is a wide area where no wiring layer exists at all because it is an “other pattern prohibited area”, the following problem occurs. That is, when an interlayer insulating film is deposited on the wiring layer and then planarized by CMP (Chemical Mechanical Polishing), the interlayer insulating film on the region where the wiring layer does not exist is located on the region where the wiring layer exists. "Dishing" occurs, which is thinner than the interlayer film. In the charged particle beam projection exposure method, the intensity of energy applied to the resist during exposure changes depending on the area ratio of the pattern, so that the line width of the pattern changes depending on the density of surrounding patterns.

  To solve this problem, a method has been proposed in which a plurality of rectangular parallelepiped dummy patterns are regularly arranged below the overlay accuracy measurement mark (Patent Document 1). In this structure, the flatness of the interlayer insulating film can be maintained, and the overlay accuracy can be measured visually by using a location where the overlay accuracy measurement mark does not overlap the underlying dummy pattern. However, high accuracy cannot be obtained by visual measurement, and automatic measurement by an overlay accuracy apparatus is indispensable.

On the other hand, the metal wiring layer below the metal wiring layer constituting the alignment deviation measurement mark is regularly arranged below the outer peripheral area of the “other pattern prohibited area” (the area between the circuit area and the other pattern prohibited area). Has been proposed (Patent Document 2). In the case of this structure, there is no metal layer under the alignment misalignment measurement mark metal layer. However, due to the existence of the “other pattern prohibited area”, countermeasures against dishing are insufficient, and a change in the pattern line width due to the area ratio cannot be prevented.
JP-A-5-094933 JP 2001-176780 A

  The present invention has been made on the basis of recognition of such a problem, and an object of the present invention is to provide a semiconductor having a multilayer wiring structure by forming an overlay accuracy measurement mark capable of measuring a pattern overlay state with high accuracy. An object of the present invention is to provide a method for manufacturing an apparatus, a wafer, and a semiconductor device.

In order to achieve the above object, according to one aspect of the present invention,
A semiconductor layer;
A first wiring layer provided on the semiconductor layer;
An interlayer insulating film provided on the first wiring layer;
A second wiring layer provided on the interlayer insulating film;
With
A mark is provided in the mark formation region of the second wiring layer,
A semiconductor device is provided in which a plurality of dummy patterns having a size that does not substantially affect recognition of the mark is provided in the mark formation region of the first wiring layer.

Here, the dummy pattern may be smaller than the resolution in the step of recognizing the mark.
Further, the size of the dummy pattern may be not more than half of the peak wavelength of detection light used in the step of recognizing the mark.

The mark may be used for overlay measurement for measuring overlay accuracy of a plurality of layers.
The mark may be used for alignment measurement for adjusting the alignment between the mask and the wafer in the exposure apparatus.

The plurality of dummy patterns may be irregular in at least one of their size, shape and arrangement.
The size of each of the plurality of dummy patterns may be not less than 100 nanometers and not more than 250 nanometers.
The area ratio occupied by the plurality of dummy patterns in the mark formation region may be substantially the same as the area ratio occupied by the wiring provided in the first wiring layer in a portion other than the mark formation region.

On the other hand, according to another aspect of the present invention,
A semiconductor layer;
A first wiring layer provided on the semiconductor layer;
An interlayer insulating film provided on the first wiring layer;
A second wiring layer provided on the interlayer insulating film;
With
A mark is provided in the mark formation region of the second wiring layer,
A wafer is provided in which a plurality of dummy patterns having a size that does not substantially affect the recognition of the mark is provided in the mark formation region of the first wiring layer.

  Here, the mark formation region may be provided on a scribe line.

According to yet another aspect of the present invention,
A semiconductor layer; a first wiring layer provided on the semiconductor layer; an interlayer insulating film provided on the first wiring layer; a second wiring layer provided on the interlayer insulating film; A method for manufacturing a semiconductor device comprising:
Forming a plurality of dummy patterns having a size that does not substantially affect the recognition of the postscript mark in the mark formation region of the first wiring layer;
Forming a mark in the mark formation region of the second wiring layer;
There is provided a method for manufacturing a semiconductor device, wherein the overlay accuracy between the second layer and the other layers is measured by recognizing the mark.

According to yet another aspect of the present invention,
A semiconductor layer; a first wiring layer provided on the semiconductor layer; an interlayer insulating film provided on the first wiring layer; a second wiring layer provided on the interlayer insulating film; A method for manufacturing a semiconductor device comprising:
Forming a plurality of dummy patterns having a size that does not substantially affect the recognition of the marks described later in the mark formation region of the first wiring layer;
Forming a mark in the mark formation region of the second wiring layer;
There is provided a method of manufacturing a semiconductor device, wherein exposure is performed by recognizing the mark to adjust an alignment between the second wiring layer and the mask.

  According to the present invention, the pattern area ratio of the substrate can be made constant. As a result, planarization can be performed with higher accuracy in the CMP process, and line width control can be performed with higher accuracy in the charged particle beam exposure process, which has a great industrial advantage.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic plan view showing an overlay accuracy measurement mark according to an embodiment of the present invention.
2 is a cross-sectional view taken along line BB in FIG.
These drawings represent a portion of the overlay accuracy measurement mark formed on the wafer in the process of manufacturing the semiconductor device.

  FIG. 2 shows a multilayer wiring structure provided on the semiconductor layer. As shown in the figure, a first interlayer insulating film 41 is provided on the interlayer insulating film 40. The first interlayer insulating film 41 is selectively provided with a first wiring layer 50 having a multilayer wiring structure. Similarly, a second wiring layer 52 having a multilayer wiring structure is selectively provided in the second interlayer insulating film 42. In the third interlayer insulating film 43, a third wiring layer having a multilayer wiring structure is selectively provided by a process performed thereafter. The fourth layer 44 is a photosensitive film (photoresist) layer for forming a wiring in the third interlayer insulating film 43. Etching of the third interlayer insulating film 43 is performed using the patterned resist 44 as a mask, and thereafter, a wiring material is embedded to complete a multilayer wiring structure.

  The actual circuit pattern is arranged over almost the entire surface of the wafer, but the lower metal wiring layer 50 is formed on the first interlayer insulating film 41, the upper metal wiring layer 52 is formed on the second interlayer insulating film 42, and the circuit pattern region. This is shown as an example of a structure that is selectively arranged in the structure.

  In the mark formation region 20, a main scale pattern 30 for overlay accuracy measurement marks is provided on the second interlayer insulating film 42. The fourth layer 44 is provided with a vernier pattern 32 (photoresist) of the overlay accuracy measurement mark. In other words, conventionally, this area 20 is set as an “other pattern prohibited area”. For this reason, conventionally, no pattern is arranged in the mark formation region 20.

  On the other hand, in the present embodiment, a plurality of dummy patterns 12 are provided in the mark formation region 20. The dummy patterns 12 are provided below the main scale pattern 30 provided in the second interlayer insulating film 42. The sizes of the dummy patterns 12 are made smaller than the image processing resolution of the overlay accuracy apparatus that recognizes the overlay accuracy measurement mark and measures the overlay accuracy. Further, at least one of the size, shape and arrangement of the dummy patterns 12 is irregularly formed.

  By doing so, these dummy patterns 12 are not recognized by the overlay accuracy measuring apparatus. The reason why any one of the size, shape, and arrangement is irregular is to prevent the dummy pattern 12 from deteriorating measurement accuracy such as moire during overlay accuracy measurement. In this way, overlay accuracy measurement can be performed with high accuracy without being affected by the dummy pattern 12. In addition, by arranging the dummy pattern 12 in the mark formation region 20, the pattern area ratio can be made equal to other regions. That is, the pattern area ratio in the wafer can be made constant. As a result, “dishing” in CMP can be reduced, and a change in line width due to the proximity effect during electron beam exposure can also be reduced.

3 to 5 are schematic diagrams illustrating specific examples of the present embodiment.
3 is a schematic plan view of a mark formation region in the present embodiment, FIG. 4 is a cross-sectional view thereof, and FIG. 5 is a schematic plan view of a layer provided with a dummy pattern.

  Also in this specific example, the size of the dummy pattern 12 is formed below the detection limit of the overlay accuracy measuring apparatus. In this way, these dummy patterns 12 are not recognized by the overlay accuracy measuring apparatus. In this specific example, the size and arrangement of the dummy patterns 12 are irregularly formed. In this way, phenomena such as moire can be prevented during overlay accuracy measurement.

  As a result of the overlay accuracy measurement, if the alignment deviation is large enough to cause circuit malfunction, the resist pattern is removed and the resist is applied again. After that, the position is corrected based on the result of the previous overlay accuracy measurement, and patterning is performed again by exposure.

  Here, the mark formation region 20 means a region where wiring patterns other than the overlay accuracy measurement mark and the alignment mark are not substantially formed. Therefore, it is desirable to provide the mark formation region 20 between, for example, the circuit region on the semiconductor substrate, the edge of the semiconductor substrate, or on the dicing line. In addition, since it is usually necessary to recognize the mark formation region 20 by an overlay accuracy measuring device, it is desirable to provide an interval so as not to misrecognize a wiring pattern arranged in the vicinity thereof. Specifically, the interval between the mark formation region 20 and the wiring pattern provided around the mark formation region 20 is preferably about 5 micrometers or more.

  In addition, the area ratio of the dummy pattern 12 in the mark formation region 20 and the minimum distance between the dummy patterns may be determined according to the circuit patterns 50 and 52 provided in the interlayer insulating films 41 and 42 and the manufacturing process. The size of the mark formation region 20 can be, for example, about 5 μm × 5 μm to 100 μm × 100 μm. The shape of the mark formation region 20 is not limited to a square, and may be a circle or a rectangle.

Next, the size of the dummy pattern 12 will be described in more detail.
In overlay accuracy measurement and alignment in an exposure apparatus, visible light having a wavelength band of 500 to 800 nanometers is usually used. The reason for this is that light having a shorter wavelength may sensitize the photosensitive film (photoresist) on the semiconductor substrate, and light having a longer wavelength (for example, infrared light) may be affected by heat. Because. Considering the use of light in this wavelength band, if the size of the dummy pattern is 250 nanometers or less, the resolution is less than the image processing resolution. In other words, the minimum wavelength of this wavelength band is 500 nanometers, and if it is less than or equal to one half, recognition by a normally used optical system becomes difficult. As a result, the dummy pattern 12 does not adversely affect overlay accuracy measurement and alignment in the exposure apparatus.
The minimum size of the dummy pattern 12 may be determined according to the process limit when forming the dummy pattern, and it is appropriate to set it to about 100 nanometers. The irregularity of the shape of the dummy pattern 12 can also be realized, for example, by irregularly changing the vertical and horizontal lengths within this size range.

  In the specific examples shown in FIGS. 3 to 5, the regular dummy pattern 10 is arranged in the region 60 between the mark formation region 20 and the circuit pattern region 62. These dummy patterns 10 are useful for making the pattern area ratio constant in a region 60 provided between the mark formation region 20 and the circuit pattern region 62. That is, in the region 60, the pattern area ratio can be easily made constant over the entire wafer surface by the substantially regular dummy pattern 10 provided in the first interlayer insulating film 41. As a result, the dishing countermeasure can be made more complete, and the line width accuracy can be improved by reducing the proximity effect.

Next, a method for determining the pattern of the random dummy pattern 12 provided in the mark formation region 20 will be described.
FIG. 6 is a flowchart showing a process of generating dummy pattern data.

First, parameters for determining a dummy pattern are determined (step S11).
Specifically, the parameters of the dummy pattern 12 include (1) the area ratio of the dummy patterns, (2) the shortest distance between the dummy patterns, (3) the distance from the boundary of the so-called “other pattern prohibited area”, (4 There is an allowable range of the size of the dummy pattern, and (5) the shape type of the dummy pattern.

  Next, the size of the dummy pattern is randomly determined according to the random number (step S12). That is, the upper and lower limits of the size of the dummy pattern are set, and the size of each pattern is determined within the variable range according to the generated random number. The upper limit of the size of the dummy pattern 12 is desirably set smaller than the resolution of image processing of the overlay accuracy apparatus.

  Subsequently, the shape of the dummy pattern is randomly determined according to the random number (step S13). That is, a parameter for determining the shape of the dummy pattern and its variable range are set, and the shape of each pattern in the variable range is determined according to the generated random number.

  Subsequently, the location of the generated dummy pattern is determined according to a random number (step S14). That is, the range in which the dummy pattern is arranged is set, and the position of each pattern is determined within the variable range according to the generated random number.

  Then, it is checked whether there is a parameter violation in the determined dummy pattern (step S15). If there are no parameter violations, the pattern is complete. If there is a parameter violation, the process returns to step S11 and starts again. Depending on the degree of violation, the procedure may return to any one of steps S12 to S14 and start again according to the procedure indicated by the broken line.

  In the present embodiment, it is not always necessary to execute all of steps S12 to S14. That is, as described above, if the size of the dummy pattern 12 is made smaller than the resolution of the image processing of the overlay accuracy apparatus and no moire or the like occurs in the overlay accuracy measurement, the steps S12 to S14 are performed. At least one of them can be omitted. For example, the size of the dummy pattern 12 may be smaller and constant than the image processing resolution of the overlay accuracy apparatus, the shape may be constant, and only the arrangement may be irregular.

  Further, the present invention is not applicable only to the mark formation region where the overlay accuracy measurement mark is provided. For example, the dummy pattern 12 is similarly provided in the mark formation region where the alignment mark for exposure is provided. The same effect can be obtained. That is, in the alignment deviation measurement, the influence of other patterns can be eliminated, high-precision deviation measurement can be performed, and a highly integrated semiconductor device with a high degree of integration can be realized by correcting the positional deviation.

  Similarly, by providing the dummy pattern 12 in the mark forming region where the alignment mark is provided, the pattern area ratio can be made constant. As a result, dishing in the CMP process can be prevented, and planarization can be performed with higher accuracy. That is, it is possible to reduce a focus shift at the time of exposure in photolithography, prevent formation failure of a metal wiring layer pattern of a circuit, and provide a highly reliable semiconductor device. Furthermore, by reducing the proximity effect in the charged particle beam exposure, the line width accuracy can be improved, and a high-performance semiconductor device can be provided.

The embodiments of the present invention have been described with reference to specific examples. However, the present invention is not limited to these specific examples.
That is, the gist of the present invention can be obtained even if those skilled in the art add design changes to each step constituting the semiconductor device, the wafer, and the semiconductor device manufacturing method of the present invention, and the apparatus, mask, wafer, etc. used therefor. Anything provided is included within the scope of the present invention.

It is a model top view showing the mark formation area of the mark for superimposition accuracy measurement concerning an embodiment of the invention. FIG. 2 is a schematic cross-sectional view of a mark formation region illustrated in FIG. 1. It is a schematic plan view showing the mark formation area concerning the specific example of this embodiment. FIG. 4 is a cross-sectional view of a mark formation region 20 illustrated in FIG. 3. FIG. 4 is a schematic plan view of a layer provided with a dummy pattern in a mark formation region illustrated in FIG. 3. It is a flowchart which determines a dummy pattern.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Dummy pattern 12 Dummy pattern provided in the lower part of other pattern prohibition area 20 Other pattern prohibition area 30 Overlay accuracy measurement mark main scale 32 Overlay accuracy measurement mark minor scale 40 Interlayer insulation film 41 First interlayer insulation film 42 Second Interlayer insulating film 43 Third interlayer insulating film 44 Fourth layer (photoresist)
50 Lower metal wiring layer 52 Upper metal wiring layer 60 Intermediate area between other pattern prohibited area and circuit pattern area 62 Circuit pattern area

Claims (9)

A semiconductor layer;
A first wiring layer provided on the semiconductor layer;
An interlayer insulating film provided on the first wiring layer;
A second wiring layer provided on the interlayer insulating film;
With
A mark is provided in the mark formation region of the second wiring layer,
The semiconductor device according to claim 1, wherein a plurality of dummy patterns having a size that does not substantially affect the recognition of the mark are provided in the mark formation region of the first wiring layer.   2. The semiconductor device according to claim 1, wherein the mark is used for overlay measurement for measuring overlay accuracy of a plurality of layers.   3. The semiconductor device according to claim 1, wherein the mark is used for alignment measurement for adjusting alignment between a mask and a wafer in an exposure apparatus.   4. The semiconductor device according to claim 1, wherein each of the plurality of dummy patterns has a size of 100 nanometers or more and 250 nanometers or less.   The area ratio occupied by the plurality of dummy patterns in the mark formation region is substantially the same as the area ratio occupied by the wiring provided in the first wiring layer in a portion other than the mark formation region. Item 5. The semiconductor device according to any one of Items 1 to 4. A semiconductor layer;
A first wiring layer provided on the semiconductor layer;
An interlayer insulating film provided on the first wiring layer;
A second wiring layer provided on the interlayer insulating film;
With
A mark is provided in the mark formation region of the second wiring layer,
The wafer, wherein the mark formation region of the first wiring layer is provided with a plurality of dummy patterns having a size that does not substantially affect the recognition of the mark.   The wafer according to claim 6, wherein the mark formation region is provided on a scribe line. A semiconductor layer; a first wiring layer provided on the semiconductor layer; an interlayer insulating film provided on the first wiring layer; a second wiring layer provided on the interlayer insulating film; A method for manufacturing a semiconductor device comprising:
Forming a plurality of dummy patterns having a size that does not substantially affect the recognition of the marks described later in the mark formation region of the first wiring layer;
Forming a mark in the mark formation region of the second wiring layer;
A method of manufacturing a semiconductor device, wherein the overlay accuracy between the second layer and the other layers is measured by recognizing the mark. A semiconductor layer; a first wiring layer provided on the semiconductor layer; an interlayer insulating film provided on the first wiring layer; a second wiring layer provided on the interlayer insulating film; A method for manufacturing a semiconductor device comprising:
Forming a plurality of dummy patterns having a size that does not substantially affect the recognition of the marks described later in the mark formation region of the first wiring layer;
Forming a mark in the mark formation region of the second wiring layer;
A method of manufacturing a semiconductor device, wherein exposure is performed by recognizing the mark and adjusting an alignment between the second wiring layer and a mask.

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