JP2006038670A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device installed with a self test function accessible to all memory regions of non-volatile memory during burn-in by providing freedom in combination of semiconductor integrated circuit loaded on the semiconductor device. <P>SOLUTION: A BIST chip 7 recognizes the kind of CPU chip 1 and the memory size and the like of a memory chip 3 based on identifiers obtained from an ID chip 5 and provides a processing means with these information. As any combinations of the CPU chip 1 and the memory chip 3 are responded, freedom can be provided in combination of the semiconductor integrated circuit loaded on the semiconductor device. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device in which a plurality of semiconductor integrated circuits are mounted in one package, and more particularly to a semiconductor device having a built-in self test function such as burn-in as an acceleration test.

  In the field of semiconductor devices, in recent years, SIP (System In Package) in which a plurality of semiconductor integrated circuits (die chips) are mounted and sealed in one package is used. In such SIP, as an accelerated test (a test performed under conditions stricter than the standard conditions for the purpose of shortening the test time), for example, as in Patent Document 1, a burn-in (electrical bias) was applied. In the state, for example, a test for operating at a high temperature of about 100 to 150 ° C. may be executed. Some SIPs have a built-in BIST (Built in Self-test) circuit for executing burn-in.

  In such a semiconductor device, when performing a burn-in, a predetermined burn-in program stored in advance in a nonvolatile memory is read out, and this burn-in program is executed by a central processing unit (hereinafter referred to as “CPU”), whereby a self-test of the semiconductor device is performed. Execute.

JP 11-271199 A

  By the way, there are several different types of semiconductor devices, and each type of semiconductor device includes a plurality of different types of CPUs and a combination of non-volatile memories with different memory sizes and data read / write methods. Sometimes.

  Here, the conventional burn-in program must be designed depending on the instruction set of the CPU built in the semiconductor device, the memory size of the nonvolatile memory, the data read / write method, and the like. It was designed differently depending on the type. Since it is impossible to apply a non-corresponding burn-in program to each semiconductor device, the burn-in program is individually applied to each semiconductor device in which the CPU and the nonvolatile memory are selectively combined. It was necessary to prepare for one-to-one correspondence.

  Therefore, in the SIP in which the CPU and the non-volatile memory are manufactured as separate chips, (1) when a program is mounted on the CPU side, the memory size of the non-volatile memory combined with the CPU, the data read / write method, etc. are unknown. (2) When the program is installed on the nonvolatile memory side, there are two problems such as the CPU being limited by the difference in the instruction set, and there is a problem with the semiconductor integrated circuit (CPU and nonvolatile memory) in the semiconductor device. There was a limit to the degree of freedom of combination, and this was a factor that hindered free design.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device with a built-in self-test function that allows a combination of semiconductor integrated circuits mounted on a semiconductor device to have a degree of freedom and can access all memory areas of a nonvolatile memory at the time of burn-in. There is.

  In order to solve the above-described problems, the present invention provides a semiconductor device having a self-test function in which a plurality of semiconductor integrated circuits are mounted in one package, and includes a processing means for executing the self-test. An integrated circuit, another semiconductor integrated circuit having a circuit to be subjected to the self-test, an identification unit having an identifier, and the identifier is read from the identification unit, and the processing unit performs a self-test according to the identifier And at least necessary processing means or necessary information input means for transmitting information on the circuit to be subjected to the self-test to the processing means.

  According to this semiconductor device, on the basis of the identifier obtained from the identification means, the necessary information input means can select the type of processing means mounted on the semiconductor device and information on a circuit to be subjected to self-test (for example, a memory circuit). The memory size) and provide this information to the processing means, such as accessing the entire storage area of the memory circuit during the self-test for various combinations of the processing means and the circuit to be tested. It is convenient to perform self-tests without any problems while performing appropriate processing.

  In addition, by simply incorporating the identification means and necessary information input means in each semiconductor device, various combinations of self-tests can be performed on the processing means and the circuit to be self-tested. It can be carried out.

  Furthermore, there is an advantage that the program used in the processing means can be unified.

{First embodiment}
<Configuration>
FIG. 1 is a block diagram showing a semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, this semiconductor device is a SIP (System In Package) in which a plurality of semiconductor integrated circuits (die chips) are mounted and sealed in one package, and has a built-in burn-in function as an acceleration test. It is a thing. This semiconductor device includes a conventional CPU chip (processing means) 1, a memory chip (storage circuit) 3 that is a nonvolatile memory, and an ID as an identifiable identification means having an identifier (ID information). A chip 5 and necessary information input means (hereinafter referred to as “BIST chip”) 7 for transmitting information necessary for determining an operation such as burn-in by reading the identifier to the CPU chip 1 are provided.

  The CPU chip 1 is configured to have a specific instruction set depending on its type, and is a functional element that operates according to a program corresponding to the instruction set. In particular, in the stage before the shipment of the semiconductor device, the BIST described later is used. When the memory size of the memory chip 3 and the data read / write method are given from the chip 7, the BIST is executed for the memory chip 3 in accordance with the burn-in processing procedure defined by the pre-stored burn-in program according to the information. The semiconductor device has a function of executing a self-test by burn-in of the semiconductor device according to the memory size obtained from the chip 7 and the data read / write method. In other words, the burn-in program is set in the CPU chip 1 so as to be able to cope with all combinations expected in advance as combinations of the CPU chip 1 and the memory chip 3, and the instruction sets of a plurality of types of CPU chips 1 are set. And a memory chip 3 having various memory sizes and data read / write methods.

  The memory chip 3 is a rewritable nonvolatile memory such as a flash ROM, for example, has a storage capacity of a memory size determined according to the type, and is set to a data read / write method according to the type. Configured.

  Conventionally, a burn-in program is stored in advance in the nonvolatile memory itself to be burned in, and the CPU reads the burn-in program and executes a self-test by burn-in. In the embodiment, since the burn-in program is stored in the CPU chip 1 in advance, it is not necessary to store the burn-in program in the memory chip 3.

  The ID chip 5 stores in advance an identifier (ID information) for identifying the combination of the type of the CPU chip 1 incorporated in the semiconductor device, the memory size of the memory chip 3, the data read / write method, and the like. Yes. As the ID chip 5, for example, a nonvolatile memory provided separately from the memory chip 3 is used.

  The BIST chip 7 is a logic function element having a built-in logic circuit (not shown). The BIST chip 7 reads a plurality of identifiers held by various ID chips 5, and based on these identifiers, the memory size of the memory chip 3 is read. Then, the data read / write method and the like are recognized, and information such as the recognized memory size and the data read / write method is output to the CPU chip 1.

<Operation>
The operation of the semiconductor device having the above configuration will be described with reference to FIG. In the stage before the shipment of the semiconductor device or the like, first, in step S01 in FIG. 2, when the BIST chip 7 of this semiconductor device is activated and the internal logic circuit operates, in step S02, the BIST chip 7 is an ID chip. 5 is read out.

  At this time, the ID chip 5 outputs an identifier (ID information) stored therein in advance to the BIST chip 7 (step S03).

  In step S04, the BIST chip 7 recognizes the memory size (for example, 512 KB or 768 KB) of the memory chip 3 and the data read / write method based on the identifier (ID information) read from the ID chip 5. Then, information such as the memory size and the data read / write method is output to the CPU chip 1.

  Then, in step S05, the CPU chip 1 accesses the memory chip 3 in accordance with the memory size of the memory chip 3 and the data read / write method, etc., according to the burn-in processing procedure defined by the burn-in program held in advance. Then, a self test by burn-in of the semiconductor device is executed.

  Incidentally, for example, as shown in FIG. 3, when there are several different types of semiconductor devices 101a to 101c, each of the semiconductor devices 101a to 101c has a plurality of different types of CPU chips 103a and 103b and a memory size. In addition, it is configured as a SIP in which different memory chips 105a and 105b such as data read / write methods are combined. In the example of FIG. 3, a first CPU chip (CPU-A) 103a and a first memory chip (MEMORY-A) 105a are mounted on the first semiconductor device 101a, and the first semiconductor device 101b has a first CPU chip (CPU-A) 103a mounted thereon. CPU chip (CPU-A) 103a and second memory chip (MEMORY-B) 105b are mounted, and the second CPU chip (CPU-B) 103b and second memory chip ( MEMORY-B) 105b is mounted.

  Since the conventional burn-in programs 107a to 107c are defined depending on the instruction set of the CPU chips 103a and 103b, the memory size of the memory chips 105a and 105b, the data read / write method, etc., the CPU chips 103a and 103b and the memory In the SIP in which the chips 105a and 105b are manufactured as separate chips, they are designed differently depending on the type of CPU chip built in the semiconductor devices 101a to 101c, the memory size of the memory chips 105a and 105b, the data read / write method, and the like. As shown in FIG. 3, different burn-in programs 107a to 107a are used for each type of individual semiconductor devices 101a to 101c in which the CPU chips 103a and 103b and the memory chips 105a and 105b are selectively combined. c had been made in a one-to-one correspondence. That is, conventionally, the first program 107a is only in the first semiconductor device 101a, the second program 107b is in the second semiconductor device 101b, and the third program 107c is only in the third semiconductor device 101c. For example, it is impossible to execute the burn-in by applying the first program 107a to the second semiconductor device 101b.

  Therefore, conventionally, when a burn-in program is mounted on the CPU chips 103a and 103b, when the memory chips 105a and 105b are assembled to the burn-in program, the memory size of the memory chips 105a and 105b, the data read / write method, etc. are unknown. If a burn-in program is mounted on the memory chips 105a and 105b, when the CPU chips 103a and 103b are assembled on the memory chips 105a and 105b, what kind of CPU chips 103a and 103b are assembled. Since the instruction set of the CPU chips 103a and 103b is unknown, there is a problem that the types of the CPU chips 103a and 103b are limited.

  On the other hand, according to this embodiment, based on the identifier (ID information) obtained from the ID chip 5, the BIST chip 7 is connected to the type of the CPU chip 1 mounted on the semiconductor device and the memory chip 3. Recognizing the memory size and its read / write method and providing such information to the CPU chip 1, various combinations of the CPU chip 1 and the memory chip 3 are accessed while accessing the entire memory area of the memory chip 3 during burn-in. It is convenient to perform self-tests without any problems.

  In addition, by incorporating the BIST chip 7 in each semiconductor device, it is possible to realize semiconductor devices with a built-in self-test function in various combinations with respect to the types of the CPU chips 103a and 103b and the memory sizes of the memory chips 105a and 105b. The semiconductor device can be freely designed.

  Further, there is an advantage that a single test program can be provided for each SIP.

  Furthermore, it is convenient because the BIST chip 7 can be designed by a process dedicated to logic.

  In this embodiment, the operation at the time of burn-in has been described. Of course, a memory test by any self-test other than the burn-in can be performed by the same method.

{Second Embodiment}
FIG. 4 is a block diagram showing a semiconductor device according to the second embodiment of the present invention. In FIG. 4, elements having the same functions as those in the first embodiment are denoted by the same reference numerals.

  In the first embodiment, as shown in FIG. 1, the BIST chip 7 is mounted as a die chip different from the CPU chip 1 and the memory chip 3, whereas the semiconductor device of this embodiment is shown in FIG. As described above, the BIST chip 7 and the CPU chip 1 are configured as one integrated circuit.

  Other configurations are the same as those in the first embodiment. In particular, based on an identifier (ID information) stored in the ID chip 5, the BIST chip 7 formed into one chip on the CPU chip 1 is the type of the CPU chip 1 mounted on the semiconductor device and the memory chip 3. This is the same as in the first embodiment in that the CPU size is recognized and the burn-in program is processed by the CPU chip 1 accordingly.

  Here, in the case where the BIST chip 7 and the CPU chip 1 are configured as one integrated circuit, if the memory size of the memory chip 3 and the data read / write method cannot be discriminated by the CPU chip 1, the self-e.g. In the test, it is difficult to execute the self test without any trouble while accessing the entire memory area of the memory chip 3.

  However, in this embodiment, the BIST chip 7 that is formed into one chip on the CPU chip 1 is mounted on the semiconductor device based on the identifier (ID information) stored in the ID chip 5. The CPU chip 1 recognizes the type of CPU chip 1 and the memory size of the memory chip 3 and the read / write method thereof, and the CPU chip 1 processes a burn-in program suitable for these, so the memory size of the memory chip 3 and the data read / write method, etc. Can be easily determined by the CPU chip 1. Therefore, the self test can be executed without any trouble while accessing the entire memory area of the memory chip 3 in the self test at the time of burn-in or the like.

  Further, since the BIST chip 7 is integrated with the CPU chip 1, it is convenient for handling when the die chip is incorporated into a semiconductor device.

{Third embodiment}
FIG. 5 is a block diagram showing a semiconductor device according to the third embodiment of the present invention. In FIG. 5, elements having the same functions as those in the first embodiment are denoted by the same reference numerals.

  In the first embodiment, the ID chip 5 is mounted as a die chip different from the memory chip 3 as shown in FIG. 1, whereas the semiconductor device of this embodiment has an ID chip as shown in FIG. The chip 5 and the memory chip 3 are configured as one integrated circuit.

  This configuration also has the same advantages as in the first embodiment.

  In FIG. 5, the BIST chip 7 is configured as a die chip different from the CPU chip 1. However, as in the second embodiment, the BIST chip 7 and the CPU chip 1 are formed as one integrated circuit (die chip). It may be configured.

{Fourth embodiment}
FIG. 6 is a view showing a semiconductor device according to the fourth embodiment of the present invention.

  As shown in FIG. 6, the semiconductor device according to this embodiment includes one CPU chip 1, a plurality of memory chips 3a and 3b, one BIST chip 7 connected to the CPU chip 1, and other peripheral circuits. Peripheral chip 9 and ID chips 5a to 5c associated with each of the memory chips 3a and 3b and the peripheral chip 9 on a one-to-one basis, and these are mounted in one package. .

  One ID chip 5a stores an identifier (ID information) corresponding to one memory chip 3a, the other ID chip 5b stores an identifier (ID information) corresponding to the other memory chip 3b, and the other The ID chip 5c stores an identifier (ID information) corresponding to the peripheral chip 9. The ID chip 5a and the memory chip 3a are configured as one integrated circuit 13a, the ID chip 5b and the memory chip 3b are also configured as one integrated circuit 13b, and the ID chip 5c and the peripheral chip 9 are also configured as one integrated circuit 13c. It is configured as.

  The CPU chip 1 and the integrated circuits 13a to 13c are connected to each other by a bus 11, and the parts 1, 13a to 13c are configured to be able to communicate with each other through the bus 11.

  In such a configuration, the BIST chip 7 first receives an identifier from the ID chip 5a of the integrated circuit 13a, this identifier is given to the CPU chip 1, and the CPU chip 1 recognizes the memory size of the memory chip 3a. Next, the BIST chip 7 receives an identifier from the ID chip 5b of the integrated circuit 13b, this identifier is given to the CPU chip 1, and the CPU chip 1 recognizes the memory size of the memory chip 3b. Further, the BIST chip 7 receives an identifier from the ID chip 5 c of the integrated circuit 13 c, and this identifier is given to the CPU chip 1 so that the CPU chip 1 recognizes the type of the peripheral chip 9.

  Then, the CPU chip 1 executes the burn-in by processing the burn-in program according to the memory size of the memory chips 3a and 3b recognized based on the information from the BIST chip 7, the type of the peripheral chip 9, and the like.

  In this way, the plurality of memory chips 3a and 3b and other peripheral chips 9 can be collectively self-tested by the operation of the CPU chip 1 by the same burn-in program, and the individual integrated circuits 13a. The self-test can be performed more efficiently than the case where the self-test is performed separately for .about.13c. In addition, various combinations such as the memory sizes of the memory chips 3a and 3b in the integrated circuits 13a to 13c and the types of the peripheral chips 9 can be handled based on information from the ID chips 5a to 5c. Is possible. In addition, since it is only necessary to provide the ID chips 5a to 5c in each of the mounted memory chips 3a and 3b and the peripheral chip 9, the number of memory chips 3a and 3b and peripheral chips 9 that can be tested simultaneously (the same number) is increased. It is possible. Therefore, various combinations of semiconductor devices with a built-in self-test function can be realized, and the semiconductor device can be freely designed.

1 is a block diagram showing a semiconductor device according to a first embodiment of the present invention. It is a figure showing processing operation of a semiconductor device concerning a 1st embodiment of the present invention. It is a figure which shows operation | movement of the comparative example for demonstrating the effect of the semiconductor device which concerns on 1st Embodiment of this invention. It is a block diagram which shows the semiconductor device which concerns on 2nd Embodiment of this invention. It is a block diagram which shows the semiconductor device which concerns on 3rd Embodiment of this invention. It is a block diagram which shows the semiconductor device which concerns on 4th Embodiment of this invention.

Explanation of symbols

1 CPU chip, 3 memory chip, 5, 5a to 5c ID chip, 7 BIST chip, 9 peripheral chip, 11 bus, 13a to 13c integrated circuit.

Claims (6)

A semiconductor device having a self-test function in which a plurality of semiconductor integrated circuits are mounted in one package,
A semiconductor integrated circuit having processing means for performing the self-test;
Another semiconductor integrated circuit having a circuit to be subjected to the self-test;
An identification means having an identifier;
The necessary information input for reading the identifier from the identification means and transmitting at least information relating to the processing means or the circuit to be subjected to the self test to the processing means necessary for the self test in the processing means in accordance with the identifier And a semiconductor device. The semiconductor device according to claim 1,
A semiconductor device, wherein the circuit to be subjected to the self-test is a memory circuit. The semiconductor device according to claim 2,
The information transmitted from the necessary information input means to the processing means includes the type of the processing means or the storage size of the storage circuit. The semiconductor device according to claim 1 or 3, wherein
A semiconductor device characterized in that the necessary information input means and the processing means are configured as one integrated circuit. The semiconductor device according to claim 1, wherein:
A semiconductor device characterized in that the identification means and the circuit to be subjected to the self-test are configured as one integrated circuit. A semiconductor device according to any one of claims 1 to 5,
A plurality of the other semiconductor integrated circuits are mounted,
A semiconductor device characterized in that a plurality of the identification means are mounted in association with each of the other semiconductor integrated circuits.

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