JP2006011630A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To cause a bus collision with data of the next cycle due to a product standard (data floating) of an external memory when memory access between a central processing unit (CPU) and an external memory is continuously performed. Avoid sex.
A data bus drive control device E is provided to control a data signal in a pseudo manner by pull-up and pull-down control in a data floating section during a write cycle, and when data input / output is switched, pull-up, Pull-down control and transistor control enable data line bus collision avoidance and faster memory access by shortening the bus cycle.
[Selection] Figure 2

Description

  The present invention relates to a microcomputer having a function of avoiding a bus collision between data of this cycle and data of the next cycle when memory access between the central processing unit (CPU) and the external memory constituting the microcomputer continues. Is.

  FIG. 13 schematically shows the main part of a conventional microcomputer. As shown in FIG. 13, the microcomputer 131 includes a central processing unit (hereinafter referred to as CPU) 132 and a memory access control device 133. Reference numeral 134 denotes an input / output control device that controls an interface with an external device, and 135 denotes an external memory. The CPU 132 and the memory access control device 133, the memory access control device 133 and the input / output control device 134, and the input / output control device 134 and the external memory 135 are respectively an address signal AD, a data signal DT, a chip select signal CS, and a read enable signal RE. Are connected via a write enable signal WE. FIG. 11 is a diagram showing a detailed configuration centering on the input / output control device 134. A is a P-type transistor, B is an N-type transistor, C is a switch-type pull-up element, and D is a switch-type pull-down element. is there. The operation of the conventional microcomputer configured as described above will be described below.

  In general, the memory access method from the CPU 132 to the external memory 135 includes a fixed wait mode in which memory access is terminated in a wait cycle set from the start of memory access, and an acknowledge signal from the external memory 135 to the CPU 132 by starting the memory access. There is a handshake mode in which memory access is terminated by returning.

  In the case of the fixed wait mode, when the CPU 132 retrieves data stored from the external memory 135, the chip select signal CS and the address value to be accessed are output to the address signal AD to the memory access control device 133 to output the external memory 135. Request access to. When the memory access control device 133 receives the chip select signal CS and the address signal AD of the address to be accessed, it passes them to the external memory 135. At this point, memory access to the external memory 135 is started. Then, the chip select signal CS is negated in the set wait cycle, and the memory access is completed.

Here, when the memory access between the CPU 132 and the external memory 135 continues, as shown in FIG. 12, the chip select signal CS remains asserted and at the same time the read enable signal RE is negated. Finish reading data. Then, after the data floating in the external memory 135, the write enable signal WE is asserted in the next cycle, and data writing to the external memory 135 is started. In the figure, t0 indicates the time when read access is completed (when the read enable signal RE is negated), and t1 indicates the time when write access is started (when the write enable signal WE is asserted).
JP 2000-250849 A

  The conventional microcomputer is configured as described above. When the memory access between the CPU 2 and the external memory 5 is continuously performed, the data is changed to the data of the next cycle according to the product standard (data floating) of the external memory 5. There is a possibility of bus collision, and if a high impedance section is provided in the data bus in order to avoid this, there is a problem that memory access is slowed down due to this influence.

  The present invention has been made to solve the above-described problems, and can avoid a data line bus collision between the CPU 2 and the external memory 5, and can realize high-speed memory access. An object is to provide a microcomputer.

  A microcomputer according to claim 1 of the present invention includes a central processing unit (CPU), a memory access control device, and an input / output control device, and performs data communication with an external memory via the input / output control device. In the microcomputer, the input / output control device performs pull-up and pull-down operations at timings different from the clock to control the input / output data, and allows the floating data to be accepted as input data even in the write cycle. It is characterized by having.

  A microcomputer according to a second aspect of the present invention includes a central processing unit (CPU), a memory access control device, and an input / output control device, and performs data communication with an external memory via the input / output control device. In the microcomputer to be executed, the input / output control device controls output data according to input data from the external memory, stops data output except for high impedance, and can accept floating data as input data even in a write cycle. It is characterized by having a signal control means.

  According to a third aspect of the present invention, in the microcomputer according to the first aspect, the signal control means includes a buffer circuit comprising a transistor for amplifying input / output data, and pulls up or pulls down the output of the buffer circuit. A data bus drive control device fixed by operation, and in the cycle of the data floating output of the external memory, the input / output data is controlled pseudo only by the pull-up / pull-down operation, and the pull-up / pull-down is controlled in the next cycle. Control is performed by both the operation and transistor elements, and only the transistor is controlled in the next cycle.

  According to a fourth aspect of the present invention, in the microcomputer according to the first aspect, the signal control means includes a buffer circuit comprising a transistor for amplifying input / output data, and pulls up or pulls down the output of the buffer circuit. A data bus drive control device that is fixed by operation, and a bus drive output control device that controls the data bus drive control device, wherein the bus drive output control device monitors input data and And controlling the data bus drive control device based on the pull-up and pull-down operations and controlling the transistors so that the control method is switched in each cycle.

  According to a fifth aspect of the present invention, in the microcomputer according to the third aspect, the data bus drive control device includes an internal register for setting a data floating period of the external memory, and the internal register The pull-up, pull-down operation, and output data control of the transistor are performed based on the value set in (1).

  According to a sixth aspect of the present invention, in the microcomputer according to the third aspect, the data bus drive control device includes a data floating period measuring means for measuring a data floating period of the external memory, and the external bus In a period other than the time of memory access, the data floating period of the external memory is measured by the first period data floating period measuring means, and the pull-up, pull-down operation and output data control by the transistor are performed based on the measured value. It is characterized by that.

  According to the microcomputer of the present invention, the data bus drive control device for fixing the output of the buffer circuit by pull-up or pull-down operation is provided in the input / output control device, and the external data signal is controlled in a pseudo manner. Even in the write cycle, floating data can be accepted as input data, and even if memory access between the CPU and external memory is performed continuously, a bus collision between this data and the next cycle data can be avoided. In addition, there is an effect that it is possible to realize an excellent microcomputer capable of increasing the memory access speed by shortening the bus cycle.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 shows a configuration diagram of a microcomputer according to Embodiment 1 of the present invention. In FIG. 1, the input / output control device 4 performs input / output control of signals from the CPU 2 and signals from the external memory 5 via the memory access control device 3.

  The CPU 2 and the memory access control device 3, the memory access control device 3 and the input / output control device 4, and the input / output control device 4 and the external memory 5 respectively have an address signal AD, a data signal DT, a chip select signal CS, and a read enable signal RE. Are connected via a write enable signal WE.

  FIG. 2 shows a detailed configuration of the input / output control device 4 of the microcomputer. In this figure, A is a P-type transistor, B is an N-type transistor, C is a switch-type pull-up element, D is a switch-type pull-down element, E is a data bus for controlling the switch-type pull-up element C and the switch-type pull-down element D It is a drive control device.

  FIG. 4 shows a timing chart of the microcomputer according to the first embodiment. In FIG. 4, t2 is the read access end time and write access start time, and t3 is the next cycle start time after floating data output. The operation of the microcomputer of the present embodiment configured as described above will be described below.

  The memory access method from the CPU 2 to the external memory 5 includes a fixed wait mode in which the memory access is terminated in a wait cycle set from the start of memory access, and an acknowledge signal is sent from the external memory 5 to the CPU 2 by starting the memory access. There is a handshake mode in which memory access is terminated by returning.

  In the case of the fixed wait mode, when the CPU 2 retrieves the stored data from the external memory 5, the chip select signal CS and the address value to be accessed are output to the address signal AD to the memory access control device 3 to the external memory 5. Request access. When the memory access control device 3 receives the chip select signal CS and the address signal AD of the address to be accessed, it passes them to the external memory 5. At this point, memory access to the external memory 5 is started. Then, the chip select signal CS is negated in the set wait cycle, and the memory access is completed.

  Here, when the memory access between the CPU 2 and the external memory 5 continues, as shown in FIG. 4, the chip select signal CS remains asserted, and the read enable signal RE is changed during the read cycle. At the same time as being negated, the read data is finished. At time t2, the write enable signal WE is immediately asserted to enter the write cycle, but the read data is floated for a certain period according to the product standard value (data floating time) of the external memory 5, so that FIG. 2, the switch-type pull-up element C in FIG. 2 is turned on when the write data is H (“1”) and turned off when the write data is L (“0”). The switch type pull-down element D is turned on when the write data is L (“0”) and turned off when the write data is H (“1”). Thus, when the read data is floating, both the switch-type pull-up element C and the switch-type pull-down element D are OFF, so that the floating data can be accepted as an input even during the write cycle, and a bus collision can be avoided.

  Further, immediately after the floating data output from the external memory 5 is completed, the write data is switched immediately, and the write data identified by the data bus drive control device in advance is transferred to the data path by the pull-up element C and the pull-down element D. (When the write data is H “1”, the pull-up element C is turned on and the pull-down element D is turned off. When the write data is L (“0”), the pull-up element C is turned off and the pull-down element D is turned on. ).

  Thus, the data signal can be controlled in a pseudo manner by pulling up and pulling down the transistors constituting the input / output control device 4 by the data bus drive control device E.

  Then, after the next cycle, that is, in the section T3 from time t3 in FIG. 4, the pseudo data control by pull-up and pull-down is returned to the normal transistor control. That is, when the write data is H, the P-type transistor A is turned ON, when the write data is L, the P-type transistor A is turned OFF, when the write data is L, the N-type transistor B is turned ON, and when the write data is H, the N-type transistor B is turned OFF. By turning off both the pull-up element C and the switch-type pull-down element D, the pseudo write to the data bus is completed.

  As described above, according to the microcomputer according to the first embodiment, the data bus drive control device E that operates at a timing different from the clock in the data floating section during the write cycle according to the content of the write data. Transistor pull-up / pull-down control allows floating data to be accepted as input data (read data) in the write cycle, and pull-up / pull-down control and transistor control are performed when switching data input / output. Since the input / output control unit 4 for controlling the data signal in a pseudo manner is provided, even when the memory access between the CPU 2 and the external memory 5 is continuously performed, the data currently being processed and the data of the next cycle Can avoid the bus collision, And, it is possible to achieve even faster memory access by shortening the bus cycle.

(Embodiment 2)
Next, a microcomputer according to a second embodiment of the present invention will be described. The basic configuration is the same as that of the microcomputer shown in FIG. FIG. 3 shows an input / output control apparatus for a microcomputer according to the second embodiment. 3, the same reference numerals as those in FIG. 11 denote the same or corresponding parts, and F denotes a control device for controlling output data.

  In addition, as a timing chart for explaining the operation of the microcomputer according to the second embodiment, reference is made to the timing chart shown in FIG. The operation of the microcomputer of the second embodiment configured as described above will be described below.

  The memory access method from the CPU 2 to the external memory 5 includes a fixed wait mode in which the memory access is terminated in a wait cycle set from the start of memory access, and an acknowledge signal is sent from the external memory 5 to the CPU 2 by starting the memory access. It has already been mentioned that there is a handshake mode that terminates memory access by returning it.

  Therefore, in the case of the fixed wait mode, when the CPU 2 retrieves the stored data from the external memory 5, it outputs the chip select signal CS and the address value to be accessed as the address signal AD to the memory access control device 3, Request access to the external memory 5. When the memory access control device 3 receives the chip select signal CS and the address signal AD of the address to be accessed, it passes them to the external memory 5. At this point, memory access to the external memory 5 is started. Then, the chip select signal CS is negated in the set wait cycle, and the memory access is completed.

  Here, when the memory access between the CPU 2 and the external memory 5 continues, as shown in FIG. 4, the chip select signal CS remains asserted, and the read enable signal RE is changed during the read cycle. At the same time as being negated, the read data is finished. At time t2, the write enable signal WE is immediately asserted to enter the write cycle, but the read data is floated for a certain period according to the product standard value (data floating time) of the external memory 5, so that FIG. In the period T1 from time t2, the output control device F is turned off if the read data is not high impedance, and the output control device F is turned on if the read data is high impedance.

  Thus, when the read data is floating, the output control device F is OFF, so that the floating data can be accepted as input data even during the write cycle. After the floating data is finished, the output control device F immediately switches to write data. After the next cycle, that is, in a T3 section from time t3 in FIG. 4, normal data output is performed.

  As described above, according to the microcomputer according to the second embodiment, during the write cycle, the data signal is controlled by the output control device F in the data floating period in the high impedance section of the data bus, and the contents of the read data are changed. Accordingly, if it is other than high impedance, the output is stopped as input data, and floating data can be accepted as input data (read data) even in the write cycle. Memory access between the CPU 2 and the external memory 5 Even in the case where data is continuously executed, a bus collision between the present data and the next cycle data can be avoided, and the speed of memory access can be increased by shortening the bus cycle.

(Embodiment 3)
Next, a microcomputer according to a third embodiment of the present invention will be described. Since the basic configuration is the same as that of the first embodiment, the description of the configuration is omitted here. FIG. 5 is a timing chart for explaining the operation of the microcomputer according to the third embodiment. In FIG. 5, time t4 is the start time of the next cycle of the next cycle start time after floating data output at time t3. Hereinafter, the operation of the microcomputer according to the third embodiment will be described.

  In the case of the fixed wait mode, when the CPU 2 retrieves the stored data from the external memory 5, the chip select signal CS and the address value to be accessed are output to the address signal AD to the memory access control device 3 to the external memory 5. Request access. When the memory access control device 3 receives the chip select signal CS and the address signal AD of the address to be accessed, it passes them to the external memory 5. At this point, memory access to the external memory 5 is started. Then, the chip select signal CS is negated in the set wait cycle, and the memory access is completed. Here, when memory access between the CPU 2 and the external memory 5 continues, the chip select signal CS remains asserted as shown in FIG. 5, and the read enable signal RE is negated during the read cycle. At the same time, the read data is taken. At the time t2, the write enable signal WE is immediately asserted to enter the write cycle, but the read data floats for a certain period according to the product standard value (data floating time) of the external memory 5, so that the data shown in FIG. In the T1 interval from time t2, when the write data is H, the switch type pull-up element C in FIG. 2 is turned ON, when the write data is L, the switch type pull-down element D is turned ON when the write data is L, and the write data is H Turn off sometimes. Thus, when the read data is floating, the switch-type pull-up element C and the switch-type pull-down element D are OFF, so that the floating data can be accepted as an input even during the write cycle. Also, immediately after the floating data is finished, it is switched to write data.

  In this way, the data signal is controlled in a pseudo manner by pull-up and pull-down control. In the next cycle, that is, the period T2 from time t3 to t4 in FIG. 5, since the pull-up and pull-down control is switched to the normal transistor control, a spike phenomenon may occur. At the same time, when the write data is H, the P-type transistor A is turned ON, when the write data is L, it is turned OFF, when the write data is L, the N-type transistor B is turned ON, and when the write data is H, it is turned OFF. Then, after the next cycle, that is, in the period T3 from time t4 in FIG. 5, the pseudo data control by pull-up and pull-down is returned to the normal transistor control. That is, when the write data is H, the P-type transistor A is turned on, when the write data is L, it is turned off, when the write data is L, the N-type transistor B is turned on, and when the write data is H, the N-type transistor B is turned off. By turning off both the up element C and the switch-type pull-down element D, the pseudo writing to the data bus is completed.

  As described above, according to the microcomputer according to the third embodiment, during the write cycle, the data bus drive control device E that operates at a timing different from the clock during the data floating period causes the transistor to be in accordance with the content of the write data. In the write cycle, floating data can be received as input data (read data) by performing pull-up / pull-down control, and even when memory access between the CPU 2 and the external memory 5 is continuously performed. Thus, a bus collision between the data currently being processed and the data of the next cycle can be avoided.

  Further, in the next cycle after the floating data is output, the occurrence of spike phenomenon can be prevented by performing pull-up, pull-down control, and transistor control at the time of data signal input / output switching.

(Embodiment 4)
Next, a microcomputer according to a fourth embodiment of the present invention will be described. FIG. 6 shows a configuration of a microcomputer having an input / output control device, a data bus drive control device, and a bus drive output control device in the fourth embodiment. In this figure, the same reference numerals as in FIGS. 1 to 3 denote the same parts, and G denotes a bus drive output control device. FIG. 7 is a timing chart for explaining the operation of the microcomputer having the input / output control apparatus according to the fourth embodiment. In FIG. 7, time t5 is the read access end time and write access start time, time t6 is the floating data output time, and time t7 is the next cycle start time after the floating data output in the external memory. The operation of the microcomputer according to this embodiment configured as described above will be described below.

  In the fixed wait mode, when the CPU 2 takes out the stored data from the external memory 5, the chip select signal CS and the address value to be accessed are output as the address signal AD to the memory access control device 3, and the external memory 5 Request access to. When the memory access control device 3 receives the chip select signal CS and the address signal AD of the address to be accessed, it passes them to the external memory 5. At this point, memory access to the external memory 5 is started. Then, the chip select signal CS is negated in the set wait cycle, and the memory access is completed. Here, when the memory access between the CPU 2 and the external memory 5 continues, as shown in FIG. 7, the chip select signal CS remains asserted, and the read enable signal RE is changed during the read cycle. At the same time as being negated, the read data is finished. At time t5, the write enable signal WE is immediately asserted to enter the write cycle, but the read data is floated for a certain period according to the product standard value (data floating time) of the external memory 5.

  Therefore, in the section T4 from time t5 to time t6 in FIG. 7, that is, when the read data is other than high impedance (when the read data is floating), the enable signal of the data bus drive control device from the bus drive output control device G And the floating data is accepted as an input even during the write cycle. After time t6 in FIG. 7, that is, if the read data is high impedance, the enable signal of the data bus drive control device E from the bus drive output control device G Is set to H level, and the state of the data bus is set to normal data output.

  In the period T5 from time t6 in FIG. 7, when the write data is H, the switch type pull-up element C and the P-type transistor A in FIG. A is turned off, the switch-type pull-down element D and the N-type transistor B are turned on when the write data is L, and the switch-type pull-down element D and the N-type transistor B are turned off when the write data is H.

  After the next cycle, that is, in the period T6 from time t7 in FIG. 7, the pseudo data control by pull-up and pull-down is returned to the normal transistor control. That is, when the write data is H, the P-type transistor A is turned on, when the write data is L, the write data is L, the N-type transistor B is turned on, and when the write data is H, the N-type transistor B is turned off. By turning off both switch-type pull-down elements D, the pseudo writing to the data bus is completed.

  As described above, according to the fourth embodiment, according to the content of the read data, if it is not high impedance, the output is stopped as input data, and the floating data is also input data (read data) in the write cycle. As in the second embodiment, even when the CPU 2 and the external memory 5 are continuously accessed, a bus collision between this data and the next cycle data is avoided. The memory access speed can be increased by shortening the bus cycle.

  Also, pull-up, pull-down control and transistor control are performed at the same time when switching the input / output of the data signal, so that when the read data is in a high impedance state, the pull-up / pull-down element is turned ON and the write data is Generation of a spike phenomenon can be prevented by creating it in a pseudo manner.

(Embodiment 5)
Next, a microcomputer according to the fifth embodiment will be described. FIG. 8 shows a configuration of a microcomputer having an input / output control device and a data bus drive control device in the fifth embodiment. In FIG. 8, H is an internal register constituting the data bus drive controller E, and stores a value corresponding to a known data floating time. FIG. 9 is a timing chart for explaining the operation of the microcomputer having the input / output control apparatus according to the fifth embodiment. In the figure, the same reference numerals as those in FIG. 1 denote the same or corresponding parts, time t8 is the read access end time and write access start time, time t9 is the previous cycle time after floating data output, and time t10 is the floating data in the external memory. The next cycle start time after output, time t11, is the next cycle start time of the next cycle start time after floating data output at time t10.

The operation of the microcomputer of the fifth embodiment configured as described above will be described below.
In the case of the fixed wait mode, when the CPU 2 retrieves the stored data from the external memory 5, the chip select signal CS and the address value to be accessed are output as the address signal AD to the memory access control device 3 to the external memory 5. Request access. When the memory access control device 3 receives the chip select signal CS and the address signal AD of the address to be accessed, it passes them to the external memory 5. At this point, memory access to the external memory 5 is started. Then, the chip select signal CS is negated in the set wait cycle, and the memory access is completed.

  Here, when the memory access between the CPU 2 and the external memory 5 continues, as shown in FIG. 9, the chip select signal CS remains asserted, and the read enable signal RE is changed during the read cycle. At the same time as being negated, the read data is finished.

  Then, by immediately asserting the write enable signal WE at time t8, the write cycle starts, but the read data floats for a certain period of time depending on the product standard value (data floating time) of the external memory 5, and therefore, as shown in FIG. The data floating time of the external memory 5 is set as an input value in the internal register H in the data bus drive E. The write data is stopped for the set time (T7 section), and then in the T8 section from time t9, the write data is H, the switch-type pull-up element C in FIG. When the write data is L, the switch type pull-down element D is turned on, and when the write data is H, the switch type pull-down element D is turned off. Thereby, when the read data is floating, the switch type pull-up element C and the switch type pull-down element D are OFF, so that the floating data is accepted as an input even during the write cycle. Also, immediately after the floating data is finished, it is switched to write data.

  In this way, the data signal is controlled in a pseudo manner by pull-up and pull-down control. Then, in the next cycle, that is, the period T9 from time t10 in FIG. 9, in conjunction with the pull-up and pull-down control, when the write data is H, the P-type transistor A is ON, when the write data is L, and when the write data is L At this time, the N-type transistor B is turned on and turned off when the write data is H.

  Then, after the next cycle, that is, in the period T10 from time t11 in FIG. 9, the pseudo data control by pull-up and pull-down is returned to the normal transistor control. That is, when the write data is H, the P-type transistor A is turned ON, when the write data is L, the P-type transistor A is turned OFF, when the write data is L, the N-type transistor B is turned ON, and when the write data is H, the N-type transistor B is turned OFF. Then, both the switch-type pull-up element C and the switch-type pull-down element D are turned off, thereby completing the pseudo write to the data bus.

  As described above, according to the fifth embodiment, when the data floating period of the external memory is known from the product standard, the internal register H for setting the time is provided in the data bus drive control device E. The memory access between the CPU 2 and the external memory 5 continues even for each external memory having a different data floating period by controlling the write data to be stopped for the corresponding time and accepting the floating data. Even in this case, a bus collision between the data currently being processed and the data of the next cycle can be avoided.

  In addition, in the next cycle after floating data output, by performing pull-up, pull-down control and transistor control together, the occurrence of spike phenomenon can be prevented.

(Embodiment 6)
Next, a microcomputer according to a sixth embodiment of the present invention will be described. FIG. 10 shows a configuration of a microcomputer having an input / output control device and a data bus drive control device according to the sixth embodiment. In this figure, the same reference numerals as those shown in FIGS. 1, 2, 3, 6, 8, and 11 denote the same or corresponding parts. In FIG. 10, I is in the data bus drive control device E. It is a data floating period measuring device for measuring a data floating time that is provided and changes depending on the operating environment.

The operation of the microcomputer of the sixth embodiment configured as described above will be described below with reference to FIG.
In the case of the fixed wait mode, when the CPU 2 retrieves the stored data from the external memory 5, the chip select signal CS and the address value to be accessed are output as the address signal AD to the memory access control device 3 to the external memory 5. Request access. When the memory access control device 3 receives the chip select signal CS and the address signal AD of the address to be accessed, it passes them to the external memory 5. At this point, memory access to the external memory 5 is started.

  Then, the chip select signal CS is negated in the set wait cycle, and the memory access is completed. Here, when the memory access between the CPU 2 and the external memory 5 continues, as shown in FIG. 7, the chip select signal CS remains asserted, and the read enable signal RE is set during the read cycle. At the same time as being negated, the read data is finished.

  At time t5, the write enable signal WE is immediately asserted to enter the write cycle, but the read data is floated for a certain period according to the product standard value (data floating time) of the external memory 5. Since this data floating time changes depending on the operating environment at that time (fluctuation of power supply voltage, temperature, humidity), the data floating period measuring device I in the data bus drive control device E in FIG. Measure the data floating time during processing other than when accessing external memory.

  At the time of subsequent external memory access, from the measurement result, the switch-type pull-up element C and the switch-type pull-down element D are turned off in the period T4 from time t5, and the floating data is accepted as an input even in the write cycle.

  In the next cycle, that is, the period T5 from time t6 in FIG. 7, along with the pull-up and pull-down control in the period T1 in FIG. 5, the write data is H, the P-type transistor A is ON, the write data is OFF, When the write data is L, the N-type transistor B is turned ON, and when the write data is H, the N-type transistor B is turned OFF.

  After the next cycle, that is, in the period T6 from time t7 in FIG. 7, the pseudo data control by pull-up and pull-down is returned to the normal transistor control. That is, the P-type transistor A is turned on when the write data is H, the P-type transistor A is turned off when the write data is L, the N-type transistor B is turned on when the write data is L, and the N-type transistor B is turned off when the write data is H Then, both the switch-type pull-up element C and the switch-type pull-down element D are turned off, thereby completing the pseudo write to the data bus.

  As described above, according to the sixth embodiment, the data floating period of the external memory is measured by the data floating period measuring device in the processing period other than the time when the external memory is accessed, and the data bus drive controller then pulls the result. Control the output data at the time of external memory access at the next opportunity using up, pull down, and transistor, and stop the write data for the corresponding time and control the floating data to be accepted, thereby floating the external memory A bus collision between data and data in the next cycle can be avoided.

  Further, as in the fifth embodiment, compared to the case where the data floating time as a standard is used, the data floating period that fluctuates around the reference value due to the power supply voltage, temperature, humidity, etc. is accurately measured and controlled. As a result, it can be expected to perform memory access control with higher accuracy than in the fifth embodiment.

  The microcomputer according to the present invention has an input / output control device and is useful as a system controller or the like that performs memory access with an external device.

1 is a configuration diagram of a microcomputer according to a first embodiment of the present invention. The block diagram of the input-output control apparatus of the microcomputer in the said Embodiment 1 and 3. FIG. The block diagram of the input / output control apparatus of the microcomputer in Embodiment 2 of this invention. The figure which described the timing chart for demonstrating operation | movement of the input / output control apparatus of the microcomputer in the said 1st and 2nd embodiment. The figure which described the timing chart for demonstrating operation | movement of the input / output control apparatus of the microcomputer in Embodiment 3 of this invention. The block diagram of the input / output control apparatus of the microcomputer in Embodiment 4 of this invention. The figure which described the timing chart for demonstrating operation | movement of the input / output control apparatus of the microcomputer in the said Embodiment 4 and 6. FIG. The block diagram of the input / output control apparatus of the microcomputer in Embodiment 5 of this invention. FIG. 10 is a timing chart for explaining the operation of the microcomputer input / output control device according to the fifth embodiment. The block diagram of the input / output control apparatus of the microcomputer in Embodiment 6 of this invention. The block diagram of the input / output control apparatus of the conventional microcomputer. The figure which described the timing chart for demonstrating operation | movement of the input / output control apparatus of the conventional microcomputer. The block diagram of the conventional microcomputer.

Explanation of symbols

1 Microcomputer 2 Central processing unit (CPU)
3 Memory access control device 4 Input / output control device 5 External memory A P-type transistor B N-type transistor C Switch-type pull-up device D Switch-type pull-down device E Data bus drive control device F Output control device G Bus drive output control device H Data Internal register I of bus drive controller I Data floating period measuring device AD Address signal DT from central processing unit Input / output data signal CS to central processing unit Chip select signal RE from central processing unit Read enable signal WE from central processing unit Write enable signal from the processing unit

Claims (6)

In a microcomputer having a central processing unit (CPU), a memory access control device, and an input / output control device, and performing data communication with an external memory via the input / output control device,
The input / output control device includes:
Pull-up and pull-down operations are performed at timings different from the clock to control input / output data, and signal control means that allows floating data to be accepted as input data in the write cycle,
A microcomputer characterized by that. In a microcomputer having a central processing unit (CPU), a memory access control device, and an input / output control device, and performing data communication with an external memory via the input / output control device,
The input / output control device includes:
The output data is controlled by the input data from the external memory, the data output is stopped except for the high impedance, and the signal control means that allows the floating data to be accepted as the input data even in the write cycle,
A microcomputer characterized by that. The microcomputer according to claim 1.
The signal control means includes
A buffer circuit composed of transistors for amplifying input / output data, and a data bus drive control device for fixing the output of the buffer circuit by pull-up or pull-down operation;
In the data floating output cycle of the external memory, the input / output data is controlled pseudo only by the pull-up / pull-down operation. In the next cycle, the pull-up / pull-down operation and the transistor are used for control, and the next cycle Then, only the transistor is controlled.
A microcomputer characterized by that. The microcomputer according to claim 1.
The signal control means includes
A buffer circuit comprising transistors for amplifying input / output data; a data bus drive control device for fixing the output of the buffer circuit by pull-up or pull-down operation; and a bus drive output control device for controlling the data bus drive control device; Have
The bus drive output control device monitors input data, controls the data bus drive control device based on the input data, and switches the control method in each cycle together with the pull-up, pull-down operation and transistor control. To control,
A microcomputer characterized by that. The microcomputer according to claim 3.
The data bus drive control device includes:
An internal register for setting a data floating period of the external memory, and based on a value set in the internal register, the pull-up, pull-down operation, and control of output data in a transistor;
A microcomputer characterized by that. The microcomputer according to claim 3.
The data bus drive control device includes:
Data floating period measuring means for measuring the data floating period of the external memory;
In a period other than the time when the external memory is accessed, the data floating period of the external memory is measured by the previous period data floating period measuring means, and the pull-up, pull-down operation and control of output data at the transistor are performed based on the measured value. Do,
A microcomputer characterized by that.

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