JP2012098779A - Data output device, data input/output device, storage device, data processing system, and control method of data output device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the collision of data while ensuring versatility in a data bus connecting a plurality of memories.SOLUTION: A control circuit 110 inputs data to an output driver 170 just from a starting point of a data output term to the lapse of a drive term shorter than the data output term, and causes a latch circuit 180 to stop supplying a current after the lapse of the data output term. The output driver 170 supplies to an output terminal 190 a driver current of which the absolute value becomes a predetermined value by applying a potential corresponding to a value of the inputted data to the output terminal 190. The latch circuit 180 holds the potential applied to the output terminal 190 and supplies to the output terminal a latch current of which the absolute value becomes smaller than the predetermined value by applying the held potential to the output terminal 190.

Description

  The present invention relates to a data output device, and more particularly to a data output device that outputs data stored in a storage element, a data input / output device, a storage device, a data processing system, and a control method for the data output device.

  Conventionally, when a processor and a plurality of memories are mounted in a data processing system, a configuration in which a data bus shared by the processor and each memory is provided and the processor accesses each memory via the data bus has been common. . In the data processing system, these memories and processors are mounted in a plane or three-dimensionally through TSV (Through-Silicon-Via) or the like.

  In a configuration in which a plurality of memories and processors are mounted, when the processor sequentially outputs data to each memory via a data bus, the memories may not be completely synchronized due to variations in characteristics of the memories. If the data output of each memory is not synchronized, data collision may occur. Data collision means that a plurality of memories simultaneously output data to the data bus. Each memory outputs data by applying a potential according to the data value to the data bus. The applied potential is a power supply level potential or a ground level potential of the memory. When a data collision occurs, for example, one memory may apply a power supply level potential, and another memory may apply a ground level potential. In this case, a current may flow from the power supply of one memory to the ground of the other memory via the data bus, which may cause a short circuit.

  In order to prevent such data collision, a data output device has been proposed in which each memory outputs data for a shorter period (see, for example, Patent Document 1). By shortening the period in which each memory outputs data, data collision is prevented even when the memories are not completely synchronized. In this data output device, each memory includes a phase adjustment circuit for adjusting the phase. Since each memory uses a phase adjustment circuit to output data in complete synchronization, the possibility of data collision is further reduced.

  There has also been proposed a data output device that adjusts the wiring length of the clock signal line of each memory and provides a delay control circuit for each memory (see, for example, Patent Document 2). This clock signal line is a signal line for transmitting a data read command or the like from the memory controller. Although the delay time of data transmission differs depending on the physical position of each memory, the wiring length is adjusted according to the delay time. The delay control circuit of each memory advances the internal operation clock for a time corresponding to the wiring length. For this reason, the phases of the internal operation clocks of the data in the respective memories coincide. As a result, data collision is prevented.

  Furthermore, a data output device that latches the output of data from each memory has been proposed (see, for example, Patent Document 3). This memory includes a connection node, an output buffer, and a bus keeper circuit. The connection node is a node connected to the data bus. The output buffer applies a potential according to the data value to the connection node. The bus keeper circuit holds the potential when the output buffer applies a potential to the connection node, and continues to apply the held potential to the connection node while the output buffer does not apply the potential. However, the current supplied by the bus keeper circuit is weak compared to the current supplied by the output buffer. With this configuration, even when the time for which each output buffer applies a potential is shortened, the bus keeper circuit holds the potential, so that the data output period can be lengthened. In addition, since the current supplied by the bus keeper circuit is weak compared to the current supplied by the output buffer, even if the potential of the bus keeper circuit of one memory and the output buffer of another memory is applied simultaneously, data collision will occur. Does not occur. Therefore, data collision can be prevented while lengthening the period during which the memory outputs data.

Japanese Patent No. 41262364 Japanese Patent Laid-Open No. 10-187592 JP 2004-362346 A

  However, the above-described conventional technology has a problem that the versatility is poor. Specifically, when each memory is configured to shorten the period during which data is output to the data bus, the margin for the operation in which the processor receives data is reduced.

  Further, in the case where each memory is provided with a phase adjustment circuit or a delay control circuit, the current consumption of the memory increases by the amount of those circuits. Further, when a phase adjustment circuit or the like is configured by a circuit that performs analog control, the circuit scale generally increases, and the area of the memory chip increases. Further, data collision cannot be reliably prevented outside the frequency band that can be handled by the phase adjustment circuit or the like.

  Further, in the case where a bus keeper circuit is provided in each memory, a plurality of bus keeper circuits hold potentials, thereby increasing the potential holding power of the data bus. For this reason, as the number of bus keeper circuits increases, it becomes more difficult to invert the potential of the data bus.

  As described above, the above-described technique has a problem in that it has poor versatility because applicable configurations are limited.

  The present invention has been made in view of such a situation, and an object of the present invention is to prevent data collision while ensuring versatility in a data bus connecting a plurality of memories.

  The present invention has been made in order to solve the above-mentioned problems, and a first aspect of the present invention is that an absolute value is obtained by applying an electric potential corresponding to the value of an input terminal and an input data to the output terminal. An output driver for supplying a driver current having a predetermined value to the output terminal, and holding the potential applied to the output terminal, and applying the held potential to the output terminal makes the absolute value the predetermined value A latch unit for supplying a latch current smaller than the value to the output terminal, and a drive period shorter than the data output period from the start of the data output period, which is a period for supplying the driver current or the latch current to the output terminal. The data is input to the output driver only until the time elapses, and the latch power is supplied to the latch unit when the data output period elapses. Data output device and a control unit for stopping the supply of, and a control method thereof. Thus, the output driver supplies a drive current by applying a potential corresponding to the data value to the output terminal only from the start of the data output period until the drive period elapses, and the data output period elapses. Sometimes, the latch unit has an effect of stopping the supply of the latch current.

  In the first aspect, the control unit obtains a clock signal in which a half of the clock period is the drive period, and determines whether the drive period has elapsed from the start time based on the clock signal. By determining, the data may be input to the output driver only during the drive period. Thus, there is an effect that it is determined based on the clock signal whether the drive period has elapsed from the start of the data output period.

  In the first aspect, the control unit generates an internal signal that is delayed by the drive period from the start time, and the output driver is only from the start time until the delay time of the internal signal elapses. You may enter data into Thus, there is an effect that data is input to the output driver only from the start of the data output period until the delay time of the internal signal elapses.

  In the first aspect, the control unit may cause the latch unit to supply the latch current only during a period from the start time to when the data output period has elapsed. As a result, the latch unit supplies a latch current over the data output period.

  In the first aspect, the control unit may supply the latch current to the latch unit only from the time when the drive period has elapsed until the time when the data output period has elapsed. Thus, the latch unit supplies the latch current only from the time when the drive period elapses until the time when the data output period elapses.

  In the first aspect, the control unit obtains a clock signal having a clock period shorter than the data output period and a half of the clock period longer than the first drive period and the second drive period, Data may be input to the output driver only from the rising edge of the clock signal until the first drive period elapses and from the falling edge of the clock signal until the second drive period elapses. Good. As a result, the output driver supplies the drive current only between the rise of the clock signal and the time when the first drive period elapses and until the second drive period elapses after the fall of the clock signal. This brings about the effect.

  Further, in the first aspect, the control unit generates a shift clock signal in which the phase of the clock signal is shifted by a predetermined period, and a rising edge of the clock signal from a rising edge of the clock signal. Data is input to the output driver only until the time point and from the falling edge of the clock signal to the falling edge of the shift clock signal, and when the data output period elapses, current is supplied to the latch unit. And an output control unit that stops supply. As a result, the output driver supplies the drive current only from the rising edge of the clock signal to the falling edge of the shift clock signal and from the falling edge of the clock signal to the falling edge of the shift clock signal. .

  In the first aspect, when the plurality of data output devices are connected to the path to which the output terminal is connected, the control unit outputs the output only from the start time until the drive period elapses. When the data is input to the driver and the supply of current to the latch unit is stopped when the data output period has elapsed, and only one data output device is connected to the path, only during the data output period Data may be input to the output driver and the latch unit may be disabled. Thereby, when there is one data output device connected to the path, the latch unit becomes invalid.

  The second aspect of the present invention provides an input / output terminal and a current whose absolute value becomes a predetermined value by applying a potential according to the value of the data to the input / output terminal only while data is being input. And an output driver for supplying a current to the input / output terminal, and holding a potential applied to the input / output terminal when a current based on an internal resistance having a predetermined resistance value is supplied to the output terminal. A latch unit that supplies a current whose absolute value is smaller than the predetermined value to the output terminal by applying the potential to the output terminal, and a period in which a current corresponding to the data is to be supplied to the input / output terminal The data is input to the output driver only from the start of the data output period until the drive period shorter than the data output period elapses, and the data output period elapses. A data input-output device including an input unit for generating data corresponding to the potential applied to the control unit and the input-output terminal for stopping the supply of the latch current to the latch portion when the. As a result, the output driver supplies a current by applying a potential corresponding to the data value to the output terminal only from the start of the data output period until the drive period elapses, and when the data output period elapses In addition, the latch unit has an effect of stopping the supply of the latch current.

  According to a third aspect of the present invention, there is provided a storage element that stores data and outputs data to a data output device when data output is requested, and a request unit that requests the storage element to output the data. And an output terminal, an output driver for supplying a driver current having an absolute value to a predetermined value by applying a potential according to the value of the input data to the output terminal, and applying to the output terminal A latch unit that holds the potential that has been held and supplies the latched potential to the output terminal by applying the held potential to the output terminal, and the driver current or the latch The output driver only during a period from the start of the data output period, which is a period in which current should be supplied to the output terminal, until a drive period shorter than the data output period elapses. And a data output device including a control unit that inputs the data output from the storage element to the storage unit and stops the supply of the latch current to the latch unit when the data output period has elapsed. It is a storage device. As a result, the output driver supplies a current by applying a potential corresponding to the data value to the output terminal only from the start of the data output period until the drive period elapses, and when the data output period elapses In addition, the latch unit has an effect of stopping the supply of the latch current.

  According to a third aspect of the present invention, a driver current whose absolute value is a predetermined value is supplied to the output terminal by applying a potential corresponding to the value of the input terminal and the input data to the output terminal. An output driver and a latch for holding a potential applied to the output terminal and supplying a latch current whose absolute value is smaller than the predetermined value to the output terminal by applying the held potential to the output terminal And the data output to the output driver only from the start of the data output period, which is a period during which the driver current or the latch current should be supplied to the output terminal, until a drive period shorter than the data output period elapses. And a controller that stops the supply of the latch current to the latch unit when the data output period has elapsed. A data output device, a path connected to the output terminal included in the plurality of data output devices, and a processing device that generates and processes data corresponding to the potential applied to the path System. As a result, the output driver supplies a current by applying a potential corresponding to the data value to the output terminal only from the start of the data output period until the drive period elapses, and when the data output period elapses In addition, the latch unit has an effect of stopping the supply of the latch current.

  According to the present invention, it is possible to achieve an excellent effect that data collision can be prevented while ensuring versatility in a data bus connecting a plurality of memories.

1 is an overall view showing a configuration example of a data processing system according to a first embodiment of the present invention. FIG. 3 is a block diagram illustrating a configuration example of a memory according to the first embodiment of the present invention. It is a block diagram which shows the example of 1 structure of the data output device in the 1st Embodiment of this invention. It is a truth table which shows an example of operation | movement of the control circuit in the 1st Embodiment of this invention. It is a circuit diagram showing an example of 1 composition of a data output device in a 1st embodiment of the present invention. It is a table | surface which shows an example of operation | movement of the output driver in the 1st Embodiment of this invention. It is a flowchart which shows an example of the control procedure of the data output device in the 1st Embodiment of this invention. It is a timing chart which shows an example of the operation result of the data output device in a 1st embodiment of the present invention. It is a timing chart which shows an example of the operation result of the data output device in a 1st embodiment of the present invention. It is a timing chart which shows an example of the operation result of the data processing system in a 1st embodiment of the present invention. It is a circuit diagram which shows one structural example of the control circuit in the 2nd Embodiment of this invention. It is a timing chart which shows an example of the operation result of the data output device in a 2nd embodiment of the present invention. It is a circuit diagram which shows one structural example of the control circuit in the 3rd Embodiment of this invention. It is a truth table which shows an example of operation | movement of the control circuit in the 3rd Embodiment of this invention. It is a flowchart which shows an example of the control procedure of the data output device in the 3rd Embodiment of this invention. It is a timing chart which shows an example of the operation result of the data output device in a 3rd embodiment of the present invention. It is a block diagram which shows one structural example of the data input / output device in the 4th Embodiment of this invention. It is a circuit diagram which shows one structural example of the control circuit in the 5th Embodiment of this invention. It is a flowchart which shows an example of the control procedure of the data output device in the 5th Embodiment of this invention. It is a timing chart which shows an example of the operation result of the data output device in a 5th embodiment of the present invention. It is a timing chart which shows an example of the operation result of the data processing system in a 5th embodiment of the present invention. It is a circuit diagram which shows the modification of the control circuit in the 5th Embodiment of this invention. It is a circuit diagram which shows the modification of the data output circuit in the 1st Embodiment of this invention. It is a general view which shows the modification of the data processing system in the 1st Embodiment of this invention.

Hereinafter, modes for carrying out the present invention (hereinafter referred to as embodiments) will be described. The description will be made in the following order.
1. First embodiment (control of data output device: example using clock signal)
2. Second embodiment (control of data output device: example in which clock signal is not used)
3. Third Embodiment (Control of Data Output Device: Example of Shortening the Latch Period)
4). Fourth embodiment (control of data input / output device: example of inputting / outputting data)
5. Fifth Embodiment (Data Output Device Control: Example of DDR System)
6). Modified example

<1. First Embodiment>
[Data processing system configuration example]
FIG. 1 is an overall view showing a configuration example of a data processing system according to the first embodiment of the present invention. The data processing system includes a plurality of memories 100, a processor 200, a data bus 300, and signal lines 401 to 406. The memory 100 and the processor 200 are mounted in a plane in the data processing system, and these are connected to the data bus 300.

  The memory 100 stores data and outputs stored data according to the control of the processor 200. The memory 100 is connected to the data bus 300 by signal lines 401 to 403. The memory 100 operates in synchronization with the external clock signal CLK.

  A signal line 401 transmits a read command CMD and a read address ADR input to the memory 100. The signal line 402 transmits the mode signal MODE input to the memory 100. The signal line 403 transmits data DATA output from the memory 100. Here, the read command CMD is a signal for instructing data reading. The mode signal MODE is a signal indicating whether or not the processor 200 continuously reads data from a plurality of memories. For example, when the processor 200 continuously reads data from a plurality of memories, the mode signal MODE is set to the “H” (high) state; otherwise, the mode signal MODE is set to the “L” (low) state. Data DATA is data stored in the memory 100.

  The memory 100 receives the read command CMD, the read address ADR, and the mode signal MODE output from the processor 200 via signal lines 401 and 402. If the read command signal is in the “H” state, the memory 100 extracts data from the storage element corresponding to the read address. The memory 100 outputs the data to the processor 200 via the signal line 403. Here, the memory 100 changes the operation of outputting data according to the value of the mode signal. Details of the operation of the memory 100 based on the mode signal will be described later with reference to FIG.

  The processor 200 receives data from the memory 100 and processes the received data. The processor 200 is connected to the data bus 300 by signal lines 404 to 406. The processor 200 includes a processing unit 210 and a data input device 220.

  A signal line 404 transmits the read command CMD and the read address ADR output from the processor 200. A signal line 405 transmits the mode signal MODE output from the processor 200. A signal line 406 transmits data DATA input to the processor 200.

  The processing unit 210 generates a read command CMD, a read address ADR, and a mode signal MODE, and processes input data DATA. The data input device 220 inputs data received from the memory 100 to the processing unit 210. When reading data from the memory 100, the processing unit 210 first generates a read command, a read address, and a mode signal. The processing unit 210 outputs a read command and a read address to the memory 100 via the signal line 404. Further, the processor 200 outputs a mode signal to the memory 100 via the signal line 405. The data input device 220 receives data from the memory 100 via the signal line 406 and inputs the data to the processing unit 210. The processing unit 210 processes the input data.

  The data bus 300 is a common path through which the plurality of memories 100 and the processor 200 exchange a read command CMD, a read address ADR, a mode signal MODE, and data DATA.

  The processor 200 of the above-described embodiment is an example of a processing device described in the claims. The data bus 300 of the above-described embodiment is an example of a route described in the claims.

  FIG. 2 is a block diagram showing a configuration example of the memory 100 according to the first embodiment of the present invention. The memory 100 includes an internal clock generation unit 104, a decoder 105, a memory cell array 106, and a data output device 110.

  The internal clock generation unit 104 generates an internal clock signal RDCLK. The internal clock signal is a signal for synchronizing devices inside the memory 100. The internal clock generation unit 104 generates an internal clock signal whose phase is slightly delayed from the external clock signal CLK from the external clock signal CLK. The internal clock generation unit 104 inputs the generated internal clock signal to the decoder 105, the memory cell array 106, and the data output device 110.

  The decoder 105 decodes the read command CMD and the read address ADR. A read command and a read address are input to the decoder 105 by the processor 200 via the signal line 401. The decoder 105 decodes the read command and generates a read command signal RD. The read command signal is a signal that is set to the “H” state only during a period during which the data output device 110 should supply the data bus 300 with a current based on data (hereinafter referred to as “data output period”). The data output period is set to a period sufficient for the processor 200 to receive data. The decoder 105 outputs a read command signal to the data output device 110. Further, the decoder 105 requests the storage element corresponding to the read address to output data based on the read address. Specifically, the decoder 105 acquires a row address and a column address from the read address. Then, the decoder 105 generates a RAS (Row Address Strobe) signal that specifies a row address and a CAS (Column Address Strobe) signal that specifies a column address, and outputs them to the memory cell array 106.

  The memory cell array 106 stores a plurality of data. The memory cell array 106 includes a plurality of memory cells, and an address is assigned to each memory cell. Each memory cell can store data. Memory cell array 106 outputs data stored in memory cells corresponding to RAS and CAS output from decoder 105 to data output device 110.

  The data output device 110 outputs the data output from the memory cell array 106 to the data bus 300 via the signal line 403. The data output device 110 receives data from the memory cell array 106 and a read command signal from the decoder 105. Further, the mode signal MODE from the processor 200 is input to the data output device 110 via the signal line 402. The data output device 110 outputs data to the signal line 403 during the ON period of the read command signal by an operation based on the mode signal.

  The decoder 105 of the above-described embodiment is an example of the request unit described in the claims. The memory cell of the above-described embodiment is an example of a memory element described in the claims.

  FIG. 3 is a block diagram showing a configuration example of the data output device 110 according to the first embodiment of the present invention. The data output device 110 includes a control circuit 120, an output driver 170, a latch circuit 180, and an output terminal 190. The control circuit 120 and the output driver 170 are connected by signal lines C1 and C2. The control circuit 120 and the latch circuit 180 are connected by a signal line L1.

  The control circuit 120 controls the output driver 170 and the latch circuit 180. The control circuit 120 receives data DATA, a read command signal RD, an internal clock signal RDCLK, and a mode signal MODE. The control circuit 120 generates a driver control signal DCtl and a latch enable signal LEN based on the input signal. Details of the operation of the control circuit 120 will be described later with reference to FIG.

  The driver control signal is a signal that controls the state of the output driver 170. The output driver 170 takes a valid or invalid state. The valid state means taking one of the “H” state and the “L” state. The invalid state is also called a high impedance (Hi-Z) state. The output driver control signal designates any one of “H” state, “L” state, and high impedance state by 2-bit information. The 2-bit information is composed of 1-bit information transmitted through the signal line C1 and 1-bit information transmitted through the signal line C2. Here, the “H” state is a state in which the output driver 170 applies a higher potential to the output terminal 190 than in the “L” state. The “L” state is a state in which the output driver 170 applies a lower potential to the output terminal 190 than in the “H” state. For example, the potential in the “H” state is a potential at the power supply level of the output driver 170, and the potential in the “L” state is a potential at the ground level of the output driver 170. The high impedance state is a state where the output driver 170 does not apply a potential to the output terminal 190.

  When the control circuit 120 controls the output driver 170 to the “H” state or the “L” state, the driver control signal is a signal corresponding to the data value. In other words, the control circuit 120 inputs data to the output driver 170 while the output driver 170 is in a valid state.

  The latch enable signal LEN is a signal that controls the latch circuit 180. The latch circuit 180 is controlled to be valid or invalid by a latch enable signal. Details of the operation of the latch circuit 180 in these states will be described later. For example, the latch enable signal is set to the “H” state when the latch circuit 180 is enabled, and is set to the “L” state when the latch circuit 180 is disabled.

  An operation of control circuit 120 when the mode signal is in the “H” state will be described. In this case, the control circuit 120 generates a driver control signal that enables the output driver 170 for a certain period shorter than the data output period after the read command signal becomes “H”. Hereinafter, the period during which the output driver is enabled is referred to as a “drive period”. For example, a period in which the internal clock signal is in the “H” state is set as a drive period. While the read command signal or the internal clock signal is in the “L” state, that is, a period other than the drive period, the control circuit 120 generates a driver control signal that puts the output driver 170 into an invalid state, that is, a high impedance state. While the read command signal is in the “H” state, the control circuit 120 generates a latch enable signal that makes the latch circuit 180 effective. While the read command signal is in the “L” state, the control circuit 120 generates a latch enable signal that disables the latch circuit 180.

  Next, the operation of the control circuit 120 when the mode signal is in the “L” state will be described. In this case, if the read command signal is in the “H” state, the control circuit 120 generates a driver control signal that makes the output driver 170 effective. As a result, the data output period becomes the drive period. On the other hand, if the read command signal is in the “L” state, the control circuit 120 generates a driver control signal that puts the output driver 170 in a high impedance state. The control circuit 120 generates a latch enable signal that disables the latch circuit 180 regardless of the values of the read command signal, the internal clock signal, and the data.

  The latch circuit 180 holds the potential applied to the output terminal 190 and applies the held potential to the output terminal 190. The latch circuit 180 takes a valid or invalid state according to the latch enable signal.

  The effective state of the latch circuit 180 is a state in which the latch circuit 180 holds the potential applied to the output terminal 190 and applies the held potential to the output terminal 190. Here, the current supplied to the output terminal 190 when the latch circuit 180 applies the potential is weak compared to the current supplied to the output terminal 190 when the output driver 170 applies the potential. To do. Hereinafter, the current supplied from the output driver 170 is referred to as “driver current”, and the current supplied from the latch circuit 180 is referred to as “latch current”. More specifically, when the output driver 170 and the latch circuit 180 apply the potential of the “H” level or the “L” level, the driver current having a value within a certain range or the current depending on the potential value to be applied. A latch current is supplied. The latch current is weak means that the range of the latch current is much narrower than the range of the driver current. In other words, the absolute value of the latch current is smaller than the absolute value of the driver current. Therefore, while the output driver 170 is applying a potential, the driver current is preferentially supplied to the output terminal 190 even if the latch circuit 180 applies the potential. Further, it is assumed that the driver current is equal to or higher than the driving current necessary for inverting the potential value held by the latch circuit 180. Therefore, when the output driver 170 applies a potential to the output terminal 190, the latch circuit 180 updates the held potential with the potential applied to the output terminal 190. When not only an output driver in the same memory but also an output driver in another memory applies a potential to the output terminal 190, the latch circuit 180 updates the held potential.

  On the other hand, the invalid state of the latch circuit 180 is a state in which the latch circuit 180 stops holding and updating the potential of the output terminal 190 and applying the potential to the output terminal 190.

  The output terminal 190 is a terminal connected to the data bus 300 via the signal line 403.

  The control circuit 120 of the above-described embodiment is an example of a control unit described in the claims. The latch circuit 180 of the above-described embodiment is an example of a latch unit described in the claims.

  FIG. 4 is a truth table showing an example of the operation of the control circuit 120 according to the first embodiment of the present invention. First, the driver control signal DCtl generated when the mode signal is “H” will be described. In this state, when the read command signal is in the “L” state, control circuit 120 generates a driver control signal that puts output driver 170 in a high impedance state regardless of the values of the internal clock signal and data. When the read command signal and the internal clock signal are in the “H” state, and the data value is “1”, the control circuit 120 generates a driver control signal that puts the output driver 170 in the “H” state. Further, when the read command signal and the internal clock signal are in the “H” state, if the data value is “0”, the control circuit 120 generates a driver control signal that puts the output driver 170 in the “L” state. When the read command signal is in the “H” state and the internal clock signal is in the “L” state, the control circuit 120 generates a driver control signal that sets the output driver 170 in the high impedance state regardless of the data value.

  Next, a latch enable signal generated when the mode signal is in the “H” state will be described. In this state, when the read command signal is in the “L” state, control circuit 120 generates a latch enable signal that disables latch circuit 180 regardless of the values of the internal clock signal and data. On the other hand, when the read command signal is in the “H” state, control circuit 120 generates a latch enable signal that makes latch circuit 180 valid regardless of the values of the internal clock signal and data.

  As described above, when the mode signal is in the “H” state and the read command signal and the internal clock signal are in the “H” state, the control circuit 120 sets the output driver 170 to the valid state. Otherwise, the control circuit 120 controls the output driver 170 to an invalid state, that is, a high impedance state. Here, as described above, the read command signal is output in synchronization with the internal clock signal. Further, the ON period of the read command signal (that is, the data output period) is set longer than the ON period of the clock signal (that is, the drive period). Therefore, the output driver 170 is valid only from the start of the data output period until a drive period shorter than that period elapses. On the other hand, the latch circuit 180 is controlled to be in an effective state during the data output period.

  In summary, the output driver 170 applies a potential corresponding to the value of data to the output terminal 190 only from the start of the data output period until the drive period elapses. The latch circuit 180 applies a potential instead of the output driver 170 after the drive period elapses until the data output period elapses. As a result, the driver current or latch current based on the data is supplied to the output terminal 190 during the data output period. In other words, data is output from the output terminal 190 over the data output period.

  Next, a driver control signal and a latch enable signal generated when the mode signal is “L” will be described. In this state, when the read command signal is in the “L” state, control circuit 120 generates a driver control signal that puts output driver 170 in a high impedance state regardless of the values of the internal clock signal and data. If the value of the data is “1” when the read command signal is in the “H” state, the control circuit 120 generates a driver control signal that puts the output driver 170 in the “H” state. If the data value is “0” when the read command signal is in the “H” state, the control circuit 120 generates a driver control signal that puts the output driver 170 in the “L” state. On the other hand, the control circuit 120 generates a latch enable signal that disables the latch circuit 180 regardless of the values of the read command signal, the internal clock signal, and the data.

  Thus, when the mode signal is in the “L” state, the control circuit 120 enables the output driver 170 and disables the latch circuit 180 only during the period when the read command signal is on. Accordingly, during the data output period, the driver current is supplied by the output driver 170, and the latch current is not supplied.

  FIG. 5 is a circuit diagram showing a configuration example of the data output device 110 according to the first embodiment of the present invention. The data output device 110 includes a control circuit 120, an output driver 170, a latch circuit 180, and an output terminal 190.

  The control circuit 120 includes inverters 121 and 125, NAND gates 122 and 126, AND gates 123 and 124, and a NOR gate 127.

  The inverter 121 inverts the input value and outputs it. The internal clock signal RDCLK is input to the input terminal of the inverter 121. Inverter 121 inverts the value of the internal clock signal and outputs the result to NAND gate 122.

  The NAND gate 122 outputs a negative logical product of the input values. The NAND gate 122 has two input terminals. A signal output from the inverter 121 is input to one input terminal of the NAND gate 122, and a mode signal MODE is input to the other input terminal. The NAND gate 122 outputs a negative logical product of the values of these signals to the AND gate 123.

  The AND gate 123 outputs a logical product of input values. The AND gate 123 has two input terminals. The read command signal RD is input to one input terminal of the AND gate 123, and the signal output from the NAND gate 122 is input to the other input terminal. The AND gate 123 outputs a logical product of these signal values to the inverter 125 and the NAND gate 126.

  With the above configuration, the AND gate 123 generates a signal that is in the “H” state when the read command signal, the internal clock signal, and the mode signal are all in the “H” state, and in the “L” state otherwise. To do. As described above with reference to FIG. 4, when the read command signal, the internal clock signal, and the mode signal are all in the “H” state, the output driver 170 determines whether the “H” state or “ The “L” state needs to be taken. When the read command signal, the internal clock signal, or the mode signal is in the “L” state, the output driver 170 needs to be in a high impedance state. Therefore, the signal generated by the AND gate 123 is a signal for controlling the output driver 170 to be in a valid or invalid state. Hereinafter, a signal output from the AND gate 123 is referred to as an output driver enable signal OEN.

  The inverter 125 inverts the input value and outputs it. The signal output from the AND gate 123 is input to the input terminal of the inverter 125. Inverter 125 inverts the value of the input signal and outputs the result to NOR gate 127.

  The NAND gate 126 outputs a negative logical product of the input values. The NAND gate 126 has two input terminals. Data is input to one input terminal of the NAND gate 126, and a signal output from the AND gate 123 is input to the other input terminal. The NAND gate 126 outputs a negative logical product of the values of these signals to the output driver 170 via the signal line C1.

  The NOR gate 127 outputs a negative logical sum of input values. The NOR gate 127 has two input terminals. Data is input to one input terminal of the NOR gate 127, and a signal output from the inverter 125 is input to the other input terminal. The NOR gate 127 outputs a negative logical sum of the values of these signals to the output driver 170 via the signal line C2.

  With the above configuration, when the output driver enable signal is in the “L” state, the signal transmitted through the signal line C1 is in the “H” state, and the signal transmitted through the signal line C2 is in the “L” state. These signals constitute a driver control signal for controlling the output driver 170 to a high impedance state. When the output driver enable signal and the data are in the “H” state, the signals transmitted through the signal lines C1 and C2 are both in the “L” state. These signals constitute a driver control signal for controlling the output driver 170 to the “H” state. When the output driver enable signal is in the “H” state and the data is in the “L” state, both signals transmitted through the signal lines C1 and C2 are in the “H” state. These signals constitute a driver control signal for controlling the output driver 170 to the “L” state.

  The AND gate 124 outputs a logical product of input values. The AND gate 124 has two input terminals. A mode signal is input to one input terminal of the AND gate, and a read command signal is input to the other input terminal. The AND gate 124 outputs a logical product of these signal values to the latch circuit 180 via the signal line L1.

  With the configuration described above, the AND gate 124 generates the latch enable signal LEN that is in the “H” state when the mode signal and the read command signal are in the “H” state, and that is in the “L” state otherwise.

  The output driver 170 includes a pMOS (positive channel metal oxide semiconductor) 171 and an nMOS (negative channel metal oxide semiconductor) 172.

  The pMOS 171 and the nMOS 172 control the supply of current to the output terminal 190 according to the gate voltage. Each of the pMOS 171 and the nMOS 172 includes a gate terminal, a source terminal, and a drain terminal. In the pMOS 171, the source terminal is connected to the power supply, the gate terminal is connected to the signal line C 1, and the source terminal is connected to the output terminal 190. In the nMOS 172, the source terminal is connected to the ground, the gate terminal is connected to the signal line C2, and the drain terminal is connected to the output terminal 190. If the signal transmitted through the signal line C1 is in the “L” state, the pMOS 171 is turned on. As a result, a power supply level potential is applied to the output terminal 190. If the signal transmitted through the signal line C1 is in the “H” state, the pMOS 171 is turned off. If the signal transmitted through the signal line C2 is in the “H” state, the nMOS 172 is turned on. As a result, the potential of the grant is applied to the output terminal 190. If the signal transmitted through the signal line C2 is in the “L” state, the nMOS 172 is turned off.

  FIG. 6 is a table showing an example of the operation of the output driver 170 in the first embodiment of the present invention. When the signal transmitted through the signal line C1 is in the “H” state and the signal transmitted through the signal line C2 is in the “L” state, both the pMOS 171 and the nMOS 172 are in the off state. As a result, no potential is applied to the output terminal 190. This state corresponds to the high impedance state of the output driver 170. When the signals transmitted through the signal line C1 and the signal line C2 are both in the “L” state, the pMOS 171 on the power supply side is turned on and the nMOS 172 is turned off. As a result, a power supply level potential is applied to the output terminal 190. This state corresponds to the “H” state of the output driver 170. When the signals transmitted through the signal line C1 and the signal line C2 are both in the “H” state, the pMOS 171 is turned off and the ground-side nMOS 172 is turned on. As a result, a ground level potential is applied to the output terminal 190. This state corresponds to the “L” state of the output driver 170.

  Returning to FIG. 5, the latch circuit 180 includes inverters 181 and 182. The inverters 181 and 182 invert the input value and output it. Inverter 181 includes a gate terminal, an input terminal, and an output terminal. The gate terminal of the inverter 181 is connected to the signal line L1. When the latch enable signal transmitted through the signal line L1 is in the “H” state, the inverter 181 inverts the value of the signal output from the inverter 181 and outputs it to the output terminal 190 and the inverter 182. An input terminal of the inverter 182 is connected to the inverter 181 and the output terminal 190. Inverter 182 inverts the value of the input signal and outputs the result to inverter 181. Here, it is assumed that the current output from the inverter 181 (that is, the latch current) is weak compared to the driver current. In addition, the drive current required to invert the inverter 182 is a value equal to or less than the driver current.

  With the configuration of the latch circuit 180 described above, the inverters 181 and 182 hold the potential applied to the output terminal 190 by the output driver 170 and apply the held potential to the output terminal 190.

  As described above, the control circuit 120 makes the output driver 170 effective from the start of the data output period until the ON period of the internal clock signal (that is, the drive period) elapses. Further, the latch circuit 180 is enabled only during the data output period. The output driver 170 applies a potential corresponding to the data value to the output terminal 190 in the valid state, and does not apply the potential in the invalid state. The latch circuit 180 holds the potential applied by the output driver 170 and applies the held potential to the output terminal 190. According to this configuration, the output driver 170 applies a potential to the output terminal 190 for a drive period shorter than the start time of the data output period. On the other hand, the latch circuit 180 is valid only during the data output period. Therefore, the latch circuit 180 applies a potential to the output terminal 190 instead of the output driver 170 until the data output period elapses even after the output driver 170 is disabled.

[Operation of data output device]
Next, the operation of the data output device 110 will be described with reference to FIG. FIG. 7 is a flowchart illustrating an example of a control procedure of the data output device 110 according to the first embodiment of the present invention. This control procedure starts when a mode signal in the “H” state is input to the data output device 110.

  The control circuit 120 determines whether or not the read command signal is in the “H” state (step S910). When the read command signal is in the “H” state (step S910: Yes), the control circuit 120 generates a latch enable signal that enables the latch circuit 180 (step S920). Further, the control circuit 120 generates a driver control signal that enables the output driver 170 while the internal clock signal is in the “H” state (step S930). Thereafter, when the internal clock signal is in the “L” state, the control circuit 120 generates a driver control signal that puts the output driver 170 into an invalid state, that is, a high impedance state (step S940). After step S940, the control circuit 120 returns to step S910.

  If the read command signal is not in the “H” state (step S910: No), the control circuit 120 generates a latch enable signal that disables the latch circuit 180 (step S950). After step S950, the control circuit 120 returns to step S910.

  Next, the operation result of the data output device 110 will be described with reference to FIGS. FIG. 8 is a timing chart showing an example of an operation result of the data output device 110 when the mode signal is in the “H” state in the first embodiment of the present invention.

  The processor 200 generates a read command CMD and a mode signal “MODE” in “H” state, and outputs them to the memory 100 in synchronization with the external clock signal CLK.

  The decoder 105 decodes the read command to generate a read command signal RD and inputs it to the data output device 110 in synchronization with the internal clock signal.

  The internal clock generation unit 104 generates an internal clock signal RDCLK in which the external clock is delayed.

  The AND gate 123 in the control circuit 120 generates an output driver enable signal OEN that enables the output driver 170 while the read command signal and the internal clock signal are in the “H” state.

  The AND gate 124 in the control circuit 120 generates a latch enable signal LEN that enables the latch circuit 180 during the ON period of the read command signal.

  The memory cell array 106 in the memory 100 outputs the stored data to the control circuit 120 in synchronization with the internal clock signal.

  The output driver 170 becomes valid according to the output driver enable signal OEN while the read command signal and the internal clock signal are in the “H” state. The output driver 170 is in an invalid state other than that period, that is, in a high impedance state.

  The latch circuit 180 is enabled during the ON period of the read command signal according to the latch enable signal LEN. The latch circuit 180 is in an invalid state, that is, a high impedance state except for that period.

  As a result, the data output device 110 outputs data by applying a potential by the output driver 170 while the read command signal and the internal clock signal are in the “H” state. During the period from when the internal clock signal becomes “L” to when the data output period elapses, the data output device 110 outputs data by applying a potential by the latch circuit 180.

  FIG. 9 is a timing chart showing an example of an operation result of the data output device 110 when the mode signal is in the “L” state according to the first embodiment of the present invention.

  The processor 200 generates a read command CMD and a mode signal “MODE” in the “L” state, and outputs them to the memory 100 in synchronization with the external clock signal CLK.

  The decoder 105 decodes the read command to generate a read command signal RD and inputs it to the data output device 110 in synchronization with the internal clock signal.

  The internal clock generation unit 104 generates an internal clock signal RDCLK in which the external clock is delayed.

  The AND gate 123 in the control circuit 120 generates an output driver enable signal OEN that enables the output driver 170 while the read command signal is in the “H” state.

  The AND gate 124 in the control circuit 120 generates a latch enable signal LEN that disables the latch circuit 180.

  The memory cell array 106 in the memory 100 outputs the stored data to the control circuit 120 in synchronization with the internal clock signal.

  The output driver 170 becomes valid according to the output driver enable signal OEN while the read command signal is in the “H” state. The output driver 170 is in an invalid state other than that period, that is, in a high impedance state.

  The latch circuit 180 enters an invalid state, that is, a high impedance state according to the latch enable signal LEN.

  As a result, the data output device 110 outputs data by applying the potential by the output driver 170 while the read command signal is in the “H” state. The latch circuit 180 is in an invalid state.

  FIG. 10 is a timing chart showing an example of the operation result of the data processing system according to the first embodiment of the present invention.

  Assume that the processor 200 reads data from “# 1” in the memory 100 and then reads data from “# 2” in the memory 100 at a certain clock. Then, it is assumed that reading of data from the memory “# 1” is delayed.

  The processor 200 outputs a mode signal in the “H” state to the memories “# 1” and “# 2” before continuously reading data from the memories “# 1” and “# 2”.

  The control circuit in the memory “# 1” activates the output driver only during the period in which the internal clock signal is in the “H” state according to the procedure illustrated in FIG. 8, and then latches until the data output period elapses. Enable the circuit. The memory “# 2” performs the same operation.

  Although the reading of data from the storage element in the memory “# 1” is delayed, the period in which the output driver is in a valid state is short. It does not overlap with the period when it enters the state. Therefore, it is possible to prevent data collisions caused by a plurality of output drivers applying potentials simultaneously.

  Here, since the reading of data from the memory “# 1” is delayed, the period in which the latch circuit of the memory “# 1” is in the valid state is the period in which the output driver in the memory “# 2” is in the valid state. And overlap. However, as described above, the drive current of the latch circuit is less than or equal to the current supplied by the output driver. Therefore, in the overlapping period, the potential held by the latch circuit of the memory “# 1” is updated by the potential applied by the output driver of the memory “# 2”. As a result, the potential applied by the latch circuit of the memory “# 1” is the same as the potential applied by the output driver of the memory “# 2”, and data collision does not occur.

  Thus, according to the first embodiment, the control circuit 120 enables the output driver 170 only during the on period of the internal clock signal from the start of the data output period. Further, the control circuit 120 enables the latch circuit 180 only during the data output period. The output driver 170 supplies a current to the output terminal 190 by applying a potential according to the data value. The latch circuit 180 holds the potential of the output terminal 190, applies the held potential to the output terminal 190, and supplies a weak current to the output terminal 190.

  According to this configuration, the drive period is shorter than the data output period. Therefore, when the processor 200 continuously reads data from the plurality of memories 100, it is possible to prevent a plurality of output drivers from applying potentials to the data bus 300 at the same time. For this reason, the data output device 110 can prevent data collision. Further, during the data output period, the latch circuit 180 holds the potential even after the output driver 170 is disabled, so that the memory 100 can output data over the data output period. Therefore, a sufficient margin for receiving data by the processor 200 can be secured. Furthermore, after the data output period has elapsed, the latch circuit 180 is disabled, so that the latch periods of the memories do not overlap. Therefore, the plurality of latch circuits do not continue to hold the potential of the data bus 300. As a result, it is possible to prevent the holding power of the data bus 300 from becoming too strong.

  When data is not continuously read from a plurality of memories, the processor 200 sets the mode signal to the “L” state, and the control circuit 120 sets the latch circuit 180 to an invalid state. Therefore, when the processor and the memory input / output data on a one-to-one basis, power consumption can be reduced by the amount of the latch circuit 180.

  In the first embodiment, the data output device 110 is mounted in the memory 100. However, if there are a plurality of devices mounted in the apparatus and they may output data to a common bus continuously, the data output device 110 may be mounted on a device other than the memory 100. Of course. For example, a device similar to the data output device 110 may be provided in each of the plurality of memory controllers.

  In the first embodiment, the control circuit 120 is configured by the circuit illustrated in FIG. However, as long as the operation of the truth table illustrated in FIG. 4 can be realized, the control circuit 120 may be configured by a circuit other than the circuit illustrated in FIG.

<2. Second Embodiment>
[Data processing system configuration example]
Next, a second embodiment of the present invention will be described with reference to FIGS. The data output device 111 of the second embodiment is different from the data output device 110 of the first embodiment in that the output driver 170 is controlled without using an internal clock signal. The data output device 111 is different from the data output device 110 of the first embodiment in that a control circuit 130 is provided instead of the control circuit 120.

  FIG. 11 is a circuit diagram showing a configuration example of the control circuit 130 according to the second embodiment of the present invention. The control circuit 130 does not receive the internal clock signal but receives the data DATA, the read command signal RD, and the mode signal MODE. The control circuit 130 is different from the control circuit 120 of the first embodiment in that a NAND gate 131 and inverters 132 and 133 are provided instead of the inverter 121 and the NAND gate 122.

  The NAND gate 131 outputs a negative logical product of the input values. The NAND gate 131 has two input terminals. The read command signal RD is input to one input terminal of the NAND gate 131, and the mode signal MODE is input to the other input terminal. The NAND gate 131 outputs a negative logical product of the values of these signals to the inverter 132.

  The inverters 132 and 133 invert the input value and output it. Inverter 132 inverts the value of the signal output from NAND gate 131 and outputs the result to inverter 133. Inverter 133 inverts the value of the signal output from inverter 132 and outputs the result to AND gate 123.

  Since read command signal RD is inverted and delayed by passing through NAND gate 131 and inverters 132 and 133, the signal output from inverter 133 is referred to as inverted delayed read command signal RDd. Therefore, the logical product OEN of the inverted delay read command signal RDd and the read command signal RD is a signal that sets the delay time of the inverted delay read command signal RDd to the on period. NAND gate 131 and inverters 132 and 133 are selected so that the delay time is shorter than the data output period.

  As described above, the control circuit 130 internally generates and uses the inverted delayed read command signal RDd whose delay time is shorter than the data output period without using the internal clock signal, thereby making the drive period shorter than the data output period. can do.

[Operation of data output device]
Next, the operation of the data output device 111 will be described with reference to FIG. FIG. 12 is a timing chart showing an example of the operation result of the data output device 111 according to the second embodiment of the present invention.

  The processor 200 generates a read command CMD and a mode signal MODE in the “H” state, and outputs them to the memory 100 in synchronization with the external clock signal CLK.

  The decoder 105 decodes the read command to generate a read command signal RD, and inputs the read command signal RD to the data output device 111 in synchronization with the internal clock signal.

  The internal clock generation unit 104 generates an internal clock signal RDCLK in which the external clock is delayed.

  By passing through NAND gate 131 and inverters 132 and 133, inverted delayed read command signal RDd is delayed with respect to read command signal RD.

  The AND gate 123 in the control circuit 130 generates an output driver enable signal OEN that enables the output driver 170 during the delay time of the inverted delayed read command signal RDd.

  The AND gate 124 in the control circuit 130 generates a latch enable signal LEN that makes the latch circuit 180 valid while the read command signal is on.

  The memory cell array 106 in the memory 100 outputs the stored data to the control circuit 130 in synchronization with the internal clock signal.

  The output driver 170 becomes valid according to the output driver enable signal OEN while the read command signal and the internal clock signal are in the “H” state. The output driver 170 is in an invalid state other than that period, that is, in a high impedance state.

  The latch circuit 180 is enabled during the ON period of the read command signal according to the latch enable signal LEN. The latch circuit 180 is in an invalid state, that is, a high impedance state except for that period.

  As a result, the data output device 111 outputs data by applying the potential by the output driver 170 during the delay time of the inverted delay read command signal RDd. Until the data output period elapses after the internal clock signal is set to the “L” state, the data output device 111 outputs data by the application of the potential by the latch circuit 180.

  As described above, according to the first embodiment, the control circuit 130 internally generates the inverted delayed read command signal RDd that is delayed with respect to the read command signal by a time shorter than the data output period, and during the delay time. Only the output driver 170 is enabled.

  According to this configuration, the output driver 170 can be enabled for a period shorter than the data output period without using the internal clock signal.

<3. Third Embodiment>
[Data processing system configuration example]
Next, a third embodiment of the present invention will be described with reference to FIGS. The data output device 112 of the third embodiment is different from the data output device 110 of the first embodiment in that the latch circuit 180 is enabled after the output driver 170 is disabled. . The data output device 112 is different from the data output device 110 of the first embodiment in that a control circuit 140 is provided instead of the control circuit 120.

  FIG. 13 is a circuit diagram showing a configuration example of the control circuit 140 according to the third embodiment of the present invention. The control circuit 140 is different from the control circuit 120 of the first embodiment in that it further includes an AND gate 141.

  The AND gate 141 outputs a logical product of input values. The AND gate 141 has two input terminals. The read command signal RD is input to one input terminal of the AND gate 141, and the signal output from the inverter 121 is input to the other input terminal. The AND gate 141 outputs a logical product of the values of these signals to the AND gate 124. The AND gate 124 outputs a logical product of the mode signal MODE and the value of the signal output from the AND gate 141 as a latch enable signal LEN.

  With this configuration, the control circuit 140 enables the latch circuit 180 when the mode signal and the read command signal are in the “H” state and the internal clock signal is in the “L” state, and otherwise. Disable it.

  FIG. 14 is a truth table showing an example of the operation of the control circuit 140 according to the second embodiment of the present invention.

  The control circuit 140 generates a latch enable signal LEN that enables the latch circuit 180 when the mode signal MODE and the read command signal RD are in the “H” state and the internal clock signal RDCLK is in the “L” state. To do. In other cases, the control circuit 140 generates a latch enable signal LEN that disables the latch circuit 180.

  In the first embodiment, the control circuit 140, as illustrated in FIG. 4, if the mode signal and the read command signal are in the “H” state, that is, within the data output period, regardless of the value of the internal clock signal. The latch circuit 180 was in an effective state. However, the control circuit 140 of the third embodiment does not enable the latch circuit 180 unless the internal clock signal is in the “L” state even during the data output period. When the internal clock signal is in the “L” state, the output driver 170 is in an invalid state. That is, the latch circuit 180 is in a valid state only from the time when the output driver 170 is disabled during the data output period until the data output period elapses.

[Operation of data output device]
Next, the operation of the data output device 112 will be described with reference to FIG. FIG. 15 is a flowchart illustrating an example of a control procedure of the data output device 112 according to the third embodiment of the present invention. This control procedure starts when a mode signal in the “H” state is input to the data output device 112.

  The control circuit 140 determines whether or not the read command signal is in the “H” state (step S910). When the read command signal is in the “H” state (step S910: Yes), the control circuit 140 generates a driver control signal that enables the output driver 170 while the internal clock signal is in the “H” state ( Step S925). After step S925, when the internal clock signal is in the “L” state, the control circuit 140 generates a driver control signal for setting the output driver 170 in the high impedance state (step S940). When the internal clock signal is in the “L” state, the control circuit 140 generates a latch enable signal that enables the latch circuit 180 (step S945). After step 945, the control circuit 140 returns to step S910.

  When the read command signal is not in the “H” state (step S910: No), the control circuit 140 generates a latch enable signal that disables the latch circuit 180 (step S950). After step 950, the control circuit 140 returns to step S910.

  Next, the operation result of the data output device 112 will be described with reference to FIG. FIG. 16 is a timing chart showing an example of the operation result of the data output device 112 when the mode signal is in the “H” state in the third embodiment of the present invention.

  The processor 200 generates a read command CMD and a mode signal “MODE” in “H” state, and outputs them to the memory 100 in synchronization with the external clock signal CLK.

  The decoder 105 decodes the read command to generate a read command signal RD, and inputs the read command signal RD to the data output device 112 in synchronization with the internal clock signal.

  The internal clock generation unit 104 generates an internal clock signal RDCLK in which the external clock is delayed.

  The AND gate 123 in the control circuit 140 generates an output driver enable signal OEN that enables the output driver 170 while the read command signal and the internal clock signal are in the “H” state.

  The AND gate 124 in the control circuit 140 generates a latch enable signal LEN that enables the latch circuit 180 while the read command signal is in the “H” state and the internal clock signal is in the “L” state. Here, the timing at which the output driver 170 switches from valid to invalid is slightly delayed from the timing at which the latch circuit 180 switches from invalid to valid. As shown in FIG. 13, the output driver enable signal needs to pass through the inverter 125, the NAND gate 126, and the NOR gate 127, whereas the latch enable signal does not go through the logic gate. It is. Therefore, the latch circuit 180 can hold the potential applied from the output driver 170 before the output driver 170 becomes invalid.

  The memory cell array 106 in the memory 100 outputs the stored data to the control circuit 140 in synchronization with the internal clock signal.

  The output driver 170 becomes valid according to the output driver enable signal OEN while the read command signal and the internal clock signal are in the “H” state. The output driver 170 is in an invalid state other than that period, that is, in a high impedance state.

  The latch circuit 180 is enabled when the internal clock signal is in the “L” state according to the latch enable signal LEN. The latch circuit 180 is in an invalid state, that is, a high impedance state except for that period.

  As described above, according to the third embodiment, the control circuit 140 includes the latch circuit 180 only during the period from when the output driver 170 is disabled within the data output period until the data output period elapses. Is enabled. With this configuration, the period during which the latch circuit 180 is enabled can be minimized, and the current consumption of the latch circuit 180 can be suppressed accordingly. Further, the period during which the latch circuit 180 holds the potential of the data bus 300 can be minimized, and the holding power of the data bus 300 can be reduced.

<4. Fourth Embodiment>
[Data processing system configuration example]
Next, a fourth embodiment of the present invention will be described with reference to FIG. The memory 100 of the fourth embodiment is different from the memory 100 of the first embodiment in that a data input / output device 113 is provided instead of the data output device 110.

  FIG. 17 is a circuit diagram showing a configuration example of the data input / output device 113 according to the fourth embodiment of the present invention. The data input / output device 113 has the same configuration as the data output device 110 of the first embodiment, except that it includes an input / output terminal 191 instead of the output terminal 190 and further includes an input circuit 185. The data input / output device 113 receives a write command signal WT from the processor 200. The write command signal is a signal that instructs the processor 200 to store data in the memory 100.

  The input circuit 185 includes an inverter 186. The inverter 186 inverts the value of the input signal and outputs it. Inverter 186 includes a gate terminal, an input terminal, and an output terminal. A write command signal is input to the gate terminal of the inverter 186. The write command signal is a signal generated by the decoder 105 decoding the write command generated by the processor 200. The input terminal of the inverter 186 is connected to the input / output terminal 191. When the write command signal is in the “H” state, inverter 186 inverts the value of the signal input from input / output terminal 191 and outputs the result to memory cell array 106. The memory cell array 106 stores the inverted value of the data output from the inverter 186 as write data. When the write command signal is in the “L” state, the inverter 186 is disabled and does not output data to the memory cell array 106.

  As described above, the data input / output device 113 includes the input circuit 185, and thus can input data to the storage element in addition to the output of data from the storage element.

<5. Fifth embodiment>
[Data processing system configuration example]
Next, a fifth embodiment of the present invention will be described with reference to FIGS. The data output device 114 of the fifth embodiment is different from the data output device 110 of the first embodiment in that a DDR (Double Data Rate) method is used.

  FIG. 18 is a circuit diagram showing a configuration example of the data output device 114 according to the fifth embodiment of the present invention. The data output device 114 is different from the data output device 110 of the first embodiment in that a control circuit 150 is provided instead of the control circuit 120.

  The control circuit 150 is different from the control circuit 120 of the first embodiment in that inverters 151 to 153, NAND gates 154 and 156, and an OR gate 155 are provided instead of the inverter 121 and the NAND gate 122.

  The inverters 151 to 153 invert input values and output the inverted values. Inverter 151 inverts the value of internal clock signal RDCLK and outputs the result to inverter 152. Inverter 152 inverts the value of the signal output from inverter 151 and outputs the result to inverter 153. Inverter 153 inverts the value of the signal output from inverter 152 and outputs the result to NAND gate 154 and OR gate 155.

  The NAND gate 154 outputs a negative logical product of the input values. The NAND gate 154 includes two input terminals. An internal clock signal is input to one input terminal of the NAND gate 154, and a signal output from the inverter 153 is input to the other input terminal. NAND gate 154 outputs a negative logical product of the values of these signals to NAND gate 156.

  The OR gate 155 outputs a logical sum of input values. The OR gate 155 has two input terminals. An internal clock signal is input to one input terminal of the OR gate 155, and a signal output from the inverter 153 is input to the other input terminal. The OR gate 155 outputs a logical sum of the values of these signals to the NAND gate 156.

  The NAND gate 156 outputs a negative logical product of the input values. The NAND gate 156 includes three input terminals. A signal output from the NAND gate 154 is input to the first input terminal of the NAND gate 156, and a signal output from the OR gate 155 is input to the second input terminal. A mode signal MODE is input to the third input terminal of the NAND gate 156. NAND gate 156 outputs a negative logical product of the values of these signals to AND gate 123.

  The internal clock signal RDCLK is delayed by passing through the inverters 151 to 153 and its value is inverted. The signal output from inverter 153 is referred to as inverted delayed internal clock signal RDCLKd. The inverted delay internal clock signal is a signal obtained by inverting the internal clock signal three times. Therefore, the delay time due to the passage of the inverters 151 to 153 is the time from the rising edge of the internal clock signal to the falling edge of the inverted delay internal clock signal. Inverters 151 to 153 are selected so that the delay time is shorter than a half cycle of the internal clock signal.

  The NAND gate 154 generates a signal that is turned off only during the above-described delay time from the falling edge of the internal clock signal, based on the negative logical product of the values of the inverted delayed internal clock signal RDCLKd and the internal clock signal RDCLK. This signal is referred to as a rising trigger signal rise_OEN_trig.

  The OR gate 155 generates a signal that is turned off only during the above-described delay time from the fall of the internal clock signal, based on the logical sum of the values of the inverted delayed internal clock signal RDCLKd and the internal clock signal RDCLK. This signal is referred to as a falling trigger signal fall_OEN_trig.

  The NAND gate 156 outputs a negative logical product of values of the rising trigger signal rise_OEN_trig, the falling trigger signal fall_OEN_trig, and the mode signal. When the mode signal is in the “H” state, the signal output from the NAND gate 156 indicates that the delay time elapses from the rise of the internal clock signal and the delay time elapses from the fall of the internal clock signal. Turns on only for a while. When the mode signal is in the “L” state, the signal output from the NAND gate 156 is turned off. This signal is referred to as an output enable trigger signal OEN_trig.

  The AND gate 123 outputs a logical product of values of the output enable trigger signal OEN_trig and the read command signal “RD” as the output driver enable signal OEN. When the mode signal is in the “H” state, this output driver enable signal is used until the delay time elapses from the rise of the internal clock signal and until the delay time elapses from the fall of the internal clock signal in the data output period. This signal is turned on only during the interval. On the other hand, when the mode signal is in the “L” state, the output driver enable signal is turned on over the data output period.

[Operation of data output device]
Next, the operation of the data output device 114 will be described with reference to FIGS. FIG. 19 is a flowchart illustrating an example of a control procedure of the data output device 114 according to the fifth embodiment of the present invention. This control procedure starts when a mode signal in the “H” state is input to the data output device 114.

  The control circuit 150 determines whether or not the read command signal is in the “H” state (step S910). When the read command signal is in the “H” state (step S910: Yes), the control circuit 150 generates a latch enable signal that enables the latch circuit 180 (step S920). Further, the control circuit 150 generates a driver control signal that enables the output driver 170 during the delay time from the rising edge of the internal clock signal (step S941). Thereafter, the control circuit 150 generates a driver control signal that makes the output driver 170 in an invalid state, that is, a high impedance state (step S942). The control circuit 150 generates a driver control signal that enables the output driver 170 during the delay time from the falling edge of the internal clock signal (step S943). Thereafter, the control circuit 150 generates a driver control signal for setting the output driver 170 in a high impedance state (step S944).

  If the read command signal is not in the “H” state (step S910: Yes), the control circuit 150 generates a latch enable signal that disables the latch circuit 180 (step S950).

  After step S943 or S950, the control circuit 150 returns to step S910.

  Subsequently, an operation result of the data output device 114 will be described with reference to FIGS. 20 and 21. FIG. FIG. 20 is a timing chart illustrating an example of an operation result of the data output device 114 when the mode signal is in the “H” state according to the fifth embodiment of the present invention.

  The processor 200 generates a read command CMD and a mode signal MODE in the “H” state, and outputs them to the memory 100 in synchronization with the external clock signal CLK.

  The decoder 105 decodes the read command to generate a read command signal RD, and inputs the read command signal RD to the data output device 114 in synchronization with the internal clock signal.

  The internal clock generation unit 104 generates an internal clock signal RDCLK in which the external clock is delayed.

  As the inverters 151 to 153 pass, the internal clock signal RDCLK is delayed and inverted to generate an inverted delayed internal clock signal RDCLKd.

  The NAND gate 154 generates a rising trigger signal rise_OEN_trig that is turned off only between the rising edge of the internal clock signal and the delay time, based on the negative logical product of the values of the inverted delayed internal clock signal and the internal clock signal.

  The OR gate 155 generates a falling trigger signal fall_OEN_trig that is turned off only during the delay time from the falling edge of the internal clock signal, based on the logical sum of the values of the inverted delayed internal clock signal and the internal clock signal.

  The NAND gate 156 generates the output enable trigger signal OEN_trig based on the negative logical product of the rising trigger signal, the falling trigger signal, and the mode signal value. This output enable trigger signal is in the “H” state only between the time when the delay time elapses from the rise of the internal clock signal and the time when the delay time elapses after the fall of the internal clock signal.

  The AND gate 123 generates the output driver enable signal OEN based on the logical product of the values of the output enable trigger signal and the read command signal RD. In the data output period, the output driver enable signal is in the “H” state only between the time when the delay time elapses from the rise of the internal clock signal and the time when the delay time elapses after the fall of the internal clock signal.

  The AND gate 124 generates a latch enable signal LEN that enables the latch circuit 180 during the ON period of the read command signal.

  The memory cell array 106 in the memory 100 outputs the stored data to the control circuit 150 in response to the rising and falling edges of the internal clock signal.

  In accordance with the output driver enable signal OEN, the output driver 170 is in a valid state only between the time when the delay time elapses from the rising edge of the internal clock signal and the time after the delay time elapses after the falling edge of the internal clock signal. Outside this period, the state becomes invalid, that is, a high impedance state.

  The latch circuit 180 is enabled during the ON period of the read command signal according to the latch enable signal LEN. The latch circuit 180 is in an invalid state, that is, a high impedance state except for that period.

  As a result, the data output device 114 applies the potential by the output driver 170 only between the time when the delay time elapses from the rising edge of the internal clock signal and the time when the delay time elapses after the falling edge of the internal clock signal. Output data. In other periods, the data output device 114 outputs data by applying a potential by the latch circuit 180 until the data output period elapses.

  FIG. 21 is a timing chart showing an example of the operation result of the data processing system according to the first embodiment of the present invention.

  Assume that the processor 200 reads data from “# 1” in the memory 100 and then reads data from “# 2” in the memory 100 at a certain clock. Then, it is assumed that reading of data from the memory “# 1” is delayed.

  The processor 200 outputs a mode signal in the “H” state to the memories “# 1” and “# 2” before continuously reading data from the memories “# 1” and “# 2”. In the memory “# 1”, the output driver is enabled only during the delay time from the rising edge and during the delay time from the falling edge according to the procedure illustrated in FIG. The latch circuit is made valid until The memory “# 2” performs the same operation.

  Even if there is a slight delay in reading data from the storage element in the memory “# 1”, the output driver in the memory “# 2” is valid during this period because the output driver is in a valid state for a short period. Does not overlap with the period when Therefore, it is possible to prevent data collisions caused by a plurality of output drivers applying potentials simultaneously.

  Further, since the data output device 114 outputs data in response to the rising and falling edges of the internal clock signal, it can be mounted on a memory that uses the DDR method.

  As described above, the data output device 114 enables the output driver only between the rising edge and the delay time and between the falling edge and the delay time, and in other periods, the latch circuit is enabled until the data output period elapses. To the state. Therefore, it is possible to improve the data output speed while preventing data collision.

  In the fifth embodiment, the control circuit 150 delays the internal clock signal by passing a plurality of inverters. However, the control circuit 150 may delay the internal clock signal using a phase shift circuit, as illustrated in FIG.

  FIG. 22 is a circuit diagram showing a modification of the control circuit 150 in the sixth embodiment of the present invention. Control circuit 150 includes 90-degree phase shift circuit 157 instead of inverters 151 and 152.

  90 degree phase shift circuit 157 shifts the phase of internal clock signal RDCLK by 90 degrees and outputs the result to inverter 153. As a result, a control circuit that operates as illustrated in FIGS. 20 and 21 can be realized.

<6. Modification>
[Data output device configuration]
FIG. 23 is a circuit diagram showing a modification of the data output device 110 according to the first embodiment of the present invention. The data output device 110 includes a control circuit 160 instead of the control circuit 120. A mode signal is not input to the control circuit 160. Further, the control circuit 160 does not include the inverter 121, the NAND gate 122, and the AND gate 124.

  AND gate 123 outputs a logical product of the values of read command signal RD and internal clock signal RDCLK to NAND gate 126 and inverter 125. The read command signal is output to the latch circuit 180 as it is as a latch enable signal LEN.

  Even with such a simple configuration, the control circuit 160 enables the output driver 170 only during the drive period from the start of the data output period, and enables the latch circuit 180 only during the data output period. Can be.

  FIG. 24 is an overall view showing a modification of the data processing system according to the first embodiment of the present invention. In the configuration illustrated in FIG. 1, the memory 100 and the processor 200 are mounted in a plane, but may be mounted three-dimensionally as illustrated in FIG. 24.

  This data processing system includes a plurality of memories 101, a processor 201, and a plurality of TSVs 301 instead of the plurality of memories 100, the processors 200, and the data bus 300. Each memory 101 and the processor 201 are mounted three-dimensionally. The TSV 301 is an electrode that penetrates the memory 101 and the processor 201. Each memory 101 and the processor 201 are connected by a TSV 301 instead of the data bus 300.

  As described above, each memory can output data to a path other than the data bus 300 such as the TSV 301.

  The embodiment of the present invention shows an example for embodying the present invention. As clearly shown in the embodiment of the present invention, the matters in the embodiment of the present invention and the claims Each invention-specific matter in the scope has a corresponding relationship. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present invention having the same names as the claims have a corresponding relationship. However, the present invention is not limited to the embodiments, and can be embodied by making various modifications to the embodiments without departing from the gist of the present invention.

  The processing procedure described in the embodiment of the present invention may be regarded as a method having a series of these procedures, and a program for causing a computer to execute the series of procedures or a recording medium storing the program May be taken as As this recording medium, for example, a CD (Compact Disc), an MD (MiniDisc), a DVD (Digital Versatile Disk), a memory card, a Blu-ray Disc (registered trademark), or the like can be used.

100, 101 Memory 104 Internal clock generator 105 Decoder 106 Memory cell array 110, 111, 112, 114 Data output device 113 Data input / output device 120, 130, 140, 150, 160 Control circuit 121, 125, 132, 133, 151- 153, 181, 182, 186 Inverter 122, 126, 131, 154, 156 NAND gate 123, 124, 141 AND gate 127 NOR gate 155 OR gate 157 90 degree phase shift circuit 170 Output driver 171 pMOS
172 nMOS
180 Latch circuit 185 Input circuit 190 Output terminal 191 Input / output terminal 200, 201 Processor 210 Processing unit 220 Data input device 300 Data bus 301 TSV
401-406 Signal line C1, C2, L1 Signal line

Claims (12)

An output terminal;
An output driver that supplies a driver current having an absolute value of a predetermined value to the output terminal by applying a potential corresponding to the value of the input data to the output terminal;
A latch unit that holds a potential applied to the output terminal, and supplies a latch current that is smaller than the predetermined value to the output terminal by applying the held potential to the output terminal;
The data is input to the output driver only from the start of the data output period, which is a period in which the driver current or the latch current is to be supplied to the output terminal, until a drive period shorter than the data output period elapses. A data output device comprising: a control unit that stops the supply of the latch current to the latch unit when the data output period has elapsed. The control unit obtains a clock signal whose half of the clock period is the drive period, and determines whether the drive period has elapsed from the start time based on the clock signal, so that only the drive period The data output device according to claim 1, wherein the data is input to the output driver. The control unit generates an internal signal that is delayed by the drive period from the start time, and inputs data to the output driver only until a delay time of the internal signal elapses from the start time. Data output device. 2. The data output device according to claim 1, wherein the control unit supplies the latch current to the latch unit only during a period from the start time to a time when the data output period has elapsed. 2. The data output device according to claim 1, wherein the control unit causes the latch unit to supply the latch current only during a period from when the drive period elapses to when the data output period elapses. The control unit obtains a clock signal having a clock cycle shorter than the data output period and a half of the clock cycle being longer than the first drive period and the second drive period, and from the rising edge of the clock signal, 2. The data output device according to claim 1, wherein data is input to the output driver only until a drive period elapses and until a second drive period elapses after a fall of the clock signal. The controller is
A phase shift unit that generates a shift clock signal in which the phase of the clock signal is shifted by a predetermined period;
Data is input to the output driver only between the rising edge of the clock signal and the falling edge of the shift clock signal, and only from the falling edge of the clock signal to the falling edge of the shift clock signal, and The data output device according to claim 6, further comprising: an output control unit that stops supply of current to the latch unit when a data output period has elapsed. When a plurality of data output devices are connected to a path to which the output terminal is connected, the control unit inputs data to the output driver only from the start time until the drive period elapses, and When the data output period elapses, supply of current to the latch unit is stopped, and when one data output device is connected to the path, data is input to the output driver only during the data output period. The data output device according to claim 1, wherein the latch unit is invalidated. Input and output terminals;
An output driver that supplies the output terminal with a current whose absolute value is a predetermined value by applying a potential corresponding to the value of the data to the input / output terminal only while data is being input;
Holds the potential applied to the input / output terminal when a current based on the internal resistance at which the resistance value becomes the predetermined value is supplied to the input / output terminal, and applies the held potential to the output terminal A latch unit that supplies a current having an absolute value smaller than the predetermined value to the input / output terminal;
The data is input to the output driver only from the start of the data output period, which is a period in which a current corresponding to the data is to be supplied to the output terminal, until a drive period shorter than the data output period elapses. A data input / output device comprising: a control unit that stops supply of the latch current to the latch unit when the data output period has elapsed; and an input unit that generates data according to a potential applied to the input / output terminal . A storage element that stores data and outputs data to a data output device when data output is requested;
A requesting unit that requests the storage element to output the data;
An output terminal, an output driver for supplying a driver current having an absolute value to a predetermined value by applying a potential corresponding to a value of input data to the output terminal, and an output driver applied to the output terminal A latch unit that holds a potential and applies a latched potential to the output terminal by applying the held potential to the output terminal; and the driver current or the latch current The data output by the storage element is input to the output driver only from the start of the data output period, which is a period to be supplied to the output terminal, until the drive period shorter than the data output period elapses. Data comprising: a control unit that stops supply of the latch current to the latch unit when the data output period has elapsed Storage apparatus comprising a power device. An output terminal, an output driver for supplying a driver current having an absolute value to a predetermined value by applying a potential corresponding to a value of input data to the output terminal, and an output driver applied to the output terminal A latch unit that holds a potential and applies a latched potential to the output terminal by applying the held potential to the output terminal; and the driver current or the latch current The data is input to the output driver only from the start of the data output period, which is a period to be supplied to the output terminal, until the drive period shorter than the data output period elapses, and the data output period elapses. A plurality of data output devices comprising a control unit that sometimes stops the supply of the latch current to the latch unit;
A path connected to the output terminal of the plurality of data output devices;
A data processing system comprising: a processing device that generates and processes data corresponding to the potential applied to the path. This is a period in which a current to be supplied to the output terminal is supplied to an output driver that supplies a driver current whose absolute value becomes a predetermined value by applying a potential according to the value of the input data to the output terminal. An input procedure for inputting the data only from the start of the data output period until a drive period shorter than the data output period elapses;
A latch unit that holds a potential applied to the output terminal and supplies a latch current having an absolute value smaller than the predetermined value to the output terminal by applying the held potential to the output terminal. A control method for a data output device, comprising: a stop procedure for stopping supply of the latch current when a data output period has elapsed.

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