JP2005353870A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device with which a problem of washing in a copper wiring forming process using a low-k film can be solved. <P>SOLUTION: A copper wiring layer 2 is formed on a silicon substrate 1; and a diffusion preventing film 7, an interlayer insulating film 8, and a cap film 9 are then formed in order on the copper wiring layer 2. A hard mask 10 is then used to perform dry etching using plasma on the cap film 9, the interlayer insulating film 8, and the diffusion preventing film 7. An opening 11 is formed down to the copper wiring layer 2. At such a time, a residual electric charge 16 is generated inside the opening 11. Pure water wherein CO<SB>2</SB>is dissolved is then blown over the silicon substrate 1 in the state of rotating the silicon substrate 1. Ordinary washing treatment is performed thereafter, and a wiring layer is formed inside the opening 11. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a copper wiring layer is formed.

  In recent years, the speed of semiconductor devices has been remarkably increased, and transmission delay due to a decrease in signal propagation speed due to wiring resistance in a multilayer wiring portion and parasitic capacitance between wiring layers has become a problem. Such a problem tends to become more prominent because the wiring resistance increases and the parasitic capacitance increases as the wiring width and the wiring interval become finer due to higher integration of semiconductor devices.

  In order to prevent signal delay due to an increase in wiring resistance and parasitic capacitance, copper wiring has been introduced instead of aluminum wiring, and an insulating film having a low dielectric constant (hereinafter referred to as a low-k film) is used as an interlayer insulating film. Has been attempted.

  As a method for forming a copper wiring using a low-k film, there is a damascene method. This is known as a technique for forming a wiring without etching copper, considering that it is difficult to control the etching rate of copper compared to aluminum.

  Specifically, the damascene method is a method of forming a copper wiring layer by embedding a copper layer in the opening after forming an opening by dry etching the Low-k film. The copper layer is embedded by forming a copper film so that the opening is embedded by plating and then planarizing the surface using a CMP (Chemical Mechanical Polishing) method so that the copper film remains only in the opening. Can be realized.

  By the way, the substrate cleaning method performed in the manufacturing process of the semiconductor device includes a batch method for cleaning a plurality of substrates at once and a single wafer method for cleaning the substrates one by one. In recent years when the diameter of the substrate is increasing, a cleaning method using a sheet method tends to become mainstream.

  As a sheet-type cleaning device, a spin-type cleaning device is generally used. According to this apparatus, the cleaning is performed by sequentially supplying the chemical solution and the pure water onto the rotating substrate. Further, the substrate after cleaning is dried by blowing off the liquid adhering to the substrate by rotation.

However, when pure water is sprayed onto the substrate while rotating the substrate, a voltage is generated due to friction between the substrate and pure water. For this reason, there is a problem that the gate insulating film is deteriorated by injecting charges into the substrate, and the yield and reliability of the semiconductor device are lowered. For this, a method of reducing the specific resistivity of pure water by adding carbon dioxide (CO ₂ ) to pure water, a method of reducing friction between the surface of the substrate and pure water, and the like have been proposed. (For example, refer to Patent Document 1).

Japanese Patent Laid-Open No. 06-275591

  However, the substrate cleaning in the actual semiconductor device manufacturing process is often performed after a plasma processing process such as dry etching. In the plasma processing step, the substrate is exposed to plasma charged particles, so that charges remain on the surface of the substrate after the plasma processing. The amount of residual charge (hereinafter referred to as residual charge amount) varies depending on the density of the pattern formed on the surface of the substrate, and the residual charge amount becomes larger when the pattern density is low. For example, the residual charge amount is larger in the hole pattern than in the groove pattern, and in the isolated pattern than in the dense pattern.

  Normally, various patterns are formed on the surface of the substrate. However, if the substrate is cleaned in a state where patterns having different pattern densities are mixed, the residual charge has a distribution on the substrate surface. When the components in the chemical solution are affected by this residual charge, there is a problem that the substrate cleaning efficiency fluctuates locally. For example, there is a problem that a component contributing to cleaning is not supplied to the substrate surface due to the influence of residual charges, and a sufficient cleaning effect cannot be obtained. In addition, since the component contributing to cleaning is affected by the residual charge, the chemical reaction on the substrate surface is accelerated, and the surface layer of the substrate is abnormally etched. In particular, in the copper wiring process by the damascene method, if the latter abnormal etching occurs in the cleaning performed after the opening is formed in the low-k film, the yield is significantly reduced, so that an immediate solution has been demanded.

  The present invention has been made in view of such problems. That is, an object of the present invention is to provide a method of manufacturing a semiconductor device that can solve the problem of cleaning in a copper wiring forming process using a low-k film.

  Other objects and advantages of the present invention will become apparent from the following description.

  The present invention relates to a method for manufacturing a semiconductor device having a multilayer wiring structure, a step of forming a copper wiring layer on a semiconductor substrate, a step of forming a diffusion prevention film on the copper wiring layer, and the diffusion Forming an interlayer insulating film on the prevention film; forming a cap film on the interlayer insulating film; forming a hard mask having a predetermined pattern on the cap film; Using a hard mask, the step of performing dry etching with plasma on the cap film, the interlayer insulating film, and the diffusion prevention film in order to form an opening that reaches the copper wiring layer, and opening the semiconductor substrate while rotating the semiconductor substrate A step of spraying a solution containing a substance having a polarity opposite to the polarity of the surface charge in the portion onto the semiconductor substrate, a step of performing a chemical treatment on the semiconductor substrate, and using pure water on the semiconductor substrate after the chemical treatment. And performing water washing treatment and is characterized by comprising a step of performing a drying treatment to remove the pure water attached to the semiconductor substrate, and forming a wiring layer inside the opening.

  The present invention can further include a step of measuring the surface potential of the semiconductor substrate after forming the opening. In this case, the step of spraying the solution onto the semiconductor substrate is performed in a state in which the semiconductor substrate is rotated at a rotation speed that generates a potential having the same absolute value as that of the measured surface potential but having the opposite polarity.

  In the present invention, the solution sprayed onto the semiconductor substrate can be pure water in which carbon dioxide is dissolved.

  In the present invention, the interlayer insulating film is preferably a low dielectric constant insulating film having a relative dielectric constant of 3.0 or less.

  According to the present invention, since the semiconductor substrate is rotated and the cleaning process is performed after the solution containing the substance having the opposite polarity to the surface charge in the opening is sprayed on the semiconductor substrate, the residual charge generated by the plasma Can be removed or reduced. Therefore, it is possible to eliminate the problem of abnormal etching of the copper wiring layer that occurs in the cleaning process due to the residual charge, and to manufacture a semiconductor device having excellent reliability with a high yield.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that a normal LSI manufacturing process such as MOS transistor, diffusion layer, and plug formation will be omitted for the sake of convenience, and the metal wiring forming process will be described.

  1 to 6 and 8 are cross-sectional views showing a method for manufacturing a semiconductor device in the present embodiment. In these drawings, the same reference numerals indicate the same parts.

  First, a lower copper wiring layer 2 is formed on a silicon substrate 1 as a semiconductor substrate (FIG. 1).

  Specifically, the first diffusion barrier film 3 and the first interlayer insulating film 4 are sequentially stacked on the silicon substrate 1, and then the opening reaching the first diffusion barrier film 3 in the first interlayer insulating film 4. The copper wiring layer 2 can be formed by providing a portion and embedding the first copper layer 6 in the opening via the first barrier metal film 5.

  Next, the second diffusion prevention film 7, the second interlayer insulation film 8, and the cap film 9 are laminated in this order on the first interlayer insulation film 4 on which the copper wiring layer 2 is formed (FIG. 2).

In the present embodiment, as the first interlayer insulating film 4 and the second interlayer insulating film 8, it is preferable to use an insulating film (Low-k film) having a relative dielectric constant lower than that of the SiO ₂ film. It is preferable to use an insulating film having a rate of 3.0 or less. As long as it is such a film, the first interlayer insulating film 4 and the second interlayer insulating film 8 may be films formed by any method. For example, a porous insulating film having pores (pores) in the film or an insulating film having no pores may be used. Furthermore, there are no particular restrictions on the size of holes or the density of holes when holes are provided. Specifically, in addition to inorganic insulating films such as SiO ₂ , SiOC, HSQ (hydrogen silsesquioxane), MSQ (methyl silsesquioxane), porous HSQ, and porous MSQ, fluorine An organic polymer insulating film containing can also be used. The first interlayer insulating film 4 and the second interlayer insulating film 8 may be films made of the same material or films made of different materials.

On the other hand, as the first diffusion preventing film 3, the second diffusion preventing film 7 and the cap film 9, for example, a SiO ₂ -based, SiN-based, SiC-based or AlO-based inorganic insulating film can be used. However, like the interlayer insulating film, the first diffusion preventing film 3, the second diffusion preventing film 7, and the cap film 9 are preferably insulating films having a relative dielectric constant as low as possible. As long as it has such characteristics, there is no particular limitation on the film quality, film thickness, formation method, and the like of these films. When a material having a relatively high relative dielectric constant is used, it is preferable that the material be formed as thin as possible so as not to impair the characteristics of the film.

  After the cap film 9 is formed, a hard mask 10 having a predetermined pattern is formed by using a photolithography method (FIG. 3). As the hard mask 10, a film made of a material having a high etching selectivity with the cap film 9 is used.

  Next, dry etching using plasma is sequentially performed on the cap film 9, the second interlayer insulating film 8, and the second diffusion prevention film 7 using the hard mask 10 as a mask. Thereby, as shown in FIG. 4, the 2nd opening part 11 which reaches the copper wiring layer 2 can be formed. Here, the first copper layer 6 is exposed from the second opening 11. Then, along with the formation of the opening 11, the contaminant 12 generated by etching adheres on the copper wiring layer 2 (FIG. 4). The contaminant 12 is mainly composed of a substance generated by a reaction between plasma active species and copper.

  Further, by performing dry etching, residual charges 16 are generated inside the openings 11 (FIG. 4). If the cleaning process for removing the contaminant 12 is performed in this state, the copper wiring layer 2 is abnormally etched in this portion. That is, the cleaning treatment process includes a chemical treatment, a water washing treatment, and a drying treatment. The chemical used for the chemical treatment includes a component that etches the copper wiring layer. In normal cleaning, the copper wiring layer is not locally etched abnormally, but when this component is activated locally due to the influence of residual charge, the copper wiring layer in the activated portion The chemical reaction is promoted, and the copper wiring layer is abnormally etched.

  As a result of earnest research, the present inventor believes that in order to prevent abnormal etching of the copper wiring layer due to the residual charge, it is necessary to remove or reduce the residual charge before the cleaning treatment process. It came. That is, since the residual charge generated after the plasma treatment has a positive polarity, the residual charge can be canceled by generating a charge having the opposite negative polarity.

Specifically, a solution containing a substance having a polarity opposite to the polarity of the surface charge in the opening may be sprayed on the semiconductor substrate while the semiconductor substrate is rotated. For example, a substrate is placed in a single-type cleaning apparatus, and pure water in which CO ₂ gas is dissolved is sprayed on the surface of the substrate while rotating the substrate. As a result, negative charges are generated on the surface of the substrate. Accordingly, the residual charge having a positive polarity can be canceled out, so that the residual charge on the substrate surface can be removed or reduced.

  After spraying an appropriate amount of the above solution, the substrate is rotated to blow off the solution remaining on the surface. As a result, the surface of the substrate is dried, and the residual charge removing step is completed.

FIG. 5 shows the relationship between the rotation speed of the substrate when pure water in which CO ₂ gas is dissolved and the accumulated charge on the substrate surface. From the figure, it can be seen that by spraying pure water in which CO ₂ gas is dissolved on the substrate, a negative potential is generated on the surface of the substrate, and the absolute value of the surface potential increases as the number of rotations of the substrate increases. . For this reason, in the present invention, after the dry etching for forming the opening is finished, the surface potential of the substrate is measured, and a potential having the same absolute value as that of the surface potential but of the opposite polarity is generated. Set the rotation speed. Then, it is preferable that pure water in which CO ₂ gas is dissolved is sprayed onto the substrate while the substrate is rotated at this rotational speed. By doing so, the residual charge can be substantially removed.

Although FIG. 5 shows an example in which pure water in which CO ₂ gas is dissolved is sprayed on the substrate, the same applies to the case where other solutions are used. That is, the potential generated when a solution containing a substance having a polarity opposite to the polarity of the surface charge in the opening is sprayed on the substrate changes depending on the number of rotations of the substrate. Therefore, if the surface potential of the substrate is measured in advance, residual charges can be substantially removed by setting the number of revolutions that generates a potential of the opposite polarity that is substantially the same as the surface potential. It becomes possible.

  In addition, the potential generated on the surface of the substrate varies depending not only on the rotation speed of the substrate described above but also on the structure of the cleaning apparatus. Therefore, it is more preferable to optimize the rotational speed in accordance with the cleaning device to be used.

  After performing the residual charge removal step, a normal cleaning step is performed for the purpose of removing the contaminants 12 attached to the surface of the copper wiring layer 2. Specifically, a water washing process is performed after a chemical solution process, and finally a drying process is performed.

  The chemical used for the chemical treatment needs to be capable of peeling and removing the contaminant 12 and not causing substantial damage to the copper wiring layer 2 and the second interlayer insulating film 8. However, the chemical solution is not particularly limited in its components and composition as long as it has such characteristics. As a chemical solution suitable for the present embodiment, for example, one containing fluorine (F) can be given.

  The chemical treatment can be performed by a sheet type method in which a chemical solution is sprayed onto a substrate in a rotating state to wash the substrates one by one. However, this invention is not limited to this, For example, you may carry out by the batch system which immerses a several board | substrate in a chemical | medical solution.

  After the chemical liquid treatment is completed, the chemical liquid is washed away by washing with pure water, and the remaining contaminants 12 are completely removed. The water washing process may be performed by either a single wafer system or a batch system. For example, when performing the cleaning process by a single wafer system, the water washing is rotated with respect to the substrate after chemical treatment. It can be performed by spraying pure water in a state.

  After the chemical solution adhering to the substrate is completely replaced with pure water, a drying process for removing the pure water is performed. For example, it can be performed by blowing off the liquid adhering to the substrate by rotation. It can also be performed by spraying an inert gas or clean air on the substrate, or replacing the attached liquid with isopropyl alcohol (IPA) liquid or its vapor.

  According to the present embodiment, since the cleaning process is performed after the residual charges 16 are removed or reduced, the copper wiring layer 2 is adhered to the surface of the copper wiring layer 2 while preventing the copper wiring layer 2 from being abnormally etched locally. The contaminated material 12 can be removed to obtain a state as shown in FIG.

  After the cleaning process is completed as described above, a second barrier metal film 13 such as a tantalum nitride (TaN) film is formed on the inner surface of the opening 11 in FIG. Thereafter, the copper layer 14 is embedded in the opening 11 via the second barrier metal film 13. Thereby, the copper wiring layer 15 can be formed in the upper layer of the lower copper wiring layer 2 (FIG. 7). Specifically, after forming a copper film (not shown) as seed copper by a sputtering method, the second copper layer 14 is formed so as to bury the opening 11 using a plating method. Next, the surface is planarized using a CMP (Chemical Mechanical Polishing) method so that the second copper layer 14 remains only in the opening 11. Thereby, the copper wiring layer 15 electrically connected to the copper wiring layer 2 can be formed.

  According to the present invention, residual charges generated by plasma processing can be removed or reduced. Therefore, it is possible to eliminate the problem of abnormal etching of the copper wiring layer that occurs in the cleaning process due to the residual charge, and to manufacture a semiconductor device having excellent reliability with a high yield.

  In the above embodiment, the residual charge generated by the dry etching process has been described, but the present invention is not limited to this. The present invention is suitable for all residual charges generated by plasma treatment. For example, the present invention can be applied to the case where the cleaning process is performed after the ashing process.

It is sectional drawing which shows the manufacturing process of the semiconductor device in this Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device in this Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device in this Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device in this Embodiment. It is a figure which shows the relationship between the rotational speed of a board | substrate, and the electric charge which generate | occur | produces on the substrate surface. It is sectional drawing which shows the manufacturing process of the semiconductor device in this Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device in this Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2,15 Copper wiring layer 3 1st diffusion prevention film 4 1st interlayer insulation film 5 1st barrier metal film 6 1st copper layer 7 2nd diffusion prevention film 8 2nd interlayer insulation film 9 Cap film 10 Hard mask 11, 28 Opening 12 Contaminant 13 Second barrier metal film 14 Second copper layer 16 Residual charge

Claims (4)

A method of manufacturing a semiconductor device having a multilayer wiring structure,
Forming a copper wiring layer on the semiconductor substrate;
Forming a diffusion barrier film on the copper wiring layer;
Forming an interlayer insulating film on the diffusion barrier film;
Forming a cap film on the interlayer insulating film;
Forming a hard mask having a predetermined pattern on the cap film;
Using the hard mask, sequentially performing dry etching with plasma on the cap film, the interlayer insulating film and the diffusion prevention film, and forming an opening reaching the copper wiring layer;
Spraying a solution containing a substance having a polarity opposite to the polarity of the surface charge in the opening in a state where the semiconductor substrate is rotated;
Performing a chemical treatment on the semiconductor substrate;
Performing a water washing process using pure water on the semiconductor substrate after the chemical treatment;
Performing a drying process to remove the pure water adhering to the semiconductor substrate;
And a step of forming a wiring layer inside the opening. After forming the opening, further comprising measuring a surface potential of the semiconductor substrate;
2. The semiconductor device according to claim 1, wherein the step of spraying the solution onto the semiconductor substrate is performed in a state in which the semiconductor substrate is rotated at a rotational speed that generates a potential having a polarity that is substantially the same as the surface potential and opposite in polarity. Manufacturing method.   The method for manufacturing a semiconductor device according to claim 1, wherein the solution is pure water in which carbon dioxide is dissolved.   The method for manufacturing a semiconductor device according to claim 1, wherein the interlayer insulating film is a low dielectric constant insulating film having a relative dielectric constant of 3.0 or less.

Images