JP2005341149A - Differential amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a differential amplifier circuit operable at a low voltage (about 1.0 V).
The common mode output voltage is extracted from the NMOS transistors Q1 and Q2 of the amplifier circuit constituting the differential pair and supplied to an error detection circuit (op-amp OP1) 12 to which a reference voltage _VREF is supplied. Is output as an error signal and negatively fed back to the gates of the NMOS transistors Q1 and Q2 of the differential amplifier circuit via the resistors R3 and R4 so that the drain voltages of the NMOS transistors Q1 and Q2 are the same as the reference voltage _VREF. Control as follows.
[Selection] Figure 1

Description

  The present invention relates to a differential amplifier circuit of an output DC voltage feedback type, and in particular, the gate of a differential pair of NMOS transistors is connected by a negative feedback circuit so that the common mode DC voltage of the output of the differential amplifier circuit is constant. The present invention relates to a differential amplifier circuit that is controlled so that a predetermined gain can be obtained even if the characteristics of NMOS transistors vary.

FIG. 3 shows a general configuration of a conventional differential amplifier circuit. In FIG. 3, input signals IN and INX are input to input terminals T1 and T2, and a constant current is supplied from a constant current source to terminal T3. CUR is supplied, and output signals OUT and OUTX are output from the output terminals T4 and T5. The gates of NMOSFET Q1 (hereinafter referred to as NMOS transistor Q1) and NMOS transistor Q2 are connected between input terminals T1 and T2, the sources of both NMOS transistors Q1 and Q2 are connected in common, and their drains are connected to load resistors R1 and R2, respectively. To the positive electrode of the power supply voltage V1 and to the output terminals T4 and T5. The sources of the NMOS transistors Q1 and Q2 constituting the differential pair are connected to the drain of the NMOS transistor Q4 of the NMOS transistors Q3 and Q4 constituting the current mirror circuit, the source is connected to the negative electrode of the power supply voltage V1, and the gate Is connected to the gate of the NMOS transistor Q3 and a terminal T3 connected to the constant current source.
It is known that the drain of the NMOS transistor Q3 constituting the current mirror circuit is connected to the gate and the terminal T3, and the source of the NMOS transistor Q3 is connected to the negative electrode of the power supply voltage V1.

  Further, as shown in FIG. 4, the source of the NMOS transistors Q1 and Q2 connected in common is connected to the negative electrode of the power supply voltage V1 through the resistor R6, and the drain of the NMOS transistor Q3 connected to the terminal T3. The gates are connected to the gates of the differential pair of NMOS transistors Q1 and Q2 via resistors R3 and R4, the NMOS transistor Q4 in FIG. 3 is changed to a resistor R6, and the NMOS transistors Q1 and Q2 are connected via resistors R3 and R4. There is also known one in which the gate is biased from the NMOS transistor Q3 as a current source.

  Generally, the circuit connected to the source for determining the bias current of the differential amplifier circuit uses a current source composed of NMOS transistors Q3 and Q4 as shown in FIG. 3, but a low voltage circuit having a power supply voltage V1 of about 1V. Since the drain-source voltage Vds of the NMOS transistors Q3 and Q4 of the current source is reduced and the constant current operation is difficult because the transition is made from the saturation region to the linear region, the bias current is determined by the resistor R6 as shown in FIG. I have to take the configuration to do. Therefore, as shown in FIG. 4, since the current value Ib of the differential amplifier circuit (NMOS transistors Q1, Q2) is determined using the NMOS transistors Q1, Q2, Q3 constituting the current mirror circuit, the current mirror circuit In order to improve the accuracy of the current ratio, the gate-source voltage Vgs is increased, or the threshold voltage ΔVth is decreased by increasing √WL of the gate width W and the gate length L. However, with such a configuration, the current of about 1/5 of the differential amplifier circuit (Q1, Q2) must be supplied to the NMOS transistor Q3 which is not involved in the amplification of the current mirror circuit, and therefore it is not suitable for low power consumption. was there. Furthermore, in order to improve the relative accuracy of the NMOS transistor, when the gate size (W, L) is increased, there is a problem that the parasitic capacitance increases and obstructs the high-speed operation of the differential amplifier circuit.

  Further, as shown in FIG. 5, a differential amplifier circuit in which a voltage obtained by comparing the midpoint potential of the bipolar transistor with the reference voltage of the comparator circuit is fed back to the base of the constant current source transistor connected to the emitter of the differential amplifier circuit. Is disclosed in Patent Document 1.

FIG. 5 shows the configuration of the above-mentioned Patent Document 1. In FIG. 5, T1 and T2 are input terminals, and input signals IN and INX are inputted. Output signals OUT and OUTX are output from the output terminals of T4 and T5. The bases of bipolar NPN transistors Tr1 and Tr2 are connected between the input terminals T1 and T2, the emitters of both bipolar NPN transistors Tr1 and Tr2 are connected in common, and the respective collectors are connected via load resistors R1 and R2. Are connected to the positive electrode of the power supply voltage V1 and to the output terminals T4 and T5. The emitters of the bipolar NPN transistors Tr1 and Tr2 constituting the differential pair are connected to the collector of the bipolar NPN transistor Tr4 constituting the current source, and the emitters are connected to the power supply voltage V1 via the resistor R10 and to the ground. Series resistors R7 and R8 are connected between the collectors of the bipolar NPN transistors Tr1 and Tr2 constituting the differential pair, and the midpoint voltage is extracted from the midpoint A of the series connection, and the non-inverting terminal (+) of the operational amplifier OP1. 3 and the inverting terminal (−) 2 is supplied with a reference voltage from the reference power source V2, and the output 1 of the operational amplifier OP1 is negatively applied to the differential amplifier circuit NPN transistors Tri and Tr2 via the base of the bipolar NPN transistor Tr4. It has been returned.
Japanese Unexamined Patent Publication No. 63-185208 (FIG. 1)

  As shown in FIG. 3, a constant current Ib is supplied from a current source to the NMOS transistors Q1 and Q2 of the differential pair to obtain a constant gain gm by a conventional general differential amplifier circuit. The gain gm is determined by the load resistors R1 and R2 disposed between the drain of the amplifier circuit and the power supply voltage V1.

  However, when using NMOS transistors Q3 and Q4 for the current source as shown in FIG. 3, when the voltage of the power supply voltage V1 of the differential amplifier circuit is lowered to about 0.7V to 1V, the NMOS transistor constituting the current source The drain-source voltage Vds of Q3 and Q4 is reduced to 0.1 to 0.2V. This is because the NMOS transistors Q3 and Q4 are switched from the saturation region to the linear region. For this reason, there has been a problem that it is difficult to perform a constant current operation by the NMOS transistors Q3 and Q4.

  Therefore, as shown in FIG. 4, a structure in which the bias current is determined by the resistor R6 must be taken. Therefore, in the conventional example, as shown in FIG. 4, the current value Ib of the differential amplifier circuit (NMOS transistors Q1, Q2) is determined using a current mirror circuit (NMOS transistors Q1, Q2, Q3).

However, in order to increase the accuracy of the current ratio of the current mirror circuit in the differential amplifier circuit as shown in FIG. 4, (a) the gate-source voltage Vgs of the NMOS transistor Q3 is increased.
(B) The gate length L and the gate width W of the NMOS transistor Q3 are increased to reduce the threshold voltage Vth.
(C) Low power consumption due to the fact that it is necessary to pass a current Ic of about 1/5 of the bias current Ib of the NMOS transistors Q1 and Q2 of the differential amplifier circuit to the NMOS transistor Q3 constituting the current mirror circuit. There was an unsuitable problem.

  Furthermore, when the gate length L and the gate width W are increased in order to improve the relative accuracy of the NMOS transistor, the parasitic capacitance is increased, which hinders the speeding up of the differential amplifier circuit.

  Further, as shown in FIG. 5, the differential amplifier circuit of Patent Document 1 has a base of a bipolar NPN transistor Tr4 that is a current source connected to a commonly connected emitter of the bipolar NPN transistors Tr1 and Tr2. The differential amplifier circuit is feedback controlled by supplying a comparison output comparing the midpoint potential and the reference value, but since the NPN transistor Tr4 is used for the current source, the collector-emitter voltage is below the saturation voltage. Since the NPN transistor Tr4 does not operate normally, a bias that generates a voltage of at least about 0.3V is required. Therefore, the emitter voltages of the NPN transistors Tr1 and Tr2 constituting the differential pair are as high as about 0.5V. Had a problem.

  The present invention has been made to solve the above-mentioned problems, and a high-frequency IC for wireless communication that operates on a battery such as a mobile phone operates with low power consumption in order to extend the communication time. Things are required. An object of the present invention is to provide an amplifier circuit that realizes low power supply voltage operation of a differential amplifier circuit used in such a high-frequency IC and achieves low power consumption.

  A first differential amplifier circuit according to the present invention includes a differential pair of NMOS transistors whose sources are coupled to each other, a resistor connected between the source and ground of the differential pair of NMOS transistors, and a differential pair of the NMOS transistors. A load resistor connected between the drain of the pair and the power source, a resistor and a capacitor for connecting the drains provided to determine the midpoint of the drain DC voltage of the differential pair of the NMOS transistor, and a DC voltage generated in the capacitor And an error detection circuit to which a reference voltage is input, and the output of the error detection circuit is connected to the gate of the differential pair of the NMOS transistor so that the reference voltage and the DC voltage of the drain are the same. Is configured to control the voltage of the.

  According to a second differential amplifier circuit of the present invention, in the first invention, the error detection circuit is configured by a folded type circuit including a differential input of an NMOS transistor and a PMOS transistor.

  According to the first aspect of the present invention, it is possible to realize an amplifier circuit that operates with a source voltage of the amplifier circuits Q1 and Q2 of the differential pair as low as about 0.2V, and an output load resistor R1 of the differential amplifier circuit. , R2 can be maintained at a constant value, so that an amplifier circuit that operates with a set gain can be realized even if the characteristics (Vth) of the MOS transistors Q1, Q2 vary. Further, since the current required for the NMOS transistors Q3 and Q4 of the bias circuit can be reduced, there is an advantage that the power consumption of the differential amplifier circuit can be reduced. Furthermore, according to the second aspect of the present invention, a high frequency IC that can be entirely composed of MOSFETs can be produced by a simple process.

  Hereinafter, one embodiment of the differential amplifier circuit of the present invention will be described in detail with reference to FIG. FIG. 1 is a circuit diagram of a differential amplifier circuit according to the present invention. 1 corresponding to the differential input / differential output type amplifier circuit shown in FIG. 3 and FIG.

  In FIG. 1, input signals IN and INX are supplied to input terminals T1 and T2, constant current CUR is supplied from a constant current source to terminal T3, and output signals OUT and OUTX are output from output terminals T4 and T5. The Between the input terminals T1 and T2, the gates of the NMOS transistor Q1 and the NMOS transistor Q2 are connected, and the sources of both the NMOS transistors Q1 and Q2 are connected in common. The respective drains are connected to the positive electrode of the power supply voltage V1 via the load resistors R1 and R2 and to the output terminals T4 and T5. A series circuit of resistors R7 and R8 is connected between the output terminals T4 and T5, and a capacitor C1 is connected between the series connection middle point A of the resistors R7 and R8 and the positive electrode of the power supply voltage V1. The midpoint voltage output from the series connection midpoint A of the resistors R7 and R8 is supplied to the non-inverting terminal (+) 3 of the operational amplifier OP1 that constitutes the error detection circuit. The output terminal 1 of the operational amplifier OP1 is connected to the gates of the NMOS transistors Q1 and Q2 constituting the amplifier circuit of the differential pair via resistors R3 and R4, and the source is connected to the negative electrode of the power supply voltage V1 via the resistor R6. ing.

  The gates of the NMOS transistors Q3 and Q4 constituting the current mirror circuit are connected to each other and connected to the terminal T3, the terminal T3 is connected to the drain of the NMOS transistor Q3, and the source is connected to the negative electrode of the power supply voltage V1. . The drain of the NMOS transistor Q4 is connected to the positive electrode of the power supply voltage V1 via the resistor 9 and is connected to the inverting terminal (−) 2 of the operational amplifier OP1, and the source is connected to the negative electrode of the power supply voltage V1.

The operation of the differential amplifier circuit of the present invention in the above circuit configuration will be described below.
In FIG. 1, the present invention is a differential amplifier circuit having a bias circuit by common mode voltage feedback. A signal is input in a balanced mode from inputs IN and INX to an amplifier circuit composed of a differential pair NMOS transistor Q1 and NMOS transistor Q2, and the output is obtained as OUT and OUTX. The gain of this differential amplifier circuit is represented by the product of gm and load resistance (R7, R8). gm is a product of the bias current Ib of the differential amplifier circuit and β defined by Equation (3), and is determined by the following equation (1). Therefore, in order to keep gm constant, the current should be a constant value. A bias circuit must be used.

上式（１）はＭＯＳＦＥＴの静特性を表す下記の（２）式及び（３）式より求めたものである。

The above equation (1) is obtained from the following equations (2) and (3) representing the static characteristics of the MOSFET.

上式（２）（３）で
Ｉｄｓ＝ドレイン電流
μ＝移動度
Ｃｏｘ＝酸化膜厚
Ｗ＝ゲート幅
Ｌ＝ゲート長
Ｖｇｓ＝ゲートソース間電圧
Ｖｔ＝閾値
である。

In the above expressions (2) and (3), Ids = drain current μ = mobility Cox = oxide film thickness W = gate width L = gate length Vgs = gate-source voltage Vt = threshold.

  In the present invention, the input signals IN and INX supplied to the input terminals T1 and T2 of the NMOS transistors Q1 and Q2 constituting the differential pair are amplified from the output terminals T4 and T5 without using a current mirror circuit as shown in FIG. When outputting the output signals OUT and OUTX, the common mode midpoint potential A accumulated in the capacitor C1 by the resistors R7 and R8 and the capacitor C1 is supplied to the non-inverting terminal 3 of the error detection circuit (op-amp) OP1. The inverting terminal (−) 2 of the operational amplifier OP1 is supplied with the reference voltage supplied with the constant current supplied from the constant current source to the terminal T3 to the NMOS transistors Q3 and Q4 constituting the bias circuit, and the output terminal of the operational amplifier OP1. Reference numeral 1 denotes a negative feedback through the resistors R3 and R4 to the gates of the NMOS transistors Q1 and Q2 for the amplifier circuit constituting the differential pair. The drain voltage and the reference voltage of the NMOS transistors Q1 and Q2 by being is controlled to become the same.

  Since the present invention is configured and operated as described above, a current mirror circuit that requires extra power is not required to obtain high current ratio accuracy as in the conventional configuration shown in FIG. It is possible to construct an amplifier circuit that can be driven with low power consumption. As the power supply voltage is increased, the drain-source voltage Vds of the NMOS transistors Q1 and Q2 of the amplifier circuit constituting the differential pair also increases and the drain-source current Ids also increases. Since negative feedback is applied so as to make the voltage drop of the resistors R7 and R8 constant, a constant bias current Ib can be supplied to the amplifier circuit without being affected by the rise of the drain-source voltage Vds. . Further, compared with the collector-emitter voltage (0.5V) of the bipolar NPN transistor Tr4 shown in FIG. 5, the present invention can reduce the source voltage (0.2V) of the NMOS transistors Q1 and Q2 to a low voltage operation of the circuit. It becomes possible.

  Next, referring to FIG. 2, the error detection circuit constituted by the operational amplifier OP1 shown in FIG. 1 is all constituted by MOSFETs to simplify the man-hours when constructing the IC, and the error detection circuit can be realized with a low voltage of about 1V. An operable circuit configuration will be described.

  In FIG. 2, the differential amplifier circuit 10 and the bias and power supply circuit 11 indicated by the alternate long and short dash line are the same as those shown in FIG.

  In FIG. 2, the error detection circuit 12 constituting the common mode negative feedback circuit is shown within a broken line.

  In the error detection circuit 12 shown in FIG. 2, the common mode midpoint potential A stored in the capacitor C1 is applied to the gate of the NMOS transistor Q6 corresponding to the non-inverting terminal (+) 2 of the operational amplifier OP1 shown in FIG. The reference voltage from the bias constant current source (Q3, Q4) is supplied to the gate of the NMOS transistor Q5 corresponding to the inverting terminal (−) 3 via the drain of the NMOS transistor Q4 of the bias circuit 11. Yes. The error voltage of the error detection circuit 12 taken out from the connection point between the drain of the NMOS transistor Q11 and the drain of the PMOS transistor Q10 indicated by 1 at the output terminal of the operational amplifier OP1 is an NMOS constituting a differential pair of the differential amplifier circuit 10. Negative feedback is provided to the gates of the transistors Q1 and Q2 via resistors R3 and R4.

  The sources of the NMOS transistors Q5 and Q6 are commonly connected to each other, and the drain of the NMOS transistor Q7 is connected to the commonly connected source. The source of the NMOS transistor Q7 is connected to the negative electrode (ground) of the power supply voltage V1, and the gate is connected to the gate of the NMOS transistor Q9 described later, the gates of the NMOS transistors Q4 and Q3 of the bias circuit 11, and the terminal T3.

  The drains of the NMOS transistors Q5 and Q6 in the differential pair configuration are connected to the positive electrode of the power supply voltage V1 via the resistors R11 and R12 and to the sources of the folding PMOS transistors Q10 and Q12.

  The source of the NMOS transistor Q9 connected to the gate of the NMOS transistor Q4 of the bias circuit 11 is grounded to the ground potential, and the drain is connected to the drain of the PMOS transistor Q8. The source of the PMOS transistor Q8 is connected to the positive electrode of the power supply voltage V1 via the resistor R13, and the source and gate are connected in common.

  The drains of the folding PMOS transistors Q10 and Q12 are connected to the drains of the current source NMOS transistors Q11 and Q13, the sources of the NMOS transistors Q11 and Q13 are connected to the ground, and the gates of the NMOS transistors Q11 and Q13 are connected in common. The commonly connected gate is connected to the drain of the NMOS transistor Q13. Further, the gates of the PMOS transistors Q8, Q10, Q11 are connected in common.

The operation of the error detection circuit 12 with the above configuration will be described. The midpoint potential A supplied to the non-inverting terminal 2 and the inverting terminal 3 of the NMOS transistors Q5 and Q6 constituting the differential pair and the reference voltage V _REF supplied from the NMOS transistors Q3 and Q4 for current source of the bias circuit are: Error signals I1 and I2 with respect to the DC voltage at the midpoint potential are turned back at the turning-back PMOS transistors Q10 and Q12 and taken out from the output terminal 1, and the gates of the NMOS transistors Q1 and Q2 of the differential amplifier circuit By negative feedback, the drain voltage of the NMOS transistors Q1 and Q2 and the reference voltage _VREF are controlled so as to be always constant.

  The NPN transistors Q3, Q4, Q7, Q9 and Q11, Q13 are transistors constituting a current source, and the PMOS Q8 is a folding transistor.

  2, for example, when the power supply voltage V1 is 1V, the source voltage of the NMOS transistors Q5 and Q6 is 0.2V, the gate voltage of the NMOS transistor Q6 is 0.9V, and the folding PMOS transistors Q10 and Q12. Gate voltage = 0.2V, the source voltage of the PMOS transistors Q10, Q12 is about 0.9V, and a differential amplifier circuit can be obtained which can be configured by only a MOSFET which can operate the power supply voltage V1 at a low voltage of 1V. Therefore, as shown in FIG. 5, an amplifier circuit which can be mixed with logic without using a bipolar transistor is obtained.

It is a circuit diagram which shows one example of the differential amplifier circuit of this invention. It is a circuit diagram which shows the other form example which comprised MOSFET as the operational amplifier of the differential amplifier circuit of this invention. It is a circuit diagram which shows the conventional differential amplifier circuit. It is another circuit diagram which shows the conventional differential amplifier circuit. FIG. 10 is still another circuit diagram showing a conventional differential amplifier circuit.

Explanation of symbols

  Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q9, Q11, Q13 ... NMOS transistor, Q8, Q10, Q12 ... PMOS transistor, OP1 ... operational amplifier, 10 ... differential amplifier circuit, 11 ... Bias and power supply circuit, 12 ... Error detection circuit

Claims (2)

A differential pair of NMOS transistors with sources coupled together;
A resistor connected between the source of the differential pair of the NMOS transistor and the ground;
A load resistor connected between the drain of each differential pair of the NMOS transistor and the power supply;
A resistor and a capacitor for connecting the drains provided to determine the midpoint of the drain DC voltage of the differential pair of the NMOS transistor;
An error detection circuit to which a DC voltage generated in the capacitor and a reference voltage are input;
The output of the error detection circuit is connected to the gate of the differential pair of the NMOS transistor, and the gate voltage is controlled so that the reference voltage and the DC voltage of the drain are the same. Differential amplifier circuit.   2. The differential amplifier circuit according to claim 1, wherein said error detection circuit is constituted by a folded circuit comprising a differential input of an NMOS transistor and a PMOS transistor.

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