JP2005250360A - Mask pattern verification apparatus and verification method - Google Patents

Abstract

In a conventional mask pattern verification apparatus, it is possible to detect a location where an OPC verification failure has occurred.
A verification apparatus and verification method for a mask pattern used for manufacturing a semiconductor integrated circuit, wherein each side of a mask pattern to be verified is divided more finely than in OPC processing according to a specified division method and division parameters. And a segment extraction unit 112 having a simulation point setting unit 112c for setting a simulation point on each divided segment by a specified method.
[Selection] Figure 1

Description

  The present invention relates to a mask pattern verification apparatus and verification method used for manufacturing a semiconductor integrated circuit (LSI), and more particularly to a mask pattern and optical proximity correction for performing layout design and mask data creation verification processing. And relates to a verification apparatus and verification method for a pattern subjected to OPC) processing.

  In order to prevent a decrease in pattern transfer fidelity due to an optical proximity effect in a lithography process in an LSI manufacturing process, an OPC process for correcting a mask pattern at the stage of LSI layout design and mask data creation is performed.

  Conventional OPC is realized by a technique called rule-based OPC and model-based OPC. Here, OPC includes correction of various effects generated throughout the wafer process such as resist development and etching, in addition to optical effects.

  For example, as described in Non-Patent Document 1, the rule-based OPC is a correlation table of distortion amounts due to proximity effects for each line width and space width based on actual measurement values obtained from test pattern transfer results. And creating a rule for changing the layout pattern to realize the correction. This rule-based OPC is good at processing to check and correct adjacent figures one-dimensionally like a line and space pattern.

  On the other hand, the model-based OPC is correction using a model based on lithography simulation, and the model is calibrated based on the actual measurement value obtained from the pattern transfer result, and more complicated in detail. It is a method that makes it possible to correspond to a process.

  This model-based OPC is good at processing that corrects two-dimensionally the effects of adjacent figures, and takes longer processing time than the rule-based OPC, but the overall correction accuracy is high. For advanced devices in recent years, OPC (two-dimensional OPC) that performs the above-described two-dimensional correction is required, and a model-based OPC that can realize this relatively easily is used. Further, a method of correcting by combining rule-based OPC and model-based OPC is also used.

  However, the accuracy required for OPC is becoming stricter as the number of process generations increases, and more patterns cannot be corrected correctly. Further, in the model-based OPC, it is not a practical method to cope with all of the calibration based on the actual measurement value in that the measurement time of the actual measurement value becomes long and it is difficult to calibrate a huge amount of data. . Therefore, the following processing method is used.

  (1) If there are areas with different required accuracy (for example, a logic circuit part and a memory and a memory peripheral part in a memory-embedded chip), a specialized model or rule is created and used separately.

  (2) When using a model or rule specialized for each process such as mask manufacturing, wafer processing after lithography such as lithography on a wafer, etching, etc. can improve accuracy (for example, If the tendency of proximity effect in etching is different from the tendency of proximity effect in other processes), a different model or rule is created, and correction for each process is sequentially performed according to the flowchart of the embodiment of high-precision OPC processing. .

  For each area on the chip, such as a logic part in a memory-embedded chip, a memory part (inside a memory cell, a cell edge part, a cell peripheral part, etc.), or for each step such as reticle manufacturing, lithography on a wafer, etching process, etc. When optimal OPC is performed by the processing methods (1) and (2), the average accuracy of the whole can be improved. However, some patterns cannot be handled, and special measures are required for each pattern. The memory part is divided into the inside of the memory cell, the cell edge part, the cell peripheral part, etc., and different OPCs are performed in each.

  Therefore, with the above-described conventional method, it is difficult to quickly start up OPC corresponding to most pattern variations. For this reason, the validity verification of the correction result of OPC is indispensable, and the establishment of a verification processing flow is a point for the early start-up of OPC.

  FIG. 33 shows an example of a flowchart and configuration for performing a conventional high-precision OPC process and its verification process (see Patent Document 1).

  In this verification processing flow, at the layout design stage in step S1, layout verification is performed using design rule check (DRC) / LVS or the like. Here, DRC is software that verifies whether the designed mask pattern conforms to the design rule, and violations of the design rule can be found in the DRC. LVS is software for verifying layout vs. schematic (Layout vs. Schematic), and uses this to verify the consistency between the original schematic and its layout. Thereafter, the verified layout design data (Layout) is stored in the layout storage device.

  Next, in the OPC process in step S2, the OPC process is performed on the verified layout data designed in step S1. In addition to OPC, layer processing is performed as appropriate. Here, the OPC process is performed for each process using (1) a method of using a model or the like for each region having different required accuracy, and (2) a model or rule specialized for each process of mask, lithography, and etching. A method of sequentially executing corresponding OPCs can be realized.

  As described above, in the pre-processing of the OPC process, the OPC target graphic is extracted and synthesized, and in the post-process of the OPC process, the graphic to be output as mask data is synthesized.

  Next, in the OPC rule check in step S3, OPC is performed to check the graphic correctness of the pattern after OPC (whether the corrected mask inspection and fabrication limit values and corrections in violation of the limit values in the wafer process have been made). Compare with previous pattern, verify using DRC, etc.

  Next, in the lithography rule check (LRC) in step S4, a pattern before and after OPC is input, and simple lithography simulation is performed for each edge after OPC or before (the side of the OPC target figure). By doing so, the data having the edge and deviation of the desired pattern larger than the specified value is outputted as the data D of the dangerous part.

  Next, in the determination based on the transfer image output in step S6, first, a dangerous part vicinity pattern including a dangerous part is read, and a detailed lithography simulation is executed on the dangerous part vicinity pattern to obtain a transfer image output. .

  Next, a determination is made based on the transfer image output to determine whether there is a problem with the OPC result. At this time, the results of the inspection in the mask fabrication and wafer fabrication in step S7 are also fed back as appropriate to determine whether there is a problem with the OPC result.

  In other words, if there is a problem pattern as a result of the determination in step S6, the process returns to step S1 or step S2, examines a workaround, etc., optimizes OPC settings, and copes with layout changes, etc. I do. This verification process is also realized between the subdivided OPC processes as described above.

  If there is no problem as a result of the determination in step S6, the OPC verified data is converted into electron beam (EB) drawing data, and the process proceeds to a mask (reticle) manufacturing process shown in step S7.

  A set of a plurality of photomasks manufactured in the mask manufacturing process is subjected to mask inspection, and if there is no problem, the process proceeds to a lithography process on the wafer. In this step, a photoresist film is applied onto the wafer using a spinner, and the photoresist film is exposed using a photomask (reticle) mounted on a stepper. Further, the process proceeds to a lithography inspection step through steps such as development, rinsing, post-baking, and curing. Further, if the photoresist pattern on the wafer is inspected and there is no problem, the process proceeds to an etching process, and the photoresist film formed on the wafer is used as an etching mask by reactive ion etching (RIE). The thin film below the film is etched. When the etching is completed, the process proceeds to the etching shape inspection. If there is a problem as a result of wafer inspection such as mask inspection, lithography inspection, and etching shape inspection, the process returns to the previous processing and the OPC setting is corrected. If the layout needs to be corrected, the process returns to the previous process and the layout is corrected.

  Hereinafter, an example of a conventional OPC verification system and an OPC verification processing flow will be described in detail.

  FIG. 21 shows an example of the configuration of a conventional mask pattern verification system. This mask pattern verification system is a mask pattern system for verifying a mask pattern used for manufacturing a semiconductor integrated circuit and a pattern subjected to optical proximity correction processing. The mask pattern verification system includes a mask pattern verification device 10, an input unit, and an output unit. Composed. The mask pattern verification device 10 includes a model-based verification device 11 and an error location extraction device 12.

  The model-based verification device 11 divides each side of the mask pattern to be verified, sets the simulation point on each divided segment, and calculates the light intensity after moving the simulation point And an optical shift amount calculation unit 14 for calculating the optical shift amount.

  The segment extraction unit 13 includes an inspection target area specifying unit 13a, an edge dividing unit 13a that divides each side of the mask pattern to be verified in accordance with a specified division method and a division parameter, and on each divided segment. The simulation point setting means 13b for setting the simulation point by the method specified in FIG.

  The optical deviation amount calculation unit 14 is a simulation point moving unit 14a for moving the simulation point installed as described above, a light intensity calculating unit 14b for calculating the light intensity after moving the simulation point, An optical shift amount calculation unit 14c that calculates an optical shift amount based on the light intensity calculation result is provided.

  FIG. 22 shows an overall flow of OPC verification processing in the mask pattern verification system of FIG.

  In the first stage, the edge of the input pre-OPC data is divided into fine segments and a simulation point for calculating the light intensity is set on each divided segment.

  In the second stage, the installed simulation point is moved, the light intensity is calculated there, and it is determined whether or not the light intensity is within a specified tolerance (Tolerance). If it is outside the allowable range, the movement amount is calculated as an optical shift amount, and an error flag is set for the segment.

  After performing the above optical deviation calculation processing for every segment, proceed to the third stage, and extract the part that you want to see from the set error flags and identify the error part. Certify.

  FIG. 23 shows a flow of extraction processing of the segment to be calculated in FIG.

  FIGS. 24A and 24B show an example of segment extraction processing (edge division and setting of simulation points) in the flow of FIG. 23. FIG. 24A is a diagram at the time of OPC. Is at the time of OPC verification. Here, 50 is a simulation point, 51 is an edge division boundary, and 52 is a segment.

  FIG. 25 shows an example of segment processing in the flow of FIG. Here, 50 is a simulation point, 51 is an edge division boundary, 52 is a segment, 53 is a wafer image shape, 54 is a simulation point after movement, 55 is an error flag, and 56 is a simulation image polygon shape.

  FIG. 26 shows a flow of the light intensity calculation process for performing the optical shift amount calculation process in FIG.

  FIG. 27 shows an example of the error location extraction process in FIG.

  FIG. 28 shows an example of the flow of the error location extraction process in FIG.

  FIG. 29 shows an example of the error location extraction process in FIG. Here, 50 is a simulation point, 51 is an edge division boundary, 52 is a segment, and 53 is a wafer image shape.

  A simulation image / polygon is generated by arithmetic processing of the error flag and the pre-OPC data that are converted into polygons, and an error location is extracted therefrom using an error location extraction filter.

  FIG. 30 shows an example of the correlation between edge division, simulation points, and wafer image shape in the OPC verification process of FIG. Here, 51 is an edge division boundary, 53 is a wafer image shape, and 61 is an error location A.

  FIG. 31 shows an error location extraction situation when the error location extraction process of FIG. 28 is performed. Here, 72 is an error distribution A, 73 is an error specification A, and 74 is an error A that is out of specification (portion extracted as an error).

  FIG. 32 shows an example of error locations and pseudo error locations when the error location extraction processing of FIG. 28 is performed. Here, 81 is a simulation image polygon, 82 is a portion extracted as an error, 83 is a pseudo error area, 84 is a direction in which Width is measured, and 85 is a direction in which Space is measured.

  However, the above-described conventional OPC verification processing method using the OPC verification system has the following problems.

  (1) The first problem is that the edge division method and simulation point setting method at the time of OPC verification shown in FIG. 24B are the same as the setting at the time of OPC shown in FIG. It is that there is a rough way. Since the calculation of the light intensity is performed only on the simulation point, for example, in the example shown in FIG.

  (2) The second problem lies in the simulation point moving step. In this OPC verification system, the upper limit of the number of step movements is determined due to software restrictions, and many points cannot be calculated by reducing the number of steps. Since the optical deviation amount is calculated as a movement amount on the simulation point, it means that if the movement step amount is coarse, the verification accuracy becomes coarse at the same time.

  (3) The third problem lies in the error location extraction method shown in FIG. The biggest problem here is that the number of error parts to be extracted becomes enormous (thousands to hundreds of thousands). It is extremely difficult to find a truly dangerous part (bridge, open, etc.) from an enormous number of error parts, and even though errors were actually extracted by this method, the dangers such as a bridge or an open. There is an example of having overlooked a part.

(4) In order to improve the problems as described above, the error location extraction process as shown in FIG. 28 is performed. The fourth problem is in the method. First, after the error flags of all segments are converted to polygons, Boolean calculation processing is performed on pre-OPC data, and error location extraction filters are performed on the entire simulation image polygon. For this reason, the larger the data scale, the greater the error extraction processing time. The error location extraction situation in this case is shown in FIG. 31. (5) The fifth problem is the DRC command (measurement of the space width and the line width of the line pattern; the post-OPC data including many fine steps; (Space / Width measurement) is performed, so that there is a high possibility that pseudo errors frequently occur as shown in FIG. That is, the problem that the number of extracted errors becomes enormous cannot be solved.

  (6) A sixth problem is that the conventional method uses only one type of verification model (only the best condition), so that the lithography margin cannot be verified.

  (7) The seventh problem is that, when verifying unexpectedly huge data, the processing time becomes enormous and the processing may not end.

Patent Document 2 discloses a mask pattern verification apparatus and a mask pattern verification method that can easily verify a mask pattern generated by a super-resolution technique and correct a layout with high accuracy.
Japanese Patent Laid-Open No. 11-102062 Japanese Patent Laid-Open No. 11-282151 Otto et.al., "Automated Optical Proximity Correction-A Rules-based Approach", SPIE Optical / Laser Micro lithography VII, March 1994

  As described above, in order to prevent a decrease in pattern transfer fidelity due to an optical proximity effect in a lithography process when manufacturing an LSI, an OPC process for correcting a mask pattern is performed at the mask data creation stage. However, with the recent miniaturization of semiconductor processes, the accuracy required for OPC processing has become stricter, and the conventional mask pattern verification system has a problem that verification failure occurs in OPC verification.

  The present invention has been made to solve the above-mentioned problems, and by devising edge division and simulation point setting during OPC verification, it is possible to detect a location where leakage of OPC verification has conventionally occurred. An object of the present invention is to provide a mask pattern verification apparatus and a verification method capable of realizing highly accurate OPC verification.

  The present invention relates to a mask pattern verification apparatus for verifying a mask pattern used for manufacturing a semiconductor integrated circuit and a pattern subjected to optical proximity correction processing. Each side of a mask pattern to be verified is divided more finely than during optical proximity correction processing. A segment extraction unit that sets a simulation point on each divided segment, an optical shift amount calculation unit that calculates an optical shift amount by calculating light intensity after moving the simulation point, and A simulation image / polygon generating unit for generating a simulation image / polygon used for error location extraction from the optical shift amount, and an error location extracting unit for extracting an error location from the optical shift amount / simulation image / polygon. It is characterized by doing.

  Further, the present invention provides a mask pattern verification method for verifying a mask pattern used for manufacturing a semiconductor integrated circuit and a pattern subjected to an optical proximity effect correction process. A segment extraction step for finely dividing and setting a simulation point on each divided segment, and an optical shift amount calculating step for calculating an optical shift amount by calculating a light intensity after moving the simulation point A simulation image / polygon generating step for generating a simulation image / polygon used for error location extraction from the optical shift amount, and an error location extracting step for extracting an error location from the optical shift amount / simulation image / polygon; It is characterized by having To.

  In the mask pattern verification apparatus and the mask pattern verification method of the present invention, it is possible to bring the verification accuracy closer to the wafer image shape by finely specifying the movement of the simulation point during OPC verification. Further, by devising the error extraction in the OPC verification, it is possible to avoid overlooking the intrinsic error by enlarging the number of errors to be extracted, and to shorten the error extraction processing time in the OPC verification. In addition, by optimizing the measurement of the space / width of the pattern during OPC verification, it becomes possible to suppress pseudo errors during error extraction as much as possible. In addition, the lithography margin can be verified by adopting a plurality of models in the OPC verification. Further, by dividing and processing the data in the OPC verification, it is possible to complete the verification process for the very large scale data (giant input data) in a realistic time (within real time). In addition, a specific location can be verified in detail during OPC verification.

  According to the mask pattern verification apparatus and the verification method of the present invention, even for a huge full chip or a complicated mask pattern, an intrinsic error that induces short-opening can be accurately and accurately detected without omission of verification and without a pseudo error. It can be detected quickly. In addition, an error location can be detected in real time by using a division method for an unexpectedly huge mask pattern.

<First Embodiment>
FIG. 1 shows an example of the configuration of a mask pattern verification system according to the first embodiment of the present invention.

  This mask pattern verification system verifies a mask pattern used for manufacturing a semiconductor integrated circuit and a pattern subjected to optical proximity correction processing, and includes a mask pattern verification device 110 including a model-based verification device 111, an input unit, And an output unit.

  The model-based verification device 111 divides each side of the mask pattern to be verified more finely than during OPC, and after moving the simulation point, a segment extraction unit 112 that sets a simulation point on each divided segment, An optical shift amount calculation unit 113 for calculating light intensity and calculating an optical shift amount, and a simulation image / polygon generation unit 114 for generating a simulation image / polygon used for error location extraction at a high speed from the optical shift amount; And an error location extraction unit 115 for extracting an error location from the optical shift amount and the simulation image / polygon at high speed.

  The segment extraction unit 112 includes an inspection target area specifying unit 112a, an edge dividing unit 112b for dividing each side of the mask pattern to be verified more finely than in the OPC according to the specified division method and division parameters, There is a simulation point setting means 112c for setting a simulation point on each segment that has been designated.

  The optical shift amount calculation unit 113 calculates the light intensity within a range of, for example, a radius of 1 μm after moving the simulation point and the simulation point moving means 113a for moving the simulation point installed as described above. A light intensity calculation means 113b and an optical shift amount calculation unit 113c for calculating the optical shift amount based on the light intensity calculation result are provided.

  FIG. 2 shows an example of the overall flow of the OPC verification process in the mask pattern verification apparatus of FIG. In the flow shown in FIG. 2, in the first stage of processing, the edge of the input pre-OPC data is divided into fine segments (Segments), and simulation points for calculating the light intensity are set on each of the divided segments. .

  In the second stage of the process, the installed simulation point is moved, where the light intensity is calculated, and it is determined whether the light intensity is within a specified tolerance (Tolerance). If it is outside the allowable range, the movement amount is calculated as an optical shift amount, and an error flag is set for the segment. Such processing is sequentially performed on all segments.

<Second Embodiment>
The second embodiment relates to the segment extraction unit 112 in FIG. FIG. 3 is a flowchart showing an example of the segment extraction process in the flow of FIG.

  FIGS. 4A and 4B show an example of segment extraction processing (edge division and setting of simulation points) in the flow of FIG. 2, and FIG. 4A is a diagram at the time of OPC. Is at the time of OPC verification. Here, 50 is a simulation point, 51 is an edge division boundary, 52 is a segment, and 53 is a wafer image shape.

  In this segment extraction process, the edge division method and the division parameters are specified more finely than in OPC (for example, if division is performed in units of 100 nm during OPC, 60 nm is used during OPC verification). The coarsely divided portion is also divided so as to be further subdivided, and the position of the simulation point is set slightly deviated from the time of OPC (about 10 nm).

  In this case, the simulation point and the edge division boundary are set more finely. At the time of OPC, the number of segments divided as shown in FIG. 4 (a) is 18, whereas at the time of OPC verification, the number of segments divided as shown in FIG. 4 (b) is 26.

  FIG. 5 shows an example of the correlation among edge division, simulation point, and wafer image shape in the second embodiment. As described above, by devising edge division and simulation point setting during OPC verification, it becomes possible to detect a location where OPC verification has been leaked as shown in FIG. Compared with the verification method, the computer processing time and the verification time can be greatly reduced, and highly accurate OPC verification can be realized.

<Third Embodiment>
The third embodiment relates to the optical shift amount calculation unit 113 in FIG. Here, in order to bring the verification accuracy close to the wafer image shape, the movement of the simulation point is made fine.

  FIG. 6 is a flowchart showing an example of the light intensity calculation process for performing the optical shift amount calculation process in the flow of FIG. Move the simulation point by the specified amount and number of movements, calculate the light intensity once on the simulation point after movement, and move the simulation point if the light intensity is outside the allowable range The amount is calculated as an optical shift amount.

  FIGS. 7A and 7B are shown for explaining the movement amount of the simulation point in the third embodiment. Here, 50 is a simulation point, 51 is an edge division boundary, 52 is a segment, 53 is a wafer image shape, 54 is a simulation point after movement, and 56 is a simulation image polygon shape.

  According to the light intensity calculation process as described above, it is possible to finely move the simulation point 54 (0.5 nm to several nm) and increase the number of calculations without any software restrictions. Thereby, there is little difference between the wafer image shape 53 and the simulation image / polygon shape 56, and the verification accuracy is approximated to the wafer image shape 53. That is, the verification accuracy can be increased to an extent that can be approximated to the wafer image shape 53.

  On the other hand, in the conventional example, as shown in FIG. 25 (b), the amount of movement of the simulation point is rough, so the wafer image shape and the simulation image / polygon shape are slightly different from each other. The accuracy drops.

<Fourth Embodiment>
The fourth embodiment relates to the error location extraction unit 115 in FIG. Here, the error extraction method is devised in order to avoid overlooking the intrinsic error due to the increase in the number of extracted errors. In addition, in order to shorten the processing time of the error extraction method, the method of generating a simulation image / polygon and the error extraction flow have been devised.

  FIG. 8A is a flowchart showing an example of simulation image / polygon generation processing by the simulation image / polygon generation unit 114 in FIG. In this simulation image / polygon generation process, after calculating the optical shift amount as described above, the segment is moved directly by the optical shift amount to have the shape as shown in FIG. 7B. Generate simulation image polygon.

  This process is performed in the model-based verification apparatus 111 shown in FIG. Further, this process is performed for each segment as shown in FIG. 2, and is repeated until the processes for all the segments are completed.

  FIG. 8B is a flowchart showing an example of the error location extraction process by the error location extraction processing unit 115 in FIG. The error location extraction unit 115 may extract the error location using the error location extraction filter after calculating the optical shift amount as described above in the error location extraction processing.

  The processing in the error location extraction filter is also performed in the model-based verification apparatus 111 shown in FIG. 1, and this processing is performed for each segment as shown in FIG. Repeat until

  According to the error location extraction process as described above, it is possible to save the trouble of generating a simulation image / polygon by Boolean calculation processing as in the conventional method, and the error location extraction filter process is also performed for each segment, so the processing becomes lighter. It is possible to complete the processing at high speed.

  9 to 11 are flowcharts showing a plurality of examples of the error location extraction filter process in FIG.

  FIG. 12 shows an example of error location extraction processing in the verification processing flow of FIG. Here, 51 is an edge division boundary, 53 is a wafer image shape, and 62 is an error location B.

  FIG. 13 is a diagram illustrating an error location extraction situation when the error location extraction process of the fourth embodiment is performed. Here, 75 is the error distribution B, 76 is the error spec B, and 77 is the error B out of spec (the part extracted as an error).

  According to the error location extraction process as described above, the number of extracted errors can be suppressed to a small number (1 in FIG. 12).

  On the other hand, as shown in FIGS. 31 and 32, in the conventional method, the number of extracted errors is large (eight in FIG. 32). In addition, in the conventional method, there is a case where an intrinsic error is overlooked when a large number (tens of thousands to hundreds of thousands) of errors are extracted. Since the number of errors is limited to a small number, the possibility of making an error that misses an intrinsic error is extremely low.

<Fifth Embodiment>
In the fifth embodiment, the error location extraction unit 115 described in the fourth embodiment devise a space / width measurement method to eliminate pseudo errors at the time of error extraction as much as possible, and correct only true errors. An error location extraction processing unit for detecting the error is provided.

  After the simulation image polygon is generated as described above, the space and width of the simulation image polygon and pre-OPC data are measured. This measurement is performed for each segment with a direction from that segment. Then, as shown in FIGS. 10 and 11, it is determined whether or not the calculated value is out of the spec, and if it is out of the spec, it is extracted as an error location. All of these series of operations are performed in the model-based verification apparatus 111 shown in FIG.

  FIG. 14 shows an example of an error location and a pseudo error location in the fifth embodiment. Here, 81 is a simulation image polygon, 83 is a pseudo error area, 84 is a direction in which Width is measured, and 85 is a direction in which Space is measured.

  According to the error location extraction process as described above, the direction is correctly determined from the segment and the space and width are measured. Therefore, as in the conventional method shown in FIG. There is no risk of extracting error locations. Therefore, the possibility that pseudo errors frequently occur is reduced, and the problem that the number of extracted errors becomes enormous is solved.

<Sixth Embodiment>
The sixth embodiment relates to another example of the optical shift amount calculation unit 113 in FIG. Here, in order to verify the lithography margin, multiple models can be used. As described above, after moving the simulation point, the light intensity is calculated and the amount of optical deviation is calculated. An optical shift amount calculation unit 113c for calculating

  FIGS. 15A and 15B are flowcharts showing two examples of the OPC verification process in the sixth embodiment.

  In the verification processing flow of FIG. 2 or FIG. 15A, one model is used when calculating the light intensity. On the other hand, in the verification processing flow of FIG. 15B, when calculating the light intensity, a plurality of (usually three) models are used. Differences between models include differences in dose amount, focus setting, NA setting, light source wavelength setting, sigma setting, sigma-in setting, exposure light source type setting, stepper setting, resist setting, transmittance setting, and processing setting. For example, model 1 is set to the best condition (best dose, best focus), model 2 is set to Under Dose and Defocus 0.15 μm, and model 3 is set to Over Dose and Defocus 0.15 μm.

  According to the configuration and processing as described above, an error result corresponding to the condition can be obtained, so that the lithography margin and variation of the mask pattern to be verified can be estimated.

<Seventh Embodiment>
The seventh embodiment is characterized in that data is divided and processed in order to process very large-scale data in a realistic time. Data for dividing input data into the input unit in FIG. An input unit is provided.

  FIG. 16 is a flowchart illustrating an example of the OPC verification process according to the seventh embodiment. In the seventh embodiment, when the input data is huge, after the area (Area) is divided into Area1, Area2, Area3,..., AreaN corresponding to the designated number N, OPC verification is performed for each area. Process.

  As described above, according to the configuration in which the input data can be divided by the data input unit, it is possible to prevent the error extraction processing time from increasing even for unexpectedly large data, and to verify in real time. It can be terminated. Further, by performing the OPC verification process for each divided area in parallel, the processing time for error extraction can be greatly shortened.

<Eighth Embodiment>
In the eighth embodiment, the error location extraction unit 115 described in the fifth embodiment includes a coverage verification unit that verifies the coverage of a hole such as a contact or a via.

  FIG. 17 shows an example of a coverage verification process for a hole by a coverage verification unit according to the eighth embodiment. Here, 91 is a wafer image shape, 92 is a contact hole, 93 is an OPC target layer, and 94 is a portion extracted as a coverage error.

  In the eighth embodiment, the coverage verification unit inspects the area ratio between the simulation image polygon and the hole described above, thereby performing an operation of extracting a portion out of the specified specification (Spec) as an error.

  By providing the coverage verification unit as described above, it is possible to verify the coverage of the hole together with the verification of the dangerous part of the short / open of the pattern.

<Ninth Embodiment>
The ninth embodiment is characterized in that a specific place can be verified in detail, and in the mask pattern verification apparatus described in the first embodiment, an inspection target that specifies a portion to be inspected in detail A segment extraction unit 112 for designating an area is provided.

  FIGS. 18A and 18B are flowcharts showing two examples of the OPC verification process in the ninth embodiment, and are the same as the verification process flow shown in FIG.

  In the verification processing flow of FIG. 18B, in addition to the verification processing flow shown in FIG.

  FIG. 19 shows an inspection target area designating operation in the verification processing flow of FIG. According to this, the inspection target area is the database (Data Base: DB) where the user (verifier, designer, process manager, etc.) specifies the area as a polygon or coordinates, and where the risk is predicted in advance. In some cases, an inspection region is extracted by performing pattern matching with input data.

  20A and 20B show an example of the inspection target area specifying process in the ninth embodiment.

  After the region to be inspected is extracted as shown in FIG. 19, when only the region is inspected, as shown in FIGS. 20A and 20B, only the region is divided into fine segments, Other areas may be divided into coarse segments.

  As described above, by including a segment extraction unit that specifies an inspection target area that specifies a location to be inspected in detail, it is possible to eliminate unnecessary work in verification, to verify at high speed, and to quickly extract a dangerous location It becomes possible.

1 is a block diagram showing an example of the configuration of a mask pattern verification system according to a first embodiment of the present invention. The flowchart figure which shows an example of the whole flow of the OPC verification process in the mask pattern verification apparatus of FIG. The flowchart figure which shows an example of the segment extraction process in FIG. The figure which shows an example at the time of OPC and OPC verification about the segment extraction process (edge division | segmentation and installation of a simulation point) in FIG. The figure which shows an example of the correlation with the edge division | segmentation in the 2nd Embodiment of this invention, a simulation point, and a wafer image shape. The flowchart figure which shows an example of the light intensity calculation process for performing the calculation process of the optical deviation | shift amount in FIG. The figure shown in order to demonstrate the movement amount of the simulation point in the 3rd Embodiment of this invention. The flowchart figure which shows an example of the production | generation process of the simulation image * polygon by the simulation image * polygon production | generation part in FIG. 1, and the flowchart figure which shows an example of the error location extraction process by the error location extraction process part in FIG. The flowchart figure which shows the other example of the error location extraction filter process in FIG.8 (b). The flowchart figure which shows the further another example of the error location extraction filter process in FIG.8 (b). The flowchart figure which shows the further another example of the error location extraction filter process in FIG.8 (b). The figure which shows an example of the error location extraction process in the verification process flow of FIG. The flowchart figure which shows an example of the OPC verification process in the 4th Embodiment of this invention. The figure which shows an example of the error location and pseudo | simulation error location in the 5th Embodiment of this invention. The flowchart figure which shows two examples of the OPC verification process in the 6th Embodiment of this invention. The flowchart figure which shows an example of the OPC verification process in the 7th Embodiment of this invention. The figure which shows an example of the coverage verification process with respect to the hole by the coverage verification part in the 8th Embodiment of this invention. The flowchart figure which shows two examples of the OPC verification process in the 9th Embodiment of this invention. The figure which shows the designation | designated operation | work of the inspection object area | region in the verification processing flow of FIG.18 (b). The figure which shows an example of the designation | designated process of the test object area | region in the 9th Embodiment of this invention. The block diagram which shows an example of a structure of the conventional mask pattern verification system. FIG. 22 is a flowchart showing an overall flow of OPC verification processing in the OPC verification system of FIG. 21; The flowchart figure which shows the flow of the extraction process (Segment extraction process) of the segment used as the calculation object in FIG. The figure which shows an example at the time of OPC and OPC verification about the segment extraction process (edge division | segmentation and installation of a simulation point) in the flow of FIG. The figure which shows an example of the segment process in the processing flow of FIG. The flowchart figure which shows the flow of the light intensity calculation process for performing the calculation process of the optical deviation | shift amount in FIG. The flowchart figure which shows an example of the flow of the error location extraction process in the verification process flow in FIG. The flowchart figure which shows the other example of the flow of the error location extraction process in the verification process flow of FIG. The figure which shows that there exists a possibility that a dangerous location may be missed in the edge division | segmentation method and simulation point installation method shown in FIG. The figure which shows an example of the correlation with the edge division | segmentation in the process of FIG. 23, a simulation point, and a wafer image shape. The figure which shows the error location extraction condition at the time of performing the error location extraction process of FIG. The figure which shows an example of the error location at the time of performing the error location extraction process of FIG. 28, and a pseudo error location. The figure which shows an example of the flowchart for performing the conventional high precision OPC process, and its verification process, and a structure.

Explanation of symbols

110 ... Mask pattern verification device, input unit, output unit, 111 ... Model-based verification device, 112 ... Segment extraction unit, 113 ... Optical shift amount calculation unit, 114 ... Simulation image / polygon generation unit, 115 ... Error location extraction unit 112a ... specifying means for inspection area, 112b ... edge dividing means, 112c ... simulation point setting means, 113a ... simulation point moving means, 113b ... light intensity calculating means, 113c ... optical deviation amount Calculation means.

Claims (5)

In a mask pattern verification apparatus for verifying a mask pattern used for manufacturing a semiconductor integrated circuit and a pattern subjected to optical proximity correction processing,
A segment extraction unit that divides each side of the mask pattern to be verified more finely than the time of optical proximity correction processing, and sets a simulation point on each divided segment;
After moving the simulation point, calculating the light intensity, an optical shift amount calculating unit for calculating the optical shift amount,
A simulation image / polygon generating unit that generates a simulation image / polygon used for error location extraction from the optical shift amount,
An apparatus for verifying a mask pattern, comprising: an error location extraction unit that extracts an error location from the optical shift amount and a simulation image / polygon. The segment extraction unit includes edge dividing means for dividing each side of the mask pattern to be verified more finely than at the time of optical proximity effect correction processing according to the designated division method and division parameters,
2. The mask pattern verification apparatus according to claim 1, further comprising simulation point setting means for setting a simulation point on a segment divided by the dividing means by a specified method.   2. The data input unit according to claim 1, further comprising a data input unit for inputting data of the optical proximity effect corrected pattern, wherein the data input unit further includes an input data dividing unit for dividing the input data into a plurality of pieces. The mask pattern verification apparatus as described. In a mask pattern verification method for verifying a mask pattern used for manufacturing a semiconductor integrated circuit and a pattern subjected to optical proximity correction processing,
Segment extraction step of dividing each side of the mask pattern to be verified more finely than at the time of optical proximity correction processing, and setting a simulation point on each divided segment,
After moving the simulation point, calculating the optical intensity, calculating the optical shift amount, calculating the optical shift amount,
A simulation image / polygon generating step for generating a simulation image / polygon used for error location extraction from the optical shift amount;
A mask pattern verification method comprising: an error location extraction step for extracting an error location from the optical shift amount and the simulation image / polygon.   5. The mask pattern verification method according to claim 4, further comprising an input data dividing step of dividing the input data of the pattern subjected to the optical proximity effect correction processing into a plurality of pieces.

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