JP2005114362A - Capacitance detecting circuit and method, and fingerprint sensor using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacitance detecting circuit and a method, and a finger print sensor, which improve S/N ratios by reducing the effects of disturbance noise, and detect a very small capacitance value Cs and a capacitance change value ΔCs of a sensor element with sufficient sensitivity. <P>SOLUTION: The capacitance detecting circuit is a capacitance detector for detecting the capacitance of intersection parts of row wires and column wires in a capacitance sensor constituted by crossing the column wires across a plurality of the row wires, and comprises: an orthogonal code generating means for generating an orthogonal code, changing it in time-series order, and outputting a row drive signal; a row wire drive means for selecting and driving a plurality of row wires corresponding to the row drive signal; a capacitance detecting means connected to the column wires for converting the sum of the capacitance of intersection parts corresponding to the selected row wires into a voltage and outputting it as a detection voltage; and a decoding arithmetic circuit for decoding a data string of the detected voltage outputted in time-series order for every column wire by computations based on the orthogonal code, and for separating a voltage corresponding to the capacitance of each intersection part. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a capacitance detection circuit and a detection method for detecting a minute capacitance, and a fingerprint sensor using the same.

  Conventionally, as the most promising fingerprint sensor in biometrics (biometric authentication technology), column wiring and row wiring are respectively formed on the surface of two films at predetermined intervals, and this film is interposed via an insulating film or the like. Thus, pressure-sensitive capacitive sensors have been developed that are arranged to face each other at a predetermined interval. In this pressure-sensitive capacitive sensor, when the finger is placed, the film shape changes corresponding to the unevenness of the fingerprint, the distance between the column wiring and the row wiring changes depending on the location, and the fingerprint shape changes between the column wiring and the row wiring. It is detected as the capacity of the intersection. In this pressure-sensitive capacitance sensor, as a conventional technique that can be applied to detect a capacitance less than several hundred fF (femtofarad), there is a detection circuit that converts a capacitance into an electric signal by a switched capacitor circuit. This is a switched capacitor that is driven by a first sensor driving signal and detects a detection target capacitance, and a reference capacitor that is driven by a second sensor driving signal and serves as a detection circuit reference capacitor. The first and second sample and hold units connected to the circuit and operating alternately sample each output signal, and then obtain a detection signal by obtaining a difference between the sampling results.

The detection circuit can stably detect a signal proportional to the capacitance value Cs to be detected and inversely proportional to the feedback capacitance Cf in a common switched capacitor circuit, and the reset switch of the switched capacitor circuit. The influence (feedthrough) in which the charge Qd accumulated in the parasitic capacitance between the gate electrode and the other electrode of the (feedback control switch) leaks to the other electrode is offset. In addition, it is expected that the low-frequency noise included in the offset component of the reference potential of the switched capacitor circuit or the input signal can be removed to some extent by obtaining the difference between the two sampling results (for example, patents). Reference 1).
JP-A-8-145717 (paragraphs 0018-0052, FIGS. 1 to 4)

However, a capacitance detection circuit such as a fingerprint sensor is required to have high sensitivity because the capacitance change is minute. However, it is required for noise transmitted from the human body (including high-frequency noise) and circuit noise. It is necessary to have all tolerances.
Further, in order to detect a capacitance change, there is a demand that there is no influence of crosstalk noise from adjacent lines or the like between column wirings or row wirings.

In response to the above-described request, the charging voltage corresponding to the charge charged in the capacitor at the intersection is detected at the time of rise of the column wiring, and then the capacitance of the intersection at the time of falling of the column wiring. A capacity detection circuit that detects a discharge voltage corresponding to the electric charge discharged from the battery and detects a change in the capacity using the charge voltage and the discharge voltage is also conceivable.
That is, this capacitance detection circuit obtains a difference voltage obtained by subtracting the discharge voltage from the charge voltage, and uses this difference voltage as a voltage corresponding to the capacitance change, thereby causing the influence of the feedthrough of the amplifier circuit that occurs with the same polarity. It is possible to remove the voltage offset due to the above and other offset components generated in other circuits, and to remove noise having a frequency sufficiently lower than the sampling frequency.

When detecting a change in capacitance of each sensor element of a capacitance sensor, a normal detection circuit including the above-described capacitance detection circuit drives only a single column wiring and crosses a plurality of row wirings serving as detection lines. It is the structure which detects the change of the capacitance value Cs of a part (sensor element).
However, as already described, the capacitance change per sensor element (one intersection) is a very small value of about several hundred fF.

For this reason, even if the conventional capacitance detection circuit removes the offset component in the circuit including the amplifier circuit, it is affected by noise originally superimposed on the capacitance sensor.
In other words, the capacitance detection circuit has an accurate capacitance due to the influence of such disturbance noise by superimposing power supply noise or conduction noise transmitted to the capacitance sensor via the human body on the signal of the column wiring and row wiring. There is a drawback that change cannot be detected.

In particular, an inverter fluorescent lamp, which is the mainstream of recent fluorescent lamps, is a noise source having a fundamental frequency of several tens of KHz because a high frequency is generated by a semiconductor to light the fluorescent lamp.
However, in the capacitance detection circuit, the sampling frequency of the capacitance change when obtaining the difference between the charge voltage and the discharge voltage is close to the fundamental frequency of the noise source.

For this reason, in this capacitance detection circuit, even if the difference between the charging voltage and the discharging voltage is obtained, a beat component caused by the frequency difference, that is, when two waves having slightly different frequencies are superimposed, the frequency A “beat (beat frequency)” equal to the difference between the two remains, and the noise component of the disturbance cannot be completely removed.
Therefore, when the user intends to use a fingerprint sensor or the like, it is used in the vicinity of the user's human body having a noise source having a frequency close to the sampling frequency of the capacitance detection circuit, for example, in the vicinity of the inverter fluorescent lamp described above. When the sensor is connected to a device having an inverter circuit used for a backlight of a liquid crystal display element, the disturbance noise caused by the above beat cannot be completely removed, and the capacitance change The S / N ratio of the signal to be detected is lowered, and the user's fingerprint cannot be read accurately.

  The present invention has been made in view of the above circumstances, and its purpose is to improve the S / N ratio by reducing the influence of disturbance noise, and to meet the intersection where column wiring and row wiring intersect ( It is an object of the present invention to provide a capacitance detection circuit, a detection method, and a fingerprint sensor capable of detecting a minute capacitance value Cs of the sensor element) and a capacitance change value ΔCs of the capacitance value Cs with sufficient sensitivity.

  The capacitance detection circuit of the present invention is a capacitance detection circuit that detects a change in capacitance at the intersection of a column wiring and a row wiring in a capacitance sensor configured by intersecting row wiring with a plurality of column wirings. The orthogonal code is changed in time series (by changing the arrangement of the bit arrangement of the data sequentially) and output as a column drive signal, and the column drive signal corresponding to the column drive signal A column wiring driving means for selecting and driving a plurality of column wirings in the wiring; and a total of change in capacitance of each of the intersections connected to the row wiring and corresponding to the selected column wiring is converted into a voltage signal; Capacitance detection means that outputs as a detection voltage, and a data string of detection voltages that are output in time series from the capacitance detection means, are decoded by a predetermined calculation based on the orthogonal code, and the capacitance change at each of the intersections Corresponding voltage And having a decoding operation unit for releasing (decoding operation circuit).

With this configuration, the capacitance detection circuit according to the present invention simultaneously drives a plurality of column wirings intersecting the row wirings by orthogonal codes (Walsh codes) having orthogonality, that is, a plurality of column wirings in a row wiring unit. The sensor elements are driven simultaneously, the capacitance value Cs and the capacitance change value ΔCs to be detected are multiplexed, and increased as the capacitance value N · Cs and the capacitance change value N · ΔCs (N is the number of column wirings driven simultaneously, In other words, the number of intersections to be multiplexed), capacitance / voltage conversion, and detection signals are used, so that substantially large capacitance values and capacitance changes are measured. By using the orthogonal code that improves the S / N ratio and is excellent in orthogonality, the influence of crosstalk between column wirings can be eliminated.
In addition, the capacity detection circuit of the present invention uses a product-sum operation (predetermined operation) for a multiplexed detection signal detected by the decoding operation unit in time series using the same orthogonal code as the orthogonal code used for multiplexing. Is used to decode the multiplexed detection value as the capacitance value Cs and capacitance change value ΔCs of each sensor element corresponding to the row wiring, so that the detection result with the same resolution as when one column wiring is driven. Can be obtained.

  The capacitance detection circuit of the present invention is also applicable to the configuration in which the capacitance of the intersection portion of the area type capacitance sensor in which a plurality of the row wirings are arranged in a matrix with respect to the plurality of column wirings is detected. By using it for a fingerprint sensor or the like, a highly accurate determination result can be obtained due to the above-described effects.

  The capacitance detection circuit of the present invention may be configured to detect the capacitance of the intersection of a line-type capacitance sensor in which one row wiring is formed corresponding to the plurality of column wirings. It can be applied, and by using it as a sensor for detecting the presence or absence or roughness of the surface, it is possible to detect the surface state with high accuracy by the above-described effects.

In the capacity detection circuit according to the present invention, in the Walsh code generated by the orthogonal code generation means as a matrix of 2 n, all columns and all rows except for a portion of logic “0” (2n−1) × In order to supply (2n-1) orthogonal codes to the column wiring drive means in time series for each column wiring of (2n-1) columns or less, with the (2n-1) matrix being an orthogonal matrix, By evenly assigning the number of times of driving to each column wiring, the detection value multiplexed by the product-sum operation (predetermined operation) is performed using the same orthogonal code as the orthogonal code used for multiplexing. Since decoding is performed as the capacitance value Cs and capacitance change value ΔCs of each sensor element corresponding to the wiring, the detection result can be obtained with the same resolution as when one column wiring is driven.
In addition, if the capacity detection circuit of the present invention is configured such that the decoding process is performed by, for example, an external personal computer, it is not necessary to directly send the fingerprint data in the decoded state, and data is multiplexed because it is multiplexed with orthogonal codes. Improves confidentiality.

In the capacity detection circuit of the present invention, in the Walsh code generated by the orthogonal code generation means as a matrix of 2 n, all the columns are excluded from the logic “0” (2 ⁿ −1) × (2 ⁽ⁿ ) matrix is an orthogonal matrix, and (2 ⁿ -1) orthogonal codes are supplied to the column wiring drive means in time series for each column wiring of (2 ⁿ ) columns or less. .
As a result, in the capacitance detection circuit of the present invention, the number of times each column wiring is driven is halved with respect to the number of detections, and the influence of crosstalk between column wirings is suppressed. Can be done more accurately.

  Since the fingerprint sensor of the present invention can detect a change in capacitance at the intersection (sensor element) using the capacitance detection circuit, it can collect fingerprints with high accuracy.

In the capacitance detection method of the present invention, when the column wiring driving means outputs a signal rising to the first voltage to the column wiring, and the column wiring is driven by the first voltage by the row voltage output means. Outputting a third voltage corresponding to a current for charging a plurality of capacitances of the intersections, and discharging a plurality of the capacitances of the intersections when the column wiring is driven by the second voltage. A corresponding fourth voltage is output to obtain a capacitance change value.
With this configuration, the capacity detection method according to the present invention enables the influence of the discharge current caused by the feedthrough that always overlaps the charge / discharge current to the capacity at the intersection in a certain direction, the output voltage during the charge and the discharge time during the discharge. Therefore, the influence of the discharge current due to the feedthrough of the amplifier circuit in the charge amplifier circuit 6 can be offset, and the capacitance change value at the intersection can be detected with high accuracy.

  As described above, according to the capacitance detection circuit of the present invention, by multiplexing with orthogonal codes and driving a plurality of column wirings at a time, a capacitance value obtained by adding capacitance changes at a plurality of intersections is detected. As a result, the influence of disturbance noise superimposed on the row wiring and the like is relatively reduced, the detection sensitivity is improved, and decoding is performed using the orthogonal code used for multiplexing, and the capacitance change value at each intersection is determined. Therefore, it is possible to obtain the effect that the capacitance change value at each intersection can be detected with substantially the same resolution as that detected by driving a single column wiring.

  The capacitance detection circuit according to the present invention is a capacitance detector that detects a change in capacitance at the intersection between a column wiring and a row wiring in a capacitance sensor configured by intersecting row wiring with a plurality of column wirings. The generating means generates orthogonal codes, changes the orthogonal codes in time series and outputs them as column drive signals, and the column wiring drive means selects a plurality of column wirings in the column wiring in accordance with the column driving signals. The capacitance detection means is connected to the row wiring, the sum of the capacitance changes of each intersection (sensor element) corresponding to the selected column wiring is converted into a voltage signal, output as a detection voltage, and decoded. A calculation circuit decodes a data string of detection voltages output in time series from the capacitance detection means by a predetermined calculation based on the orthogonal code, and separates the voltage corresponding to the capacitance change at each intersection to detect the detection value. To do.

A capacitance detection circuit according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram illustrating a configuration example of the capacitance detection circuit according to the first embodiment.
The orthogonal code generator 1 generates an orthogonal code used for generating a column drive signal for driving each column wiring of the column wiring group 2 of the sensor unit 4. As this orthogonal code, an orthogonal code with high orthogonality, for example, a Wilsh code is used. In the sensor unit 4, the column wirings of the column wiring group 2 and the row wirings of the row wiring group 3 intersect in a matrix, and each intersection forms a sensor element (sensor element 55 in FIG. 4).
2A is a plan view of the sensor unit 4, and FIG. 2B is a cross-sectional view. As shown in FIG. 2A, for example, each column wiring of the column wiring group 2 and each row wiring of the row wiring group 3 arranged at a pitch of 50 μm intersect each other. As shown in FIG. 2B, a row wiring group 3 composed of a plurality of row wirings is arranged on a substrate 50, an insulating film 51 is laminated on the surface, and only a gap 52 is formed on the surface of the insulating film 51. The film 54 is disposed with a space therebetween, and the column wiring group 2 including a plurality of column wirings is attached to the lower surface of the film 54. A sensor element is formed as a capacitive element having a predetermined capacitance at the intersection of the row wiring of the row wiring group 3 and the column wiring of the column wiring group 2 with the gap 52 and the insulating film 51 interposed therebetween.

When the finger 56 is put on the sensor unit 4 described above, the film 54 and the column wiring of the column wiring group 2 are deformed due to the unevenness of the finger 56 as shown in FIG. The capacitance of the sensor element 50 formed at the intersection between the column wiring group 2 and the row wiring group 3 changes.
FIG. 4 is a conceptual diagram showing a matrix of capacitive elements (sensor elements) between the column wirings and the row wirings of the sensor unit 4. The sensor unit 4 is composed of matrix-like sensor elements 55, 55..., And the column wiring drive unit 5 and the capacitance detection circuit 100 are connected to each other. The column wiring drive unit 5 outputs a drive pulse train to the column wiring group 2 corresponding to the bit arrangement of the orthogonal codes, that is, in parallel to the column wirings of the column wiring group 2 of the sensor unit 4, respectively. A predetermined drive pulse (drive signal) is output to A drive pulse pattern in this drive pulse train (a pattern that does not drive) is generated based on the orthogonal code, and drives a plurality of column wirings of the column wiring group 2 in accordance with the bit string data of the orthogonal code ( The capacitance change value of each intersection (sensor element) formed by the row wiring of each driven column wiring (corresponding to each row wiring) is multiplexed. The capacitance detection circuit 100 includes a charge amplifier circuit 6, a sample hold circuit 17, a selector circuit 8, an A / D converter 9, a decoding operation circuit 10, and a timing control circuit 11 (see FIG. 1).

The charge amplifier circuit 6 is provided in each row wiring in the row wiring group 3 of the sensor unit 4, and enters and exits according to the capacitance of the intersection (sensor element) (based on the charge / discharge current). Current corresponding to the amount of change) is detected, the current is amplified and converted into a voltage, and output as a detection signal (measurement voltage). The sample hold circuit 7 is provided for each charge amplifier circuit 6 and samples the measurement voltage of the detection signal by inputting the sampling hold signal, and temporarily holds it as voltage information. The selector circuit 8 switches the voltage information held in each of the sample hold circuits 7 sequentially, for example, in the order of the row arrangement, and outputs the voltage information to the A / D converter 9.
The A / D converter 9 converts the measurement voltage, which is analog voltage information input in time series, into digital measurement data at the timing of the A / D clock input from the decoding arithmetic circuit unit 10. To the decoding arithmetic circuit unit 10.
Further, when processing at a high speed, the A / D converter 9 is provided in each charge amplifier circuit 6 without providing the sample hold circuit 7, and the analog measurement voltage is converted into digital measurement data. You may do it.

In the digitized measurement data, the decoding calculation circuit unit 10 performs calculation processing for removing an offset component due to feedthrough by calculating a difference between measurement data at the time of charging the sensor element at the intersection and measurement data at the time of discharging, The signal multiplexed by the orthogonal code is decoded by a product-sum operation using the same orthogonal code as the encoded orthogonal code, and separated into voltage data components indicating a change capacitance value for each sensor element. Perform arithmetic processing.
When a start signal indicating that capacitance detection is started is input from the decoding arithmetic circuit 10 to the timing control circuit 11, the orthogonal code generation unit 1, the column wiring drive unit 5, the charge amplifier circuit 6, the sample hold circuit 7 and A clock and a control signal are output to the selector circuit 8 and the like, and the operation timing of the entire capacitance detection circuit 100 is controlled.

  Next, the configuration of the charge amplifier circuit 6 will be described with reference to FIG. FIG. 5 is a conceptual diagram showing a configuration example of the charge amplifier circuit 6. As shown in this figure, the charge amplifier circuit 6 includes an operational amplifier 121 and a feedback capacitor connected between the inverting input terminal and the output terminal of the operational amplifier 121. Cf and an analog switch 124 for discharging the charge of the feedback capacitor Cf. The non-inverting input terminal of the operational amplifier 121 is connected to the reference potential. In the figure, Cp is a parasitic capacitance of the operational amplifier 121 and the like, Cs is a capacitance of the sensor element at the above-described intersection (total of multiplexed sensor elements), and Cy is a capacitance of the sensor element with respect to the column wiring that is not detected. Is the sum of

Next, an example of the operation of the capacitance detection circuit according to the first embodiment of the present invention having the above configuration will be described with reference to FIG. Here, in order to simplify the description, a 15-bit orthogonal code generated from an orthogonal code reading circuit 20 described later will be described as an example.
It is assumed that the decoding operation circuit 10 has received a signal from the outside to start capacity detection, that is, a fingerprint collection by the fingerprint sensor (sensor unit 4).
As a result, the decoding arithmetic circuit 10 outputs a start signal that instructs the timing control circuit 11 to start detection. Next, the timing control circuit 11 outputs a clock signal and a reset signal to the orthogonal code generator 1.
Then, the orthogonal code generation unit 1 initializes each of the internal address counter 22 and the storage register 23 (FIGS. 8 and 9) via the orthogonal code read circuit 20 in response to the reset signal, and generates the clock. In synchronization, the orthogonal codes are sequentially read from the code memory 21 and output.

Here, the orthogonal code generation unit 1 stores an orthogonal code created in advance in the internal code memory 21, and each time a clock is sequentially input, a data string having orthogonality is connected to the column wiring drive unit. Output to 5.
The Walsh code, which is a typical orthogonal code, is generated in the order shown in FIG. As a basic structure, a basic unit of 2 (rows) × 2 (columns) is formed, but the upper right, upper left, and lower left bits are the same, and the lower right is an inversion of these bits.
Next, four 2 × 2 basic units described above are combined as blocks in the upper right, upper left, lower right, and lower left to create a code of a bit array of 4 (rows) × 4 (columns). Here, as in the creation of the 2 × 2 basic unit, the lower right block is bit-inverted. In the same procedure, the number of bits of the bit arrangement of the code (corresponding to the number of columns) and the number of codes (the number of rows) are set as 8 (row) × 8 (column), 16 (row) × 16 (column). Response).

In the first embodiment, the measurement data can be multiplexed on the first row and the first column, all of which are logic “0”, that is, all the bits of data are “0”, without driving the columns. Because it was not, it was excluded from the code. In FIG. 6, for example, a 15 × 15 bit matrix is used as an orthogonal code.
As described above, a Walsh code can be generated similarly for a code having a long code length, and the generated Walsh code can be applied to multiplexing in capacity measurement described below.
In this embodiment, for example, the column wiring group 2 is composed of 15 wirings C1 to C15, and orthogonal codes represented by a matrix of 15 × 15 bits are used for multiplexing at the time of capacitance measurement.

The code memory (code memory 21 in FIG. 8) in the orthogonal code generator 1 stores the data of the orthogonal codes represented by the 15 × 15 matrix in the data format shown in the table of FIG. Each row is stored in order in association with the addresses t1 to t15.
Here, for example, the Walsh code in the row of the address t1 is {1 (LSB), 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1 (MSB)}. And the Walsh code of the row at address t15 is {1 (LSB), 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0 (MSB)} It has become.

When the start signal is input, the timing control circuit 11 outputs a measurement start signal to the orthogonal code generator 1.
In FIG. 8, when the measurement start signal is input, the orthogonal code reading circuit 20 resets the address counter 22 and the storage register 23 and sets the count value of the address counter 22 to “0”.

Next, after the above initial state, the orthogonal code readout circuit 20 receives the clocks output in time series from the timing control circuit 11 when measuring the capacitance value at the intersection when measuring the capacitance at the intersection. A count signal is output to the address counter 22 each time.
Then, the address counter 22 counts the input count signal and outputs the addresses t1, t2,..., T15 to the code memory 21 corresponding to the count value.
As a result, the code memory 21 outputs Walsh code data (row bit arrangement) corresponding to the input addresses t 1, t 2,..., T 15 to the storage register 23.

In this storage register 23, the LSB of the bit string of Walsh code is input to the register 231 and sequentially input, and the MSB of the bit string of Walsh code (hereinafter referred to as orthogonal code) is input to the register 2315.
Each register of the storage register 23 is connected to the buffer circuit in the column wiring drive section 5, that is, each of the registers 231, 232, 233, 234, 235, ..., 2314, 2315 is connected to the buffer circuit 51. , 52, 53, 54, 55,... 514, 515, respectively.

  Next, as shown in FIGS. 8 and 9, the column wiring drive unit 5 simultaneously drives a plurality of column wirings in the column wiring group 2 in correspondence with the orthogonal code output from the orthogonal code generation unit 1. That is, as shown in FIG. 8, at time t1, the orthogonal code reading circuit 20 outputs a count signal to the address counter 22, and from the initial state, outputs an address t1 as a result of counting one count signal. Read bit array {1 (LSB), 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1 (MSB)} of the orthogonal code at address t 1 from the memory 21 .

Then, the orthogonal code reading circuit 20 writes the data of each bit of the read bit arrangement to each register of the storage register 23.
As a result, the column wiring driving unit 5 outputs a driving signal when the bit data of the bit arrangement is “1” and does not output a driving signal when the bit data is “0”. In the array, a drive signal is output to each of the column wirings C1, C3, C5, C7, C9, C11, C13, and C15 in the column wiring group 2, and the measurement data of the capacitances at a plurality of intersections are multiplexed.

Next, at time t2, the address t2 is output as a result of counting one count signal from the state at time t1, and the bit array {0 (LSB), 1, 1, 2 of the orthogonal code of the address t2 is output from the code memory 21. 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1 (MSB)} is read.
Then, the orthogonal code reading circuit 20 writes the data of each bit of the read bit arrangement to each register of the storage register 23 as at time t1.
As a result, the column wiring drive unit 5 outputs a drive signal to each of the column wirings C2, C3, C6, C7, C10, C11, C14, and C15 in the column wiring group 2 in the bit array of the orthogonal code at time t2. Multiplexed capacity measurement data at multiple intersections.

Hereinafter, the above-described operations are performed at times t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, and t15, so that the registers 231, 232, 233, 234, 235, and 236 are obtained. , 237, 238, 239, 2310, 2311, 2312, 2313, 2314, and 2315 are sequentially input from the code memory 21 with each bit of the bit arrangement of the orthogonal code of the address corresponding to each time. become.
Here, the data stored in each register 231, 232, 233, 234, 235, 236, 237, 238, 239, 2310, 2311, 2312, 2313, 2314, 2315 of the storage register 23 is the column wiring. It is supplied to driver circuits 51, 52, 53, 54, 55, 56, 57, 58, 59, 510, 511, 512, 513, 514, 515 in the drive unit 5, respectively. At the time t1 to t15, when the measurement process in which the capacities of a plurality of intersections are multiplexed is completed, it is one cycle of the fingerprint collection process in the present invention.

  Further, the column wiring drive unit 5 includes corresponding column wirings C1, C2, C5, C5, C5, C5, C5, C5, C5, C5, C5, C5, C5, C5, C5, C5, C5, C5, C5, C5, C5 In C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, and C15, based on the clock signal output from the timing control circuit 11, the drive pulse has a predetermined constant width. Driven by a drive pulse train (see FIG. 10C). At this time, the column wiring drive unit 5 outputs the drive pulse (predetermined voltage) when the bit data is “1” and the bit data is “0” in the case of the drive pulse train P1 corresponding to the bit string of the orthogonal code. In this case, the drive pulse is not output, and the ground potential is output to the column lines other than the column line outputting the drive pulse. Therefore, at the time t1, as described above, the wirings C1, C3, C5, C7, C9, C11, C13, and C15 are driven by the predetermined drive pulse of the drive pulse train P1. Each row wiring R1, R2, R3,... Has a total value of the capacitances of the capacitive sensors formed by the plurality of driven column wirings, that is, a capacitance value multiplexed by a bit arrangement of orthogonal codes. Will be connected.

At this time, as shown in FIG. 10B and FIG. 11A, the timing control circuit 11 has a time point just before the rising edge of each driving pulse of the driving pulse train for driving the column wiring and a slight falling edge. A reset signal is output to the charge amplifier circuit 6 at the previous time point, and, as shown in FIGS. 10 (d) and 11 (b), the sample / hold signal is supplied to the sample / hold circuit at a time point just before the reset signal. 7 is output.
Further, the timing control circuit 11 outputs N (N is the number of sample hold circuits 7) switching signals to the selector circuit 8 at intervals at which sample hold signals are sequentially input. Thus, as shown in FIG. 11 (c), each signal held in the sample hold circuits 7, 7... By one sample hold signal is sequentially selected until the next sample hold signal. To the A / D converter 9. Thus, the A / D converter 9 sequentially converts the measurement voltage in the detection signal for each row wiring into digital data at the timing of the A / D clock input from the decoding arithmetic circuit 10, and each row is used as the measurement data d1. It outputs to the decoding arithmetic circuit 10 for every line. Then, the decoding arithmetic circuit 10 writes the data string in the measurement data that is sequentially input to the internal memory for each row wiring.

Here, the operation of the charge amplifier circuit 6 will be described in detail. First, at time td1 slightly before time t1 shown in FIG. 10, when a reset signal is output from the timing control circuit 11, the analog switch 124 (MOS transistor, FIG. 5) is turned on, and the feedback capacitor Cf is discharged. The output OUT of the operational amplifier 121 is short-circuited with the inverting input terminal and becomes a reference potential. In addition, the row wiring connected to the inverting input terminal of the operational amplifier 121 also becomes the reference potential.
Next, when this reset signal is turned off, the output voltage of the operational amplifier 121 slightly rises due to feedthrough due to the gate parasitic capacitance of the analog switch 124 (see the symbol Fd after time td1 in FIG. 10A).

  At time t1, when a predetermined drive pulse corresponding to the bit pattern of the orthogonal code in the drive pulse train (drive pulse train P in (d) in FIG. 11) rises (inputs), the drive pulse is connected to the column wiring. The voltage value of the output OUT of the operational amplifier 121 is applied to the inverting input terminal of the operational amplifier 121 via the sensor element (capacitance Cs) at the intersection of the wirings and flows based on the voltage value of the driving pulse, as shown in FIG. As shown in the figure, it descends gradually.

Next, at time td2, the timing control circuit 11 outputs a sample hold signal (S / H signal) to the sample hold circuit 7. Thereby, the sample hold circuit 7 holds the measurement voltage Va output from the output OUT of the operational amplifier 121 in the charge amplifier circuit 6 at the time when the sample hold signal is input.
Next, at time td3, the timing control circuit 11 outputs a reset signal to the charge amplifier circuit 6 again. As a result, the output OUT of the operational amplifier 121 and the inverting input terminal are short-circuited, the feedback capacitor Cf is discharged, and the output OUT of the operational amplifier 121 returns to the reference potential. When the reset signal is turned off, the output voltage of the operational amplifier 121 slightly increases due to the feedthrough due to the gate parasitic capacitance of the analog switch 124 as in the case described above (reference Fd after time td3 in FIG. 10A). reference).

Next, at time td4, when the drive pulse in the drive pulse train P1 falls, the column wiring driven by the drive pulse and the sensor element (capacitance Cs) at the intersection of the row wiring are based on the voltage of the drive pulse. As a result, the output OUT of the operational amplifier 21 gradually rises.
Next, at time td5, the timing control circuit 11 outputs a sample hold signal to the sample hold circuit 7. Thereby, the sample hold circuit 7 holds (holds) the measurement voltage Vb of the output OUT of the operational amplifier 121 at the time when the sample hold signal is input.
Next, at time td6, the timing control circuit 11 outputs a reset signal to the charge amplifier circuit 6. As a result, the output OUT of the operational amplifier 121 and the inverting input terminal in the charge pump circuit 6 are short-circuited, the feedback capacitor Cf is discharged, and the output OUT of the operational amplifier 121 returns to the reference potential. Thereafter, the above operation is repeated.

In the measurement described above, the offset Vk due to the feedthrough current of the analog switch 124 is generated in the + direction regardless of whether the output OUT drops from the reference potential or rises. As in this embodiment, when the capacitance Cs to be detected is tens to hundreds of femtofarads, the offset due to this feedthrough cannot be ignored. In the above measurement,
-Va0 = -Va + Vk
Is a voltage proportional to the detection target capacitance Cs, but the measured voltage is Va, and this voltage Va includes an error Vk due to an offset.
Va = Va0 + Vk

Therefore, in this embodiment, the voltage Vb at the time of discharging the detection target capacitor Cs is also measured. Here, the voltage Vb0 = Vb-Vk
Is a voltage proportional to the capacitance Cs, and the measured voltage is Vb = Vb0 + Vk
It becomes. These measurement voltages Va and Vb are sequentially held by the sample and hold circuit 7, and then the held voltage is A / D converted by the A / D converter 9 for each of the measurement voltages Va and Vb. Store in the memory. In the decoding arithmetic circuit 10,
Vd = Vb-Va = (Vb0 + Vk)-(Vk + Va0) = Vb0-Va0
Thus, measurement data Vd corresponding to the measurement value not including the offset error, that is, the multiplexed capacitance value is obtained.

  As described above, the decoding arithmetic circuit 10 determines the difference between the output signal of the charge amplifier circuit 6 when the potential of the column wiring is raised and when the potential of the column wiring rises and falls at the rise and fall of a predetermined drive pulse in the drive pulse train. By taking this, the capacitance value of the sensor element can be measured in a state where there is no influence of feedthrough. Further, by providing the selector, the charge amplifier circuit 6 that requires measurement time can be measured in parallel in each column wiring, and the measurement speed of the entire sensor can be increased.

  Next, at time t2 (time before the rise of the driving pulse P by the bit arrangement of the orthogonal code corresponding to the address t2 in FIG. 11), the timing control circuit 11 outputs a clock to the orthogonal code generation unit 1. . Thus, in the orthogonal code generator 1, the address counter 22 outputs the address t2 in response to the count signal from the orthogonal code reading circuit 20, and the code memory 21 stores the bit array of the orthogonal code corresponding to the address t2 in the storage register 23. Output to. Therefore, in the storage register 23, in synchronization with the clock, a bit string {0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0 of the orthogonal code corresponding to the address t 2 is stored. 0, 1, 1} is written to the corresponding register.

  For this reason, as shown in FIG. 9, each of the registers 231, 232, 233, 234, 235, 236, 237, 238, 239, 2310, 2311, 2312, 2313, 2314, 2315 of the storage register 23 is stored. The data is the bit string {0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1}. The output of each register of the storage register 23 is the driver circuit 51, 52, 53, 54, 55, 56, 57, 58, 59, 510, 511, 512, 513, 514, 515 in the column wiring drive unit 5. Supplied to each. Therefore, when the time t2 ends, the bit string {0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1} of the orthogonal code is the column wiring drive The driver circuit 51, 52, 53, 54, 55, 56, 57, 58, 59, 510, 511, 512, 513, 514, 515 in the section 5 is supplied.

Next, at time t2, the column wiring drive unit 5 causes the driver circuits 51, 52, 53, 54, 55, 56, 57, 58, 59, 510, 511, 512, 513, 514, 515 to correspond to the corresponding columns. The wirings C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, and C15 are driven pulse trains (addresses) based on the clock pulses output from the timing control circuit 11. Driving is performed by a driving pulse having a predetermined constant width in the driving pulse train P2) corresponding to the bit arrangement of the orthogonal code corresponding to t2 (see FIGS. 10C and 11F). At the time t2, the column wirings C2, C3, C6, C7, C10, C11, C14, and C15 are driven (FIG. 9). The state at time t2 corresponds to the time t1 already described.
Then, at time t2 (that is, in the vicinity of time t2), the operation from time td1 to time td5 described above with reference to FIG. 10 is repeated, and a bit string of orthogonal codes is sequentially read from the code memory 21 and used. By driving the wiring, the capacitance values of the plurality of sensor elements are multiplexed, and a measurement voltage obtained by converting the multiplexed capacitance into a voltage value is obtained.
The processing described at time t1 and t2 is repeated from time td1 to time td5 shown in FIG. 10 at each timing corresponding to time t3 to time t15 (FIG. 23 shows storage registers at each time. 23, the bit arrangement of the orthogonal code of 23) is shown), reading from the code memory 21 of the orthogonal code, driving of the column wiring, and acquisition of the measurement voltage are repeated over one cycle from the memory address t1 to t15, Fingerprint acquisition processing is performed.

Then, the capacitance detection circuit 100 drives the plurality of column wirings of the column wiring group 2 by each of the drive pulse trains P1 to P15, sequentially reads out the 15-bit orthogonal codes in the above-described measurement processing from the code memory 21, and respectively Fifteen different measurement voltages Vd for each address t1 to t15 are obtained for each row wiring in time series. The A / D converter 9 converts this measurement voltage Vd into measurement data d in time series, and a data string {d1, d2,..., D15} of measurement data multiplexed with orthogonal codes is obtained.
Measurement data different for each of the 15 orthogonal codes for each row wiring is stored in the memory inside the decoding arithmetic circuit 10 as the following data.
d1 = Vs1 + Vs3 + Vs5 + Vs7 + Vs9 + Vs11 + Vs13 + Vs15
d2 = Vs2 + Vs3 + Vs6 + Vs7 + Vs10 + Vs11 + Vs14 + Vs15
d3 = Vs1 + Vs2 + Vs5 + Vs6 + Vs9 + Vs10 + Vs13 + Vs14
d4 = Vs4 + Vs5 + Vs6 + Vs7 + Vs12 + Vs13 + Vs14 + Vs15
・
・
・
d15 = Vs1 + Vs2 + Vs4 + Vs7 + Vs8 + Vs11 + Vs13 + Vs14

Here, Vs is voltage data (digital value) obtained by converting each capacitance of the sensor element at the intersection of each driven column wiring and row wiring into a voltage, and each measurement data d is driven based on an orthogonal code. Multiplexed by the capacitance of the sensor element corresponding to the column wiring.
When considered as a general formula, the following formula (1) is obtained.

In this equation, about half (eight) in the column wiring group 2 are simultaneously driven based on the orthogonal code, so that the integrated value of the voltage data Vsj corresponding to the capacitance Csj of the sensor elements at about half of the intersections. Is obtained as measurement data di. Here, “j” is the number of the column wiring C, “i” is the number of the measurement data (corresponding to the order of the addresses ti), and i = 1, 2, 3,..., N, j = 1, 2, 3, ..., N. That is, the code CD (i, j) in the equation (1) indicates the code of the j-th element in the i-th code used at the time ti.
Then, the decoding arithmetic circuit 10 obtains the voltage data Vs of each sensor element by the following equation (2) from the multiplexed measurement data and the orthogonal code used for multiplexing.

As described above, the orthogonal codes are sequentially read from the code memory 21, and the obtained time-series measurement data d is obtained by performing the product sum operation of the orthogonal codes and the measurement data d by the above equation (2). And voltage data ds corresponding to the capacitance of the sensor element at the intersection of the driven column wiring and the voltage data Vs.
Here, in the equation (2), when the bit data of the orthogonal code is CD (i, j) = 1, the coefficient CDs (i, j) = + 1 and when CD (i, j) = 0. , Coefficient CDs (i, j) = − 1.
The decoding operation circuit 10 performs an operation of separation from the measurement data d to the voltage data ds using the equation (2).

  That is, when obtaining the voltage data ds for each sensor element, that is, the voltage data {ds1, ds2, ds3,..., Ds14, ds15}, the voltage data ds is multiplexed by orthogonal codes in units of row wirings, and the data of the measurement data is obtained. Since the sequence {d1, d2, d3,..., D14, d15} is obtained, first, the bit sequence {1 (LSB), 0, 1, 0, 1, 0, 1, 0 of the orthogonal code for each measurement data di. , 1, 0, 1, 0, 1, 0, 1 (MSB)} is multiplied by the coefficient corresponding to the data CD (i, j) of each bit.

  Here, at the time of measurement, when a drive signal is applied to the column wiring based on a predetermined orthogonal code, the order of the bit strings sequentially corresponds to the order of each column wiring. For example, the LSB bit corresponds to the column wiring C1. The MSB bit corresponds to the column wiring C15. Next, the voltage data ds1 corresponding to the intersection of the column wiring C1 is the LSB bit string {1 (t1), 0 (t2), 1 (t3), 0 ( t4), 1 (t5), 0 (t6), 1 (t7), 0 (t8), 1 (t9), 0 (t10), 1 (t11), 0 (t12), 1 (t13), 0 ( t14), 1 (t15)}, the coefficient corresponding to the data CD (i, j) of each bit of this bit string is multiplied for each measurement data di and integrated over one period.

  That is, the column wiring C1 is driven corresponding to the data of the LSB (first bit) of the orthogonal code at the address t1 at time t1, as can be seen from the data of the orthogonal code bit for each time of FIG. Is driven corresponding to the LSB data of the orthogonal code at the address t2 at time t2, and so on, and driven at the time t15 corresponding to the data of the LSB bit of the orthogonal code at the address t15. Also, the coefficient for the corresponding orthogonal code bit data is multiplied for each measurement data and added.

Similarly, the voltage data dS2 corresponding to the intersection of the column wiring C2 is driven corresponding to the second bit data of the orthogonal code at the address t1 at the time t1, and the second bit of the orthogonal code at the address t2 at the time t2. ..,..., And is driven in correspondence with the second bit data of the orthogonal code at the address t15 at time t15. The corresponding coefficient is multiplied and added.
That is, the voltage data ds2 is a bit string {0 (t1), 1 (t2), 1 (t3), 0 (t4), 0 (t5) consisting of the second bit of the bit arrangement of each orthogonal code at addresses t1 to t15. , 1 (t6), 1 (t7), 0 (t8), 0 (t9), 1 (t10), 1 (t11), 0 (t12), 0 (t13), 1 (t14), 1 (t15) }, A coefficient corresponding to the data CD (i, j) of each bit of this bit string is multiplied for each measurement data di and integrated over one period.

As described above, the voltage corresponding to the capacitance of each crossing portion is a coefficient for the data CD (i, j) of each bit of the bit string corresponding to the data applied to the corresponding column wiring at time t1 to t15. Multiply every measurement data di and integrate over one period. This process corresponds to a product-sum operation on the orthogonal code. As shown below, the voltage data dSj corresponding to each intersection is measured data di and each bit arrangement of the orthogonal code stored in the code memory 21. It is obtained by the product-sum operation with the coefficient corresponding to the data.
That is, in the product-sum operation at the time of decoding, for each measurement data measured at each time, in the column wiring number of the intersection to be obtained and the bit array of the orthogonal code used at the time corresponding to this number The coefficients corresponding to the bit data of the number (order) are respectively multiplied and accumulated (that is, the bits of the orthogonal code used when driving the corresponding column wiring at each time during measurement) And the coefficient corresponding to the data of the same value is multiplied).

In the orthogonal code shown in FIG. 8 and stored in the code memory 21 corresponding to the 15 column wirings in the present embodiment, the decoding arithmetic circuit 10 uses (2) the bit arrangement of the orthogonal codes of the addresses t1 to t15. Based on the formula
ds1 = + d1-d2 + d3-d4 + d5-d6 + d7-d8 + d9-d10 + d11-d12 + d13-d14 + d15
ds2 = -d1 + d2 + d3-d4-d5 + d6 + d7-d8-d9 + d10 + d11-d12-d13 + d14 + d15
ds3 = + d1 + d2-d3-d4 + d5 + d6-d7-d8 + d9 + d10-d11-d12 + d13 + d14-d15
ds4 = -d1-d2-d3 + d4 + d5 + d6 + d7-d8-d9-d10-d11 + d12 + d13 + d14 + d15
・
・
・
ds15 = + d1 + d2-d3 + d4-d5-d6 + d7 + d8-d9-d10 + d11-d12 + d13 + d14-d15
And the voltage data dsj corresponding to the capacitance value of each sensor element is separated from the data string of the measurement data di.

  As described above, in the first embodiment, a plurality of column wirings are simultaneously driven based on the orthogonal code, and at the next timing, the orthogonal code of the address corresponding to the time is read from the code memory 21 and measured. On the other hand, the data obtained in time series on the detection side is subjected to product-sum operation processing with orthogonal codes, so that the influence from the intersection capacitance with other column wirings is almost averaged simultaneously It is possible to extract only the information on the charge / discharge of the sensor element (capacitance sensor) at the intersection with the target column wiring.

FIG. 12 is a block diagram showing a configuration example when the present embodiment is used for a line sensor.
In the sensor unit 4B of this line sensor, a line type sensor is configured by arranging the row wiring to be detected in one column.
Each configuration of the capacitance detection circuit is the same as that of the already described area type sensor except that the selector circuit 8 for selecting the row wiring for detecting the capacitance is not provided. .

This line type sensor has a smaller circuit scale than an area type sensor, and can reduce power consumption and cost.
When this line type sensor is used as a fingerprint sensor, the finger is swept at an angle substantially perpendicular to the row wiring, the timing control circuit 11 outputs each signal for measurement processing at a predetermined period, and the decoding arithmetic circuit 10 Detects the two-dimensional fingerprint data by connecting the measurement data in units of row wirings inputted every predetermined period.

Next, the second embodiment will be described with reference to FIG. 1, but the description of the same configuration and operation as those of the first embodiment will be omitted. Here, the column wiring group 2 has one more configuration than the first embodiment of the column wirings C1 to C16. In the capacity detection apparatus of the second embodiment, a matrix of 15 (rows) × 16 (columns) excluding the first row (address t1) in which all bits are logic “0” in the Walsh code of FIG. As an orthogonal code.
At this time, all the first columns are logic 0, which is inconvenient for multiplexing measurement data, so that the orthogonal code generator 1 inverts the output of each register of the storage register 23.
That is, an inverting circuit that inverts the logic of each bit data of the bit arrangement of the orthogonal code is added between the storage register 23 and the column wiring drive circuit 5, and the non-inverted orthogonal code, the inverted orthogonal code, and One of the following is output.

By outputting 15 (rows) × 16 (columns) in the non-inverted state and 15 (rows) × 16 (columns) subjected to inversion processing, orthogonal codes are combined, and logical “ The number of detection times “1” (15 times to correspond to orthogonal code rows) and the number of detection times “0” (15 times to correspond to orthogonal code rows) are the same.
Here, the number of detections of capacitance detection is 15 (rows) × 16 (columns) in a non-inverted state, 15 (rows) × 16 (columns) in which inversion processing is performed, and twice the number of rows as in the first embodiment. It becomes. A code table of the bit arrangement of orthogonal codes obtained as a result is shown in FIG. The data stored in the code memory 21 are odd addresses t1, t3, t5, t7, t9, t11, t13, t15, t17, t19, t21, t23, t25, t27, t29.

  14 and 15 includes addresses t1, t3, t5, t7, t9, t11, t13, t15, t17, t19, which are odd numbers output from the address counter 22. In the case of t21, t23, t25, t27, t29, the corresponding bit data of the code memory 21 is output, and even addresses t2, t4, t6, t8, t10, t12, t14, t16, t18, t20, In the case of t22, t24, t26, t28, t30, the bit data of the orthogonal code corresponding to the odd address read from the code memory 21 immediately before is inverted and output.

Next, a specific column wiring driving operation will be described with reference to FIGS.
At time t1, the column wiring drive unit 5 simultaneously drives a plurality of column wirings in the column wiring group 2 corresponding to the orthogonal code output from the orthogonal code generation unit 1. That is, as shown in FIG. 14, at time t1, the orthogonal code reading circuit 20B outputs a count signal to the address counter 22, and from the initial state, outputs the address t1 as a result of counting one count signal. Bit array of orthogonal code at address t1 from the memory 21 {0 (LSB), 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1 (MSB)} Is read.

Then, the orthogonal code reading circuit 20B writes the data of each bit of the read bit arrangement to each register of the storage register 23.
As a result, the column wiring drive unit 5 receives the bit sequence of the orthogonal code corresponding to the address t1 from the storage register 23 via the inverting circuit 24, so that the bit data of the bit sequence is “1”. Since the drive signal is output in the case of "0" and no drive signal is output in the case of "0", the column wirings C1, C3, C5, C7, C9, C11 in the column wiring group 2 in the bit array of the orthogonal code at the time t1. , C13, and C15 are each output with a drive signal, and the measurement data of the capacitance at a plurality of intersections is multiplexed. At this time, since the address is an odd number, the inverting circuit 24 outputs the data of the orthogonal code read from the address t 1 of the code memory 21 to the column wiring driving unit 5 without performing the inverting process.

Next, at time t2, the address t2 is output as a result of counting one count signal from the state at time t1, but the bit array of the orthogonal code at the address t1 is still read from the code memory 21. ing.
Then, the orthogonal code reading circuit 20B writes the data of each bit of the bit arrangement read from the code memory 21 by the address t1 to each register of the storage register 23, similarly to the time t1.
At this time, the inversion circuit 24 inverts each bit of the orthogonal code of the input address t1, and the bit array {1 (LSB), 0, 1, 0, 1, 0, 1, 0 of the even address t2. , 1, 0, 1, 0, 1, 0, 1, 0 (MSB)}.

Then, similarly to the time t1, the column wiring driving unit 5 outputs a driving pulse train (P2) for driving the column wiring corresponding to the read data of each bit in the bit arrangement.
Thereby, the column wiring drive unit 5 outputs a drive signal to each of the column wirings C2, C4, C6, C8, C10, C12, C14, C16 in the column wiring group 2 in the bit arrangement of the orthogonal code at the time t2. Multiplexed capacity measurement data at multiple intersections.

Hereinafter, the above-described operation is performed at times t3, t4, t5,..., T29, t30, thereby register 231, 232, 233, 234, 235, 236, 237, 238, 239, 2310, 2311, 2312, 2313. , 2314, 2315, and 2316 are sequentially input from the code memory 21 with each bit data of the bit array of the orthogonal code of the address corresponding to each time.
Here, the data stored in each register 231, 232, 233, 234, 235, 236, 237, 238, 239, 2310, 2311, 2312, 2313, 2314, 2315, 2316 of the storage register 23 is It is supplied to driver circuits 51, 52, 53, 54, 55, 56, 57, 58, 59, 510, 511, 512, 513, 514, 515, 516 in the column wiring drive section 5, respectively. At the time t1 to t30, when the measurement process in which the capacities of a plurality of intersections are multiplexed is completed, it is one cycle of the fingerprint collection process in the present invention.

Then, the capacitance detection circuit 100 drives a plurality of column wirings of the column wiring group 2 by each of the drive pulse trains P, and sequentially converts the 16-bit orthogonal code in the above-described measurement processing from the code memory 21 at odd addresses. At the read and even address, the orthogonal code data of the odd address read immediately before from the code memory 21 is inverted, and 30 measurement voltages Vd that differ for each address t1 to t30 are time-sequentially. Obtained for each row wiring. The measurement voltage Vd is converted to measurement data d by the A / D converter 9 in a time series, and the data string {d1, d2,..., D15,. Is obtained.
Measurement data different for each of the 30 orthogonal codes for each row wiring is stored in the memory inside the decoding arithmetic circuit 10 as the following data.
d1 = Vs2 + Vs4 + Vs6 + Vs8 + Vs10 + Vs12 + Vs16
d2 = Vs1 + Vs3 + Vs5 + Vs7 + Vs9 + Vs11 + Vs13 + Vs15
d3 = Vs3 + Vs4 + Vs7 + Vs8 + Vs11 + Vs12 + Vs15 + Vs16
d4 = Vs1 + Vs2 + Vs5 + Vs6 + Vs9 + Vs10 + Vs13 + Vs14
.
.
d29 = Vs2 + Vs3 + Vs5 + Vs8 + Vs9 +++ Vs12 + Vs14 + Vs15
d30 = Vs1 + Vs4 + Vs6 + Vs7 + Vs10 + Vs11 + Vs13 + Vs16

Here, Vsj (1 ≦ j ≦ 15, corresponding to the column wiring number) is voltage data (digital value) obtained by converting each capacitance of the sensor element at the intersection of each driven column wiring and row wiring into a voltage. Each measurement data d is multiplexed by the capacitance of the sensor element corresponding to the column wiring driven based on the orthogonal code.
In the already-described expression (1), half (eight) in the column wiring group 2 are simultaneously driven based on the orthogonal code, so that the integration of the voltage data Vsj corresponding to the capacitance Csj of the sensor element at the half of the intersection is performed. The obtained value is obtained as measurement data di. Here, “j” is the number of the column wiring C, “i” is the number of the measurement data (corresponding to each order of the address ti), i = 1, 2, 3,..., J = 1, 2, 3, and so on.
Then, the decoding arithmetic circuit 10 obtains the voltage data Vs of each sensor element by the equation (2) from the multiplexed measurement data and the orthogonal code used for multiplexing.

As described above, the orthogonal codes are sequentially read from the code memory 21 in the case of odd addresses, and the orthogonal code data corresponding to the previous odd address is inverted and multiplexed in the case of even addresses. The obtained time-series measurement data d corresponds to the capacitance of the sensor element at the intersection of the row wiring and the driven column wiring by the product-sum operation of the orthogonal code and the measurement data d according to the above equation (2). Voltage data ds, that is, voltage data Vs can be separated.
In this equation (2), as in the first embodiment, when the bit data of the orthogonal code is CD (i, j) = 1, CDs (i, j) = + 1, and CD ( When i, j) = 0, CDs (i, j) =-1.
The decoding operation circuit 10 performs an operation of separation from the measurement data d to the voltage data ds using the equation (2).

  That is, when obtaining the voltage data ds for each sensor element, that is, the voltage data {ds1, ds2, ds3,..., Ds14, ds15}, the voltage data ds is multiplexed by orthogonal codes in units of row wirings, and the data of the measurement data is obtained. Since the sequence {d1, d2, d3,..., D14, d15} is obtained, first, the bit sequence {0 (LSB), 1, 0, 1, 0, 1, 0, 1 of the orthogonal code for each measurement data di. , 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1 (MSB)} The bit data CD (i, j) is multiplied as a coefficient.

  Here, the order of the bit columns sequentially corresponds to the order of the column wirings. For example, the LSB bit corresponds to the column wiring C1, and the MSB bit corresponds to the column wiring C15. Next, the voltage data ds1 corresponding to the intersection of the column wiring C1 is the LSB bit string {0 (t1), 1 (t2), 0 (t3), 1 ( t4), 0 (t5), 1 (t6), 0 (t7), 1 (t8), 0 (t9), 1 (t10), 0 (t11), 1 (t12), 0 (t13), 1 ( t14), 0 (t15), 1 (t16, 0 (t17), 1 (t18), 0 (t19), 1 (t20), 0 (t21), 1 (t22), 0 (t23), 1 (t24 ), 0 (t25), 1 (t26), 0 (t27), 1 (t28), 0 (t29), 1 (t30)}, and the data CD (i, j) of each bit of this bit string as a coefficient Multiply every measurement data di and integrate over one period.

  That is, the column wiring C1 is driven corresponding to the data of the LSB (first bit) of the orthogonal code at the address t1 at time t1, and is driven corresponding to the LSB data of the orthogonal code at the address t2 at time t2. ..,... Are driven corresponding to the LSB bit data of the orthogonal code at the address t30 at the time t30, so that in the product-sum operation, the corresponding orthogonal code bit data is multiplied and added. Become.

Similarly, the voltage data dS2 corresponding to the intersection of the column wiring C2 is driven corresponding to the second bit data of the orthogonal code at the address t1 at the time t1, and the second bit of the orthogonal code at the address t2 at the time t2. ,..., And at the time t30, the data is driven corresponding to the second bit data of the orthogonal code at the address t30. Multiply and add.
That is, the voltage data ds2 is a bit string {1 (t1), 0 (t2), 1 (t3), 0 (t4), 1 (t5) composed of the second bit of the bit arrangement of each orthogonal code at addresses t1 to t15. , 0 (t6), 1 (t7), 0 (t8), 1 (t9), 0 (t10), 1 (t11), 0 (t12), 1 (t13), 0 (t14), 1 (t15) 0 (t16, 1 (t17), 0 (t18), 1 (t19), 0 (t20), 1 (t21), 0 (t22), 1 (t23), 0 (t24), 1 (t25), 0 (T26), 1 (t27), 0 (t28), 1 (t29), 0 (t30)}, the data CD (i, j) of each bit of this bit string is used as a coefficient and multiplied for each measurement data di Accumulate over one cycle.

  As described above, the voltage corresponding to the capacitance of each intersection is obtained by using the data CD (i, j) of each bit of the bit string corresponding to the data applied to the corresponding column wiring at the time t1 to t30 as a coefficient. Multiply every measurement data di and integrate over one period. This process corresponds to a product-sum operation on orthogonal codes. As shown below, voltage data dSj corresponding to each intersection is obtained by measuring data di and the bit array of each orthogonal code stored in the code memory 21. It is obtained by multiply-accumulate with data.

In the orthogonal code shown in FIG. 13 corresponding to the 16 column wirings in the present embodiment and stored in the code memory 21 or inverted, the decoding arithmetic circuit 10 uses the bit arrangement of the orthogonal codes at the addresses t1 to t30. Is based on equation (2)
ds1 = -d1-d3-d5-d7-d9-d11-d13-d15-d17-d19-d21-d23-d25-d27-d29 + d2 + d4 + d6 + d8 + d10 + d12 + d14 + d16 + d18 + d20 + d22 + d24 + d26 + d28 + d30
ds2 = d1-d3 + d5-d7 + d9-d11 + d13-d15 + d17-d19 + d21-d23 + d25-d27 + d29-d2 + d4-d6 + d8-d10 + d12-d14 + d16-d18 + d20-d22 + d24-d26 + d28-d30
ds3 = -d1 + d3 + d5-d7-d9 + d11 + d13-d15-d17 + d19 + d21-d23-d25 + d27 + d29 + d2-d4-d6 + d8 + d10-d12-d14 + d16 + d20-d22 + d24 + d26-d28-d30
・
・
・
ds15 = d1 + d3-d5 + d7-d9-d11 + d13 + d15-d17-d19 + d21-d23 + d25 + d27-d29-d2-d4 + d6-d8 + d10 + d12-d14-d16 + d18 + d20-d22 + d24-d26-d28 + d30
And the voltage data dsj corresponding to the capacitance value of each sensor element is separated from the data string of the measurement data di.

  As described above, in the first embodiment, a plurality of column wirings are simultaneously driven based on the orthogonal code, and at the next timing, the orthogonal code of the address corresponding to the time is read from the code memory 21 and measured. On the other hand, the data obtained in time series on the detection side is subjected to product-sum operation processing with orthogonal codes, so that the influence from the intersection capacitance with other column wirings is almost averaged simultaneously It is possible to extract only the information on the charge / discharge of the sensor element (capacitance sensor) at the intersection with the target column wiring.

In the first and second embodiments, the description has been given of the multiplexed measurement of the capacitance of the sensor element formed at the intersection of the column wiring and the row wiring as shown in FIG. However, in the third embodiment, a configuration when applied to the sensor unit 4C which is an active matrix sensor shown in FIG. 16 will be described.
A bit string of a predetermined orthogonal code is input from the orthogonal code generator 1 to the column wiring drive circuit 5, drives a plurality of column wirings in the column wiring group 2, and the capacity of the unit capacity cell 70 (sensor element) in units of row wiring. The fifth embodiment is the same as the first and second embodiments in that they are multiplexed. The capacitance detection circuit 200 is similar in configuration and operation to the first and second embodiments, but the charge amplifier circuit 6 is replaced with a charge amplifier circuit 72 shown in FIG. The capacitance detection circuit 200 has the same configuration except that the charge amplifier circuit is replaced.

The charge amplifier circuit 72 has the configuration shown in FIG. 17, and the same components as those of the charge amplifier circuit 6 are denoted by the same reference numerals. Since the measurement method of the active matrix sensor is slightly different, only the measurement operation in which the charge amplifier circuit 72 is different from the charge amplifier circuit 6 will be described.
Before measuring the fingerprint data, the switch 73 is turned off, the switch 74, the switch 124, and the cell selection switch 71 connected to the plurality of column wirings corresponding to the bit 1 are turned on, and the unit capacity cell 70 (capacitance Cs) The charge is accumulated until the parasitic capacitance CD becomes the voltage Vc, and all the switches are temporarily turned off.

  In the measurement of fingerprint data, when the switch 73 and the cell selection switch 71 are turned on at the same time while the switch 74 and the switch 124 are kept in the off state, each unit capacity cell 70 is placed on the sensor unit 4C. Therefore, a voltage corresponding to the sum of the charges generated by the voltage difference between the voltage Vc and the reference voltage Vref is generated at the output terminal of the operational amplifier 121, and this is used as measurement data d of the decoding arithmetic circuit 10. Stored in internal memory. Multiplexed measurement data strings di are obtained by repeating this sequence of charge accumulation and detection voltage measurement. Then, the decoding operation circuit 10 obtains voltage data ds corresponding to the capacity Cs of each unit capacity cell 70 from the data string of the measurement data d stored in the internal memory by the operation of the decoding process already described.

  In each of the first to third embodiments, a program for realizing the function of the decoding arithmetic circuit 10 in FIG. 1 is recorded on a computer-readable recording medium, and the program recorded on the recording medium is recorded. May be calculated by decoding the voltage data dsj corresponding to the capacitance of each sensor element from the data string of the measurement data di multiplexed by reading into the computer system. Here, the “computer system” includes an OS and hardware such as peripheral devices. The “computer system” includes a WWW system having a homepage providing environment (or display environment). The “computer-readable recording medium” refers to a storage device such as a flexible medium, a magneto-optical disk, a portable medium such as a ROM and a CD-ROM, and a hard disk incorporated in a computer system. Further, the “computer-readable recording medium” refers to a volatile memory (RAM) in a computer system that becomes a server or a client when a program is transmitted via a network such as the Internet or a communication line such as a telephone line. In addition, those holding programs for a certain period of time are also included.

  The program may be transmitted from a computer system storing the program in a storage device or the like to another computer system via a transmission medium or by a transmission wave in the transmission medium. Here, the “transmission medium” for transmitting the program refers to a medium having a function of transmitting information, such as a network (communication network) such as the Internet or a communication line (communication line) such as a telephone line. The program may be for realizing a part of the functions described above. Furthermore, what can implement | achieve the function mentioned above in combination with the program already recorded on the computer system, and what is called a difference file (difference program) may be sufficient.

It is a block diagram which shows the structure of the fingerprint sensor using the capacity | capacitance detection circuit by the 1st Embodiment of this invention. It is a conceptual diagram which shows the structural example of the sensor part 4 in FIG. It is a conceptual diagram explaining the measurement of the fingerprint data using the sensor part 4 in FIG. 5 is a conceptual diagram illustrating a configuration example of a sensor element 55 formed at each intersection of a column wiring of the column wiring group 2 and a row wiring of the row wiring group 3 in the sensor unit 4 of the area sensor type. FIG. FIG. 2 is a conceptual diagram illustrating a configuration example of a sensor unit 4 and a charge amplifier circuit 6 in FIG. 1. It is a conceptual diagram explaining the procedure which produces | generates the Walsh code which is an orthogonal code. It is a figure which shows the table of the Walsh code memorize | stored in the code memory 21 in FIG.8 and FIG.9. FIG. 5 is a conceptual diagram for explaining an operation example of the first embodiment of the present invention in which column wiring is driven by orthogonal codes and the capacitance of the sensor element 55 is multiplexed. FIG. 5 is a conceptual diagram for explaining an operation example of the first embodiment of the present invention in which column wiring is driven by orthogonal codes and the capacitance of the sensor element 55 is multiplexed. 5 is a timing chart for explaining the detection signal and the operation of the charge amplifier circuit 6 in the first embodiment. 6 is a timing chart for explaining the operation of controlling the selector and the column wiring in the first embodiment. It is a block diagram which shows the structural example at the time of using 1st Embodiment for a line sensor. It is a table which shows the bit arrangement | sequence of Walsh code in 2nd Embodiment. It is a conceptual diagram for demonstrating the operation example of the 2nd Embodiment of this invention which drives column wiring by an orthogonal code and multiplexes the capacity | capacitance of the sensor element 55. FIG. It is a conceptual diagram for demonstrating the operation example of the 2nd Embodiment of this invention which drives column wiring by an orthogonal code and multiplexes the capacity | capacitance of the sensor element 55. FIG. It is a conceptual diagram which shows the structural example of the active matrix type sensor in 3rd Embodiment. It is a block diagram which shows the structure of the charge amplifier circuit 72 in 3rd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Orthogonal code generation part 2 ... Column wiring group 3 ... Row wiring group 4, 4B ... Sensor part 5 ... Column wiring drive part 6, 72 ... Charge amplifier circuit 7 ... Sample hold circuit 8 ... Selector circuit 9 ... A / D conversion 10: Decoding arithmetic circuit 11 ... Timing control circuit 20, 20B ... Orthogonal code reading circuit 21 ... Code memory 22 ... Address counter 23 ... Storage register 24 ... Inverting circuit 50 ... Substrate 51 ... Insulating film 52 ... Air gap 54 ... Film 100 ... Capacitance detection circuit

Claims (7)

A capacitance detection circuit that detects a change in capacitance at an intersection between a column wiring and a row wiring in a capacitance sensor configured by intersecting row wiring with respect to a plurality of column wirings.
Orthogonal code generating means for generating an orthogonal code, changing the orthogonal code in a time series, and outputting it as a column drive signal;
Column wiring driving means for selecting and driving a plurality of column wirings in the column wiring corresponding to the column driving signal;
Capacitance detecting means connected to the row wiring and converting the sum of the capacitance changes of the intersections corresponding to the selected column wiring into a voltage signal and outputting it as a detection voltage;
A decoding calculation circuit for decoding a data string of detection voltages output in time series from the capacitance detection means by a predetermined calculation based on the orthogonal code, and separating a voltage corresponding to a capacitance change at each of the intersections; A capacitance detection circuit comprising:   2. The capacitance detection circuit according to claim 1, wherein a capacitance of the intersecting portion of an area-type capacitance sensor in which a plurality of the row wirings are arranged in a matrix is detected with respect to the plurality of column wirings.   2. The capacitance detection circuit according to claim 1, wherein a capacitance of the intersecting portion of a line-type capacitance sensor in which one row wiring is formed corresponding to the plurality of column wirings is detected. In the Walsh code generated by the orthogonal code generating means as a 2 n matrix, (2 ⁿ −1) × (2) excluding the portions where all columns are logical “0” and all rows are logical “0”. Supply (2 ⁿ -1) orthogonal codes in time series to the column wiring driving means for each of the column wirings of (2 ⁿ -1) columns or less with the ( ⁿ -1) matrix as an orthogonal matrix. The capacitance detection circuit according to claim 1, wherein In the Walsh code generated by the orthogonal code generation means as a 2 n matrix, a (2 ⁿ −1) × (2 ⁿ ) matrix in which all the columns are excluded from the logic “0” is an orthogonal matrix, 4. The (2 ⁿ −1) orthogonal codes are supplied to the column wiring driving means in time series for each of the column wirings of (2 ⁿ ) columns or less. The capacitance detection circuit according to any one of the above.   A fingerprint sensor comprising the capacitance detection circuit according to claim 1. A capacitance detection method for detecting a change in capacitance at an intersection between a column wiring and a row wiring in a capacitance sensor composed of a plurality of column wirings and a plurality of row wirings.
A process of generating an orthogonal code by the orthogonal code generating means, changing the orthogonal code in a time series, and outputting as a column drive signal;
A step of selecting and driving a plurality of column wirings in the column wiring in response to the column driving signal by a column wiring driving means;
A step of converting a sum of changes in capacitance of each of the intersections corresponding to the selected column wiring to a voltage signal by the capacitance detection means, and outputting as a detection voltage;
A decoding calculation circuit decodes a data string of detection voltages output in time series from the capacity detection means by a predetermined calculation based on the orthogonal code, and separates a voltage corresponding to a capacitance change at each of the intersections. A capacity detection method comprising:

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