JP2005109260A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device, capable of a conductor film or the like from being exfoliated, when embedding the conductor film or the like to a gate trench or the like. <P>SOLUTION: The manufacturing method of the semiconductor device includes the steps of: forming an element isolation region 103 to a first region on the semiconductor substrate 101; forming an element-forming region 102 to a second region; forming a dummy pattern 107 on the element-forming region 102; introducing impurity to form a diffusion layer, by using the dummy pattern 107 as a mask; depositing a first insulating material 109 and leveling the material 109, until the upper part of the dummy pattern 107 is exposed; removing the dummy pattern 107 to form a trench part 110; and depositing first conductive materials 112, 114 on the semiconductor substrate 101 so as to bring a tensile stress of the film to 500 MPa or lower, embedding the first conductive materials 112, 114 to the trench part 110 and forming a wiring pattern 116. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a transistor in which a refractory metal is used for a gate electrode and a gate electrode is formed by a filling method.

  In recent years, semiconductor devices have been highly integrated and increased in speed. In particular, reducing the resistance of the gate electrode plays an important role in achieving high speed in miniaturization of MOS transistors. In the generation of transistors with a gate length of 100 nm or less, the gate resistance of the polycrystalline silicon gate electrode normally used is high, and the depletion layer is formed on the gate electrode side, so that the effective insulating film thickness is thick, and as a result As a result, transistor characteristics such as short channel effect and reduction of drain current are deteriorated.

  One solution to the problem of reducing the resistance of the gate electrode is to reduce the resistance of the gate electrode by forming a conductive material such as a refractory metal through a barrier metal. When a metal material is used as the conductive material for the gate electrode, the gate electrode is formed using a so-called damascene gate process because of problems such as self-alignment and heat resistance against a high temperature heat treatment process.

  As a conventional method for manufacturing a semiconductor device, a method for manufacturing a complementary MOS transistor (CMOS) in which a refractory metal is used for a gate electrode and a gate electrode is formed by a buried method will be described in detail below.

  First, as shown in FIG. 12A, a thick silicon oxide film is formed in an arbitrary region of a normal semiconductor substrate 901, and an element formation region 902 and an element isolation region 903 are formed. This element isolation step is performed using, for example, an STI (Shallow Trench Isolation) method. In the case of forming a CMOS transistor, desired impurities are introduced by an ion implantation method, and n-type or p-type wells are formed in the semiconductor substrate 901. Next, the surface of the element formation region 902 is oxidized to form a thin buffer oxide film 904.

  Next, as shown in FIG. 12B, a polycrystalline silicon 905 and a silicon nitride film 906 are sequentially stacked as a dummy gate material. The film thickness is about 200 nm and 50 nm, respectively. Next, a resist (not shown) is applied to form a resist film, and a resist pattern is formed using a lithography technique in which exposure and development are performed. FIG. 15 shows a top view of the entire surface of the wafer including the semiconductor substrate 901. As shown in FIG. 15, in the case where transistors are formed on a plurality of chips 1102 on the wafer 1101, the resist pattern is formed on the entire surface of the wafer including a region 1103 on the periphery of the wafer where a drivable transistor is not formed. Subsequently, as shown in FIG. 12B, anisotropic etching such as RIE is performed using the resist pattern (not shown) as a mask, and the silicon nitride film 906 and the polycrystalline silicon 905 are etched to thereby form a dummy gate 907. Form. Next, using the dummy gate 907 as a mask, impurities such as As and B are introduced by ion implantation, and activation annealing is performed to form source / drain diffusion regions.

  Next, as shown in FIG. 12 (c), after forming a sidewall protective film 908 made of a silicon nitride film, ion implantation of impurities is performed using the sidewall protective film 908 as a mask, followed by activation annealing, thereby Form a region.

Next, as shown in FIG. 13D, for example, a TEOS film is deposited on the entire surface of the wafer by about 280 nm to form a first interlayer insulating film 909. Subsequently, the first interlayer insulating film 909 is planarized by etching using CMP (Chemical Mechanical Polishing) until the upper surface of the dummy gate 907 is exposed.

  Next, as shown in FIG. 13 (e), the exposed silicon nitride film 906 and the polycrystalline silicon 905 of the dummy gate 907 are sequentially removed using thermal phosphoric acid treatment and CDE (Chemical Dry Etching). Thus, the dummy gate 907 is removed and a gate groove 910 is formed. Subsequently, after the buffer oxide film 904 is removed with dilute hydrofluoric acid, a gate insulating film 911 is formed. The gate insulating film 911 can be used as a gate insulating film by forming a silicon oxide film by oxidizing the exposed surface of the semiconductor substrate 901.

  As shown in FIG. 13 (f), after the gate insulating film 911 is formed, TiN913 is formed as the barrier metal 912 over the entire surface. The film thickness is, for example, about 10 nm. Subsequently, tungsten 915, which is a refractory metal, is formed on the entire surface as a metal material 914 with a thickness of about 250 nm. The wafer temperature at the time of film formation of tungsten 915 is about 400 ° C., and the flow ratio WF6 / (WF6 + H2) of WF6 and H2, which is the source gas at the time of film formation, is about 0.1. Next, the tungsten 915 and the TiN 913 are etched and planarized by using a CMP method, and the gate electrode 916 is formed by embedding in the gate groove 910.

  Next, as shown in FIG. 13 (g), after forming a second interlayer insulating film 917 on the entire surface of the gate electrode 916 and the first interlayer insulating film 909, the gate electrode 916 and the source / drain regions A contact hole for forming a contact is formed by anisotropic etching. Next, a Ti / TiN / Al laminated film is deposited, etched into a desired shape, and a wiring electrode 918 is formed, thereby forming a CMOS transistor. A manufacturing method of this type of semiconductor device is described in Patent Document 1.

  In the manufacturing method of the semiconductor device, the TiN913, which is the barrier metal 912 of the gate electrode 916, is formed by the sputtering method. When the device is configured as a device, the transistor characteristics such as the gate voltage vary. Further, there is a problem that the gate insulating film 911 is seriously damaged by forming the TiN913 by sputtering using molecules having high ion energy.

That is, when TiN molecules are deposited on the gate insulating film with high ion energy, as shown in FIG. 13 (f) and FIG. 13 (g), TiN molecules enter the gate insulating film 911 and effective gate insulation is achieved. Since the film thickness of the film 911 becomes small or causes a conductive state, there are problems such as an increase in leakage current due to a decrease in breakdown voltage and an inability to control the source / drain current. Therefore, the above-described problem can be solved by forming the TiN913, which is the barrier metal 912, by the CVD method.
Japanese Patent Laid-Open No. 11-243150 (FIG. 4)

However, TiN913, which is a barrier metal 912 formed by a CVD method, has a problem that it does not enter the gate insulating film 911 and has poor adhesion to the base. Further, the first layer TiN913 formed by the CVD method has the same tensile stress (stress toward the center of the groove) as that of the second layer tungsten 915 used as the metal material 914. Has a large tensile stress of 1 Gpa or more, which causes a problem of film peeling as shown in FIG. However, the arrows in FIG. 14 indicate the tensile stress of the film. Therefore, when the film is peeled off, a device having a predetermined function cannot be formed, and the yield is reduced. In addition, this film peeling is particularly problematic because it occurs with a lower film stress when embedded in a groove such as a damascene gate structure than when it is deposited on the entire wafer surface without a groove.

  In the prior art, a dummy gate is also formed in a region where a transistor that can be driven originally is not formed on the peripheral edge of the wafer. However, as shown in FIG. In the CMP process in which the material is buried and flattened, the pressure from the pad is large in the CMP process. When film peeling occurs during the CMP process, the peeled barrier metal or metal material adheres to and contaminates other areas as the wafer rotates, yielding damage when configured as a device. descend.

  The present invention has been made to solve the above problems, and in particular, it is possible to prevent film peeling when a material such as a conductive material is embedded in a groove such as a gate groove such as a damascene gate structure. A first object is to provide a method for manufacturing a semiconductor device. It is a second object of the present invention to provide a method for manufacturing a semiconductor device that can prevent film peeling even at the wafer periphery where film peeling is more likely to occur.

One aspect of a method for manufacturing a semiconductor device of the present invention that achieves one of the above-described objects is as follows.
Forming an element isolation region in the first region on the semiconductor substrate;
Forming an element formation region in a second region other than the element isolation region;
Forming a dummy pattern by patterning a film on a part of the element formation region; and impurities of a carrier type opposite to the semiconductor substrate on the surface of the element formation region, using the dummy pattern as a mask. Introducing using and forming a diffusion layer;
Depositing a first insulating material on the semiconductor substrate and the dummy pattern, and planarizing until the upper portion of the dummy pattern is exposed;
Removing the dummy pattern and forming a groove;
Depositing the first conductive material in the groove so that the tensile stress of the film is 500 MPa or less and planarizing the first conductive material in the groove to form a wiring pattern When,
Depositing a second insulating material on the first insulating material and the wiring pattern; and
Forming an opening so as to expose the surface of the diffusion layer and the wiring pattern, and forming a contact by forming a second conductive material in the opening; and
It is characterized by comprising.

  According to the present invention, even when a material such as a conductive material is embedded in a gate groove having a depth of about 250 nm or a groove whose shape is not particularly limited, such as a damascene gate structure, film peeling is prevented. can do. Further, it is possible to prevent film peeling in the wafer peripheral region where film peeling is more likely to occur.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(First embodiment)
In this embodiment, a method for manufacturing a complementary MOS transistor (CMOS) in which a refractory metal is used for a gate electrode and the gate electrode is formed by a filling method will be described.

First, as shown in FIG. 1A, a thick silicon oxide film is formed in an arbitrary region of a normal semiconductor substrate 101, and an element formation region 102 and an element isolation region 103 are formed. This element isolation step is performed using, for example, STI (Shallow Trench Isolation) or LOCOS (Local Oxidation of Silicon) method. In the case of forming a CMOS transistor, desired impurities are introduced by an ion implantation method, and n-type or p-type wells are formed in the semiconductor substrate 101 to form an nMOS formation region and a pMOS formation region. If necessary, impurities are ion-implanted into a desired region on the element formation region 102, and the threshold concentration is adjusted by adjusting the impurity concentration of the channel portion of the transistor. Note that channel ion implantation is usually performed in a process before the formation of the gate electrode. However, in this embodiment mode, impurities can be ion-implanted after the gate groove is formed; . Next, the surface of the element formation region 102 is oxidized to form a thin buffer oxide film 104.

  Next, as shown in FIG. 1B, a polycrystalline silicon 105 and a silicon nitride film 106 are sequentially stacked as a dummy gate material. The second layer silicon nitride film is used as a stopper during etching. The film thickness is about 200 nm and 50 nm, respectively. This dummy gate, which is a dummy pattern, needs to be removed at a later step to form a trench, and a conductive material is buried in the trench, and is preferably formed at a height of about 100 nm to 350 nm. . Next, a resist is applied to form a resist film (not shown), and a resist pattern is formed using a lithography technique for performing exposure and development. Next, anisotropic etching such as RIE is performed using the resist pattern (not shown) as a mask, and the silicon nitride film 106 and the polycrystalline silicon 105 are etched to form a dummy gate 107. Subsequently, using the dummy gate 107 as a mask, impurities such as As and B are introduced by ion implantation, and activation annealing is performed to form source / drain diffusion regions.

  Next, as shown in FIG. 1 (c), after forming a sidewall protective film 108 made of a silicon nitride film on the dummy gate 107, ion implantation of impurities is performed using this as a mask, and activation annealing is performed, thereby performing source / drain Form a region.

  Next, as shown in FIG. 2D, for example, a TEOS film is deposited on the entire surface of the wafer by about 280 nm to form a first interlayer insulating film 109. Subsequently, the first interlayer insulating film 109 is planarized by etching using CMP (Chemical Mechanical Polishing) until the upper surface of the dummy gate 107 is exposed.

  Next, as shown in FIG. 2 (e), by using thermal phosphoric acid treatment and CDE (Chemical Dry Etching), the exposed silicon nitride film 106 of the dummy gate 107 and the polycrystalline silicon 105 are sequentially removed. Then, the dummy gate 107 is removed, and a gate groove 110 is formed. Subsequently, after removing the buffer oxide film 104 with dilute hydrofluoric acid, a gate insulating film 111 is formed. The gate insulating film 111 may be formed by depositing a high dielectric film such as tantalum oxide, or a silicon oxide film is formed by oxidizing the exposed surface of the semiconductor substrate 101 and used as a gate insulating film. Also good.

  Next, as shown in FIG. 2 (f), after the gate insulating film 111 is formed, titanium nitride (TiN) 113 is formed as a barrier metal 112 over the entire surface by CVD. The film thickness is, for example, about 10 nm. Subsequently, tungsten (W) 115, which is a refractory metal, is formed on the entire surface as a metal material 114 to a thickness of about 250 nm.

  At this time, the tensile stress of the film during the W film formation is suppressed to 500 MPa or less. In particular, as shown in the present embodiment, when the conductive material embedded in the gate groove 110 is a laminated film of TiN and W, as shown in FIG. 3, the wafer temperature during W film formation is 500 ° C. or more. Alternatively, the flow ratio WF6 / (WF6 + H2) of WF6 and H2, which is a source gas during film formation, is set to 0.05 or less. If the flow ratio WF6 / (WF6 + H2) between WF6 and H2 is lowered, defects such as seams are likely to occur in the conductive material embedded in the gate groove, so the flow ratio WF6 / (WF6 + H2) between WF6 and H2. ) Is preferably 0.025 or more.

  Subsequently, the W115 and the TiN 113 are etched and planarized by using a CMP method, and the gate electrode 116 is formed by embedding the gate groove 110.

  Next, as shown in FIG. 2 (g), after the second interlayer insulating film 117 is formed on the entire surface of the gate electrode 116 and the first interlayer insulating film 109, the gate electrode 116 and the source / drain regions are formed. A contact hole for forming a contact is formed by anisotropic etching. Next, a laminated film of Ti / TiN / Al is deposited and etched into a desired shape to form a wiring electrode 118, thereby forming a CMOS transistor.

  According to the present embodiment, as shown in FIG. 4, when the groove depth is about 250 nm, the larger the groove diameter, the easier the film peels off, but the film tensile stress during film formation is 500 MPa or less. By suppressing the thickness of the gate groove 110, the film is not limited to the conductive material embedded in the gate groove 110, and peeling of the film can be prevented. The arrows in FIG. 4 indicate the tensile stress of the film.

  In particular, when the conductive material embedded in the groove is a laminated film of TiN and W, the wafer temperature during W film formation is set to 500 ° C. or higher, or the flow rate ratio of WF6 and H2 that are source gases during film formation By setting WF6 / (WF6 + H2) to 0.05 or less, the tensile stress of the film during film formation can be suppressed to 500 MPa or less, it becomes possible to prevent film peeling, and the yield can be further improved. it can.

(Second embodiment)
In the present embodiment, a method of manufacturing a complementary MOS transistor (CMOS) in which a refractory metal is used for the gate electrode and the gate electrode is formed by a burying method will be described, as in the first embodiment. Detailed description of the same parts as those in the first embodiment will be omitted. Since the steps up to the step of forming the gate insulating film are the same as those in the first embodiment, detailed description thereof is omitted.

  As shown in FIGS. 1 (a) to 2 (e), after forming the gate insulating film 111, as shown in FIG. 2 (f), TiN 113 is formed as a barrier metal 112 on the entire surface using the CVD method. . The film thickness is, for example, about 10 nm. Subsequently, W115, which is a refractory metal, is deposited as a metal material 114 as thin as 100 nm on the entire wafer surface by the CVD method, and further deposited on the upper surface by about 150 nm by the sputtering method.

  Next, similarly to the first embodiment described above, the gate electrode 116 is formed by etching and planarizing the W115 and the TiN 113 using the CMP method and embedding them in the gate groove 110. Thereafter, as shown in FIG. 2G, steps such as formation of the second interlayer insulating film 117, formation of contact holes, formation of the wiring electrodes 118, and the like are performed to form a CMOS transistor.

  In the present embodiment, the film stress of the gate electrode formed by the stacked W115 is, as shown in FIG. 5, the first layer W115a formed by the CVD method is tensile stress, The second layer W115b formed by sputtering is a compressive stress in the direction opposite to the tensile stress. Accordingly, as shown in FIG. 5, the tensile film stress in the entire W115a, 115b film is reduced, and the film can be prevented from peeling off. However, the arrows in FIG. 5 indicate the tensile stress of the film and the compressive stress in the direction opposite to the tensile stress. The first layer W115a may be formed by sputtering, but it is not preferable because the W115a may penetrate the barrier metal 112 and damage the gate insulating film 111. Further, the shape of the groove and the conductive material embedded in the groove are not particularly limited.

According to this embodiment, a film having a tensile stress and a film having a compressive stress can be formed by forming a film using a CVD method and a sputtering method, and the tensile stress of the laminated film can be reduced. In addition, it is possible to provide a method for manufacturing a semiconductor device that can prevent film peeling and can further improve the yield. The deposition by the CVD method and the deposition by the sputtering method may be performed a plurality of times, and after depositing a film by the CVD method on the first layer, the deposition order may be changed freely. An effect is obtained.

(Third embodiment)
In the present embodiment, a method of manufacturing a complementary MOS transistor (CMOS) in which a refractory metal is used for the gate electrode and the gate electrode is formed by a burying method will be described, as in the first embodiment. Detailed description of the same parts as those of the first embodiment described above will be omitted. Since the steps up to the step of forming the gate insulating film are the same as those in the first embodiment, detailed description thereof is omitted.

  After forming the gate insulating film 109 as shown in FIGS. 1 (a) to 2 (e), TiN 113 is formed on the entire surface by CVD as the barrier metal 112 as shown in FIG. 2 (f). . The film thickness is, for example, about 10 nm. Subsequently, W115, which is a refractory metal, is deposited as a metal material 114 to a thickness of about 100 nm by the CVD method, and then annealed at 400 ° C. for 10 minutes in an O 2 atmosphere. The annealing temperature and time are not particularly limited. At this time, a part of the W115 deposited on the entire surface of the wafer by about 100 nm is oxidized to become WO2 having a film thickness of about 150 nm.

  Next, as in the first embodiment described above, the WO2, W113, and TiN111 are etched and planarized using the CMP method, and are buried in the gate groove. Subsequently, the WO2 is subjected to hydrogen treatment to be reduced to W, thereby forming the gate electrode 114. Thereafter, as shown in FIG. 2G, steps such as formation of the second interlayer insulating film 117, formation of contact holes, formation of the wiring electrodes 118, and the like are performed to form a CMOS transistor.

  In this embodiment, the film stress of the gate electrode formed by stacking the W113 and the WO2 is accompanied by volume expansion, whereas the first layer W formed by the CVD method is tensile stress. WO2 of the second layer formed by oxidation is a compressive stress in the direction opposite to the tensile stress. Therefore, the tensile stress in the entire laminated film is reduced, and it becomes possible to prevent the film from peeling off. The shape of the groove is not particularly limited, but the conductive material embedded in the groove is preferably a material that can be returned to its original state by reduction, such as W.

  Further, the W film thickness of the first layer and the annealing temperature and time during oxidation are selected in accordance with the depth and diameter of the groove. According to the present embodiment, a film having a tensile stress and a film having a compressive stress are formed by performing a CVD method and oxidizing and reducing the film, thereby forming a film having a tensile stress and a tensile stress of the laminated film. It is possible to provide a method for manufacturing a semiconductor device that can be reduced, can prevent film peeling, and can further improve yield.

(Fourth embodiment)
In the present embodiment, a manufacturing method of a complementary MOS transistor (CMOS) in which a high melting point metal is used for a gate electrode and a gate electrode is formed by an embedding method, particularly a method for manufacturing a peripheral region of the wafer will be described. Detailed description of the same parts as those in the first to third embodiments will be omitted. The steps up to the step of forming the nMOS formation region and the pMOS formation region and the method for manufacturing the central region of the wafer are the same as those in the first to third embodiments, and thus the first to third embodiments. The detailed description will be omitted with reference to FIGS. 1 (a) to 2 (f) used in the detailed description.

As shown in FIG. 1 (a), after forming an nMOS formation region and a pMOS formation region and oxidizing the surface of the element formation region 102 to form a thin buffer oxide film 104, as shown in FIG. Then, a polycrystalline silicon 105 and a silicon nitride film 106 are sequentially stacked as a dummy gate material. The second layer silicon nitride film is used as a stopper during etching. The film thickness is about 200 nm and 50 nm, respectively. This dummy gate, which is a dummy pattern, needs to be removed at a later step to form a trench, and a conductive material is buried in the trench, and is preferably formed at a height of about 100 nm to 350 nm. . Next, a resist is applied to form a resist film (not shown).

  FIG. 7A shows a top view of the entire surface of the wafer including the semiconductor substrate 101. As shown in FIG. 7A, when transistors are formed on a plurality of chips 602 on a wafer 601, a region 603 in the center of the wafer where a drivable transistor is formed is resisted using a lithography technique that performs exposure and development. On the other hand, a resist pattern is not formed in the peripheral region 604 of the wafer where a drivable transistor is not formed. Here, the wafer peripheral region 604 indicates either a region 605 other than a region where a drivable transistor is formed or a region 606 which is about 5 mm from the outer periphery of the wafer where a drivable transistor is not formed. Here, the region 605 is a region other than a region where a drivable transistor is formed.

  Next, in the wafer central region 603, anisotropic etching such as RIE is performed using a resist pattern (not shown) as a mask, and the silicon nitride film 106 and the polycrystalline silicon 105 are etched to form a dummy gate 107. To do. On the other hand, the dummy gate 107 is not formed in the peripheral area 604 of the wafer because the resist pattern is not formed. Next, in the wafer center region 603 where the dummy gate 107 is formed, impurities such as As and B are introduced by ion implantation using the dummy gate 107 as a mask, and activation annealing is performed. Source / drain diffusion regions are formed.

  Next, as shown in FIG. 1 (c), after forming a sidewall protective film 108 made of a silicon nitride film on the dummy gate 107, ion implantation of impurities is performed using the mask as a mask, and activation annealing is performed. Source / drain regions are formed.

  Next, as shown in FIG. 2D, for example, a TEOS film is deposited on the entire surface of the wafer by about 280 nm to form a first interlayer insulating film 109. As shown in FIG. 6, since the dummy gate 107 is not formed in the wafer peripheral region 604, the first interlayer insulating film 109 is formed on the entire surface. Subsequently, the first interlayer insulating film 109 is planarized by etching using CMP (Chemical Mechanical Polishing) until the upper surface of the dummy gate 107 is exposed.

  Next, as shown in FIG. 2 (e), the region 603 in the center of the wafer is formed by using thermal phosphoric acid treatment and CDE (Chemical Dry Etching) to expose the exposed silicon nitride film 106 and the multiple layers of the dummy gate 107. By removing the crystalline silicon 105 in order, the dummy gate 107 is removed and a gate groove 110 is formed. On the other hand, since the dummy gate 107 is not formed in the peripheral area 604 of the wafer, the gate groove 110 is not formed. Subsequently, in the region 603 in the center of the wafer, the buffer oxide film 104 in the gate trench 110 is removed with dilute hydrofluoric acid, and then a gate insulating film 111 is formed.

  Next, as shown in FIG. 2 (f), a conductive material is deposited, the conductive material is etched and planarized using a CMP method, and the gate electrode 116 is formed by embedding it in the gate groove 110. Next, as shown in FIG. The subsequent steps of configuring the CMOS transistor are the same as those in the first embodiment described above, and are therefore omitted.

In the present embodiment, the shape of the groove and the conductive material embedded in the groove are not particularly limited. According to the present embodiment, the peripheral region 604 of the wafer is generated by applying a large pressure from the pad during the CMP process without embedding the conductive material because the gate groove 110 is not formed. The film can be prevented from peeling off. Also, the wafer peripheral area
The same effect can be obtained even if 604 is a region 606 of about 5 mm from the outer periphery of the wafer where a drivable transistor is not formed (see FIG. 7B).

  Therefore, by applying this embodiment, peeling of the film during the CMP process is prevented, and the peeled conductive material adheres to and contaminates other regions as the wafer rotates, thereby causing damage. Therefore, it is possible to provide a method for manufacturing a semiconductor device that does not cause defects and can further improve the yield. In addition, since the present embodiment can be realized by performing exposure tuning at the time of exposure so that a resist pattern is not formed in a peripheral region of a wafer where a drivable transistor is not formed, a method for manufacturing a semiconductor device particularly suitable for mass production It is.

(Fifth embodiment)
In the present embodiment, a manufacturing method of a complementary MOS transistor (CMOS) in which a high melting point metal is used for a gate electrode and a gate electrode is formed by an embedding method, particularly a method for manufacturing a peripheral region of the wafer will be described. Detailed description of the same parts as those in the first to third embodiments will be omitted. The steps up to the step of forming the nMOS formation region and the pMOS formation region and the method for manufacturing the central region of the wafer are the same as those in the first to third embodiments, and thus the first to third embodiments. The detailed description will be omitted with reference to FIGS. 1 (a) to 2 (f) used in the detailed description.

  As shown in FIG. 8 (a), an nMOS formation region and a pMOS formation region are formed in the peripheral region of the wafer where a drivable transistor is not formed, and the surface of the element formation region 102 is oxidized to form a thin buffer oxide film 104. After the formation, as shown in FIG. 8B, the polycrystalline silicon 105 and the silicon nitride film 106 are sequentially stacked as a dummy gate material. The second layer silicon nitride film is used as a stopper during etching. The film thickness is about 200 nm and 50 nm, respectively. Next, a resist is applied to form a resist film (not shown), and a resist pattern is formed using a lithography technique for performing exposure and development. Next, anisotropic etching such as RIE is performed using the resist pattern (not shown) as a mask, and the silicon nitride film 106 and the polycrystalline silicon 105 are etched to form a dummy gate 107.

  Next, as shown in FIG. 8C, the dummy gate 107 in the peripheral area of the wafer where the drivable transistor is not formed is removed by RIE or pharmacological treatment. In the central region of the wafer where the drivable transistors are formed, diffusion of the source and drain is performed by introducing impurities such as As and B by ion implantation using the dummy gate 107 as a mask and performing activation annealing. Form a region.

  Here, as shown in FIGS. 7A and 7B, the region 604 on the periphery of the wafer is a region 605 other than a region where a drivable transistor is formed, or a drivable transistor is not formed. One of the regions 606 of about 5 mm from the outer periphery of the wafer is shown. Here, as in the fourth embodiment, a region 605 other than a region where a drivable transistor is formed is used.

  Next, in the region where the dummy gate 107 is formed in the central region 603 of the wafer, a sidewall protective film 108 made of a silicon nitride film is formed on the dummy gate 107, and then ion implantation of impurities is performed using it as a mask. Then, activation annealing is performed to form source / drain regions (see FIG. 1 (c)). On the other hand, the wafer peripheral region 604 where the dummy gate 107 is not formed is removed after the silicon nitride film is formed as shown in FIG. 9 (d).

Next, for example, a TEOS film is deposited on the entire surface of the wafer by about 280 nm to form a first interlayer insulating film 109. As shown in FIG. 9 (e), since the dummy gate 107 is not formed in the wafer peripheral region 604, the first interlayer insulating film 109 is formed on the entire surface. Subsequently, the first interlayer insulating film 109 is planarized by etching using CMP (Chemical Mechanical Polishing) until the upper surface of the dummy gate 107 is exposed (see FIG. 2D).

  Next, in the central region of the wafer, the dummy gate 107 is removed by sequentially removing the exposed silicon nitride film and polycrystalline silicon of the dummy gate 107 using thermal phosphoric acid treatment and CDE (Chemical Dry Etching). Then, the gate groove 110 is formed (see FIG. 2 (e)). On the other hand, in the region 604 on the peripheral edge of the wafer, as shown in FIG. 9 (f), since the dummy gate 107 is removed, the gate groove 110 is not formed.

  Subsequently, after removing the buffer oxide film 104 in the gate trench 110 with dilute hydrofluoric acid, a gate insulating film 111 is formed. Next, a conductive material is deposited, the conductive material is etched and planarized using a CMP method, and the gate electrode 116 is formed by embedding the gate groove 110 (see FIG. 2F). The subsequent steps of configuring the CMOS transistor are the same as those in the first embodiment described above, and are therefore omitted.

  In the present embodiment, the shape of the groove and the conductive material embedded in the groove are not particularly limited. According to this embodiment, since the gate groove 110 is not formed in the peripheral region 604 of the wafer, the conductive material is not embedded, and a film generated by applying a large pressure from the pad during the CMP process. Can be prevented. The same effect can be obtained even if the peripheral area 604 of the wafer is an area 606 of about 5 mm from the outer periphery of the wafer where a drivable transistor is not formed.

  Therefore, by applying this embodiment, peeling of the film during the CMP process is prevented, and the peeled conductive material adheres to and contaminates other regions as the wafer rotates, thereby causing damage. Therefore, it is possible to provide a method for manufacturing a semiconductor device that does not cause defects and can further improve the yield.

(Sixth embodiment)
In the present embodiment, a manufacturing method of a complementary MOS transistor (CMOS) in which a high melting point metal is used for a gate electrode and a gate electrode is formed by an embedding method, particularly a method for manufacturing a peripheral region of the wafer will be described. Detailed description of the same parts as those in the first to third embodiments will be omitted. The steps up to the step of forming the nMOS formation region and the pMOS formation region and the method for manufacturing the central region of the wafer are the same as those in the first to third embodiments, and thus the first to third embodiments. 1 (a) to 2 (f) used in the detailed description of FIG. 1, and detailed description thereof is omitted.

  As shown in FIG. 10 (a), an nMOS formation region and a pMOS formation region are formed in the peripheral region of the wafer where a drivable transistor is not formed, and the surface of the element formation region 102 is oxidized to form a thin buffer oxide film 104. After the formation, as shown in FIG. 10B, a polycrystalline silicon 105 and a silicon nitride film 106 are sequentially stacked as a dummy gate material. The second layer silicon nitride film is used as a stopper during etching. The film thickness is about 200 nm and 50 nm, respectively. This dummy gate, which is a dummy pattern, needs to be removed at a later step to form a trench, and a conductive material is buried in the trench, and is preferably formed at a height of about 100 nm to 350 nm. . Next, a resist is applied to form a resist film (not shown), and a resist pattern is formed using a lithography technique for performing exposure and development.

  Next, anisotropic etching such as RIE is performed using the resist pattern (not shown) as a mask, and the silicon nitride film and polycrystalline silicon are etched to form the dummy gate 107. Next, using the dummy gate 107 as a mask, impurities such as As and B are introduced by ion implantation, and activation annealing is performed to form source / drain diffusion regions.

Next, as shown in FIG. 10 (c), after forming a sidewall protective film 108 made of a silicon nitride film, impurity ions are implanted using the mask as a mask, and activation annealing is performed to form source / drain regions. To do.
Next, as shown in FIG. 11D, for example, a TEOS film is deposited on the entire surface of the wafer to a thickness of about 280 nm to form a first interlayer insulating film 109. Subsequently, the first interlayer insulating film 109 is planarized by etching using CMP (Chemical Mechanical Polishing) until the upper surface of the dummy gate 107 is exposed.

  Next, as shown in FIG. 11 (e), the exposed silicon nitride film 106 and the polycrystalline silicon 105 of the dummy gate 107 are sequentially removed using thermal phosphoric acid treatment and CDE (Chemical Dry Etching). Thus, the dummy gate 107 is removed and a gate groove 110 is formed. Subsequently, after removing the buffer oxide film 104 with dilute hydrofluoric acid, a gate insulating film 111 is formed. The gate insulating film 111 can be formed by depositing a high dielectric film such as tantalum oxide, or a silicon oxide film can be formed by oxidizing the exposed surface of the semiconductor substrate 101 and used as a gate insulating film. You can also. Next, a conductive material 801 constituting the gate electrode is deposited on the entire surface of the wafer.

  Next, as shown in FIG. 11 (f), the conductive material 801 deposited in the peripheral region of the wafer where the drivable transistor is not formed is removed by RIE or the like. Here, as shown in FIGS. 7A and 7B, the region 604 on the periphery of the wafer is a region 605 other than a region where a drivable transistor is formed, or a drivable transistor is not formed. One of the regions 606 of about 5 mm from the outer periphery of the wafer is shown. Here, as in the fourth embodiment, a region 605 other than a region where a drivable transistor is formed is used.

  Next, in the wafer center region 603, the CMP method is used to etch and planarize the conductive material 801 and fill the gate groove 110 to form a gate electrode 116 (see FIG. 2F). Subsequently, as shown in FIG. 2 (g) and FIG. 11 (g), the second interlayer insulating film is formed on the entire surface of the first interlayer insulating film 109 and the like in the central region 603 of the wafer and the peripheral region of the wafer, respectively. 117 is formed. The subsequent steps of configuring the CMOS transistor are the same as those in the first embodiment described above, and are therefore omitted.

  In the present embodiment, the shape of the groove and the conductive material embedded in the groove are not particularly limited. According to the present embodiment, since the conductive material 801 formed in the gate groove 110 in the peripheral region 604 of the wafer is removed before the CMP process, a large pressure is applied from the pad during the CMP process. It is possible to prevent the film from peeling off. Further, the same effect can be obtained even when the peripheral region 604 of the wafer is a region 606 of about 5 mm from the outer periphery of the wafer where a drivable transistor is not formed (see FIG. 7B).

  Therefore, by applying this embodiment, peeling of the film during the CMP process is prevented, and the peeled conductive material adheres to and contaminates other regions as the wafer rotates, thereby causing damage. Therefore, it is possible to provide a method for manufacturing a semiconductor device that does not cause defects and can further improve the yield.

  The first to sixth embodiments have been described above, but the present invention can be applied to the case of forming a multilayer wiring plug instead of forming a gate electrode. . Furthermore, the semiconductor device to be formed is not limited to a CMOS transistor, and even a MOS transistor, a memory, etc. can be applied to the groove filling process, and the same effect can be obtained and the yield can be further improved. Is possible.

FIG. 3 is a cross-sectional view of a principal part showing a part of a process of the method for manufacturing a semiconductor device in the first embodiment of the present invention. FIG. 3 is a cross-sectional view of a principal part showing a part of a process of the method for manufacturing a semiconductor device in the first embodiment of the present invention. FIG. 4 is a diagram illustrating the tensile stress of a film when the film formation temperature and the source gas flow rate ratio are changed according to the first embodiment of the present invention. FIG. 4 is a partially enlarged cross-sectional view of a first embodiment of the present invention when a film is formed in a groove. FIG. 6 is a partially enlarged cross-sectional view when a film is formed in a groove according to the second embodiment of the present invention. FIG. 10 is a fragmentary cross-sectional view showing a part of a process of a method for manufacturing a semiconductor device in a fourth embodiment of the present invention. FIG. 10 is a top view showing the entire surface of a wafer in a method for manufacturing a semiconductor device according to fourth to sixth embodiments of the present invention. FIG. 10 is an essential part cross-sectional view showing a part of a process of a method for manufacturing a semiconductor device in a fifth embodiment of the present invention. FIG. 10 is an essential part cross-sectional view showing a part of a process of a method for manufacturing a semiconductor device in a fifth embodiment of the present invention. FIG. 10 is a cross-sectional view of a principal part showing part of a process of a method for producing a semiconductor device in a sixth embodiment of the present invention. FIG. 10 is a cross-sectional view of a principal part showing part of a process of a method for producing a semiconductor device in a sixth embodiment of the present invention. It is principal part sectional drawing which shows a part of process of the manufacturing method of the semiconductor device in a prior art. It is principal part sectional drawing which shows a part of process of the manufacturing method of the semiconductor device in a prior art. FIG. 6 is a partially enlarged cross-sectional view of a conventional technique when a film is formed in a groove. It is a top view which shows the wafer whole surface of the manufacturing method of the semiconductor device in a prior art.

Explanation of symbols

101,901 ... Semiconductor substrate
102,902 ... Element formation region
103,903 ... element isolation region
104,904 ... Buffer oxide film
105,905 ... polycrystalline silicon
106,906… Silicon nitride film
107,907 ... Dummy gate
108,908… Sidewall protective film
109,909 ... first interlayer insulating film
110,910 ... Gate groove
111,911 ... Gate insulation film
112,912 ... Barrier metal
113,913… TiN
114,914 ... Metal material
115, 115a, 115b, 915 ... W
116,916 ... Gate electrode
117, 917 ... Second interlayer insulating film
118,918 ... wiring electrode
601 ... wafer
602 ... chip
603 ... Wafer center area where drivable transistors are formed
604 ... Wafer peripheral area where a drivable transistor is not formed
605 ... Area other than the area where a drivable transistor is formed
606 ... about 5mm from the outer periphery of the wafer where no driveable transistor is formed
801 ... Conductive material
1101 ... Wafer
1102 ... chip
1103 ... Area around the wafer where a drivable transistor is not formed
1104: Peripheral area where film peeling is likely to occur

Claims (22)

Forming an element isolation region in the first region on the semiconductor substrate;
Forming an element formation region in a second region other than the element isolation region;
Forming a dummy pattern by patterning a film on a part of the element formation region; and impurities of a carrier type opposite to the semiconductor substrate on the surface of the element formation region, using the dummy pattern as a mask. Introducing using and forming a diffusion layer;
Depositing a first insulating material on the semiconductor substrate and the dummy pattern, and planarizing until the upper portion of the dummy pattern is exposed;
Removing the dummy pattern and forming a groove;
A first conductive material is deposited in the groove so that the tensile stress with the film is 500 MPa or less, and is planarized, thereby embedding the first conductive material in the groove and forming a wiring pattern. Process,
Depositing a second insulating material on the first insulating material and the wiring pattern; and
Forming an opening so as to expose the surface of the diffusion layer and the wiring pattern, and forming a contact by forming a second conductive material in the opening; and
A method for manufacturing a semiconductor device, comprising: 2. The method for manufacturing a semiconductor device according to claim 1, wherein at least a lowermost layer of the conductive film constituting the wiring pattern is a film deposited by using a CVD method. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the dummy pattern has a height of 100 nm to 350 nm. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the wiring pattern is a step of embedding a laminated film of a barrier metal and a metal material in the groove portion. . 5. The method for manufacturing a semiconductor device according to claim 4, wherein the metal material is a refractory metal. 6. The method for manufacturing a semiconductor device according to claim 5, wherein the refractory metal is tungsten. In the step of depositing the tungsten on the barrier metal, the step of forming the semiconductor substrate by heating to 500 ° C. or more, or using WF6 and H2 as source gases at the time of film formation, the flow rate ratio WF6 / (WF6 + H2 7. The method of manufacturing a semiconductor device according to claim 6, wherein at least one of the steps of forming under a condition such that (2) is 0.025 or more and 0.05 or less is performed. Forming an element isolation region in the first region on the semiconductor substrate;
Forming an element formation region in a second region other than the element isolation region;
Forming a dummy pattern by patterning a film on a part of the element formation region; and impurities of a carrier type opposite to the semiconductor substrate on the surface of the element formation region, using the dummy pattern as a mask. Introducing using and forming a diffusion layer;
Depositing a first insulating material on the semiconductor substrate and the dummy pattern, and planarizing until the upper portion of the dummy pattern is exposed;
Removing the dummy pattern and forming a groove;
A step of laminating a film having a tensile stress and a film having a compressive stress, and depositing and planarizing the film to form a wiring pattern;
Depositing a second insulating material on the first insulating material and the wiring pattern; and
Forming an opening so as to expose the surface of the diffusion layer and the wiring pattern, and forming a contact by forming a conductive material in the opening;
A method for manufacturing a semiconductor device, comprising: 9. The method of manufacturing a semiconductor device according to claim 8, wherein the film having tensile stress is formed by a CVD method, and the film having compressive stress is formed by a sputtering method. The film having tensile stress is formed using a CVD method, the film having compressive stress is formed by oxidizing the film having tensile stress, and the wiring 9. The method for manufacturing a semiconductor device according to claim 8, further comprising a step of reducing the film having compressive stress after performing the step of forming a pattern. 11. The film having a tensile stress is configured by a laminated film of a barrier metal and a metal material, and the film having a compressive stress is configured by a metal material. The manufacturing method of the semiconductor device as described in any one of. 12. The method for manufacturing a semiconductor device according to claim 11, wherein the metal material is a refractory metal. 13. The method of manufacturing a semiconductor device according to claim 12, wherein the refractory metal is tungsten. In the step of forming a dummy pattern by patterning a film on a part of the element formation region, a region where a device that can be driven on the wafer is not formed, or a device that can be driven from the outer edge of the wafer is formed 9. The method of manufacturing a semiconductor device according to claim 1, wherein the dummy pattern is not formed in any region of the outer peripheral portion up to a region that is not to be formed. The region where the dummy pattern is not formed is removed by etching the film forming the dummy pattern without forming the resist pattern when forming the dummy pattern in the other region where the dummy pattern is formed. 15. The method for manufacturing a semiconductor device according to claim 14, wherein: 15. The method of manufacturing a semiconductor device according to claim 14, wherein in the region where the dummy pattern is not formed, the dummy pattern once formed is removed by etching. In the step of forming the wiring pattern, there is no area on the wafer where a drivable device is formed, or any area on the outer periphery from the outer edge of the wafer to a area where a drivable device is not formed. 9. The method for manufacturing a semiconductor device according to claim 1, wherein the wiring pattern is not formed. The region where the wiring pattern is not formed is a film deposited in the groove portion before the step of planarizing the film deposited on the groove portion and the first insulating material in another region where the wiring pattern is formed. 18. The method for manufacturing a semiconductor device according to claim 17, wherein the wiring pattern is not formed by performing the step of removing the semiconductor device. In the step of forming the plug of the multilayer wiring including the step of embedding a conductive material in the groove, the film is deposited so that the tensile stress of the film embedded in the groove is 500 MPa or less, and is embedded in the groove by flattening. A method of manufacturing a semiconductor device. In a step of forming a plug of a multilayer wiring including a step of embedding a conductive material in the groove, a film having a tensile stress and a film having a compressive stress are stacked and deposited in the groove and flattened to be embedded in the groove. A method of manufacturing a semiconductor device. The groove is not formed in a region where a drivable device is not formed on the wafer or in an outer peripheral portion from the outer edge of the wafer to a region where a drivable device is formed. 21. A method of manufacturing a semiconductor device according to claim 19 or claim 20. In the region where no driveable device is formed on the wafer or the outer periphery from the outer edge of the wafer to the region where the driveable device is formed, the groove is deposited in the other region. 21. The method of manufacturing a semiconductor device according to claim 19, wherein a step of removing the film deposited in the groove is performed before the step of planarizing the formed film.

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