JP2005191075A - Relay board and manufacturing method thereof, board with relay board - Google Patents

Abstract

The present invention provides a relay substrate that has excellent electrical characteristics because of low conductor resistance and that can impart high reliability to a joint portion with a semiconductor element.
A relay board 31 of the present invention includes a substantially board-shaped relay board main body 38 and a plurality of conductor pillars 35. The relay substrate body 38 has a first surface 32 and a second surface 33 on which the semiconductor element 21 having the surface connection terminals 22 is to be mounted. The relay substrate body 38 has a plurality of through holes 34 that allow the first surface 32 and the second surface 33 to communicate with each other. The relay substrate body 38 is made of a ceramic sintered body having a flexural modulus of 250 MPa or more. The plurality of conductor columns 35 are to be electrically connected to the surface connection terminals 22. The plurality of conductor columns 35 are formed by filling and firing the metal paste 52 into the plurality of through holes 34 and are made of a metal sintered body having a resistivity of 5.0 × 10 ⁻⁸ Ωm or less.
[Selection] Figure 1

Description

  The present invention relates to a relay board, a manufacturing method thereof, and a board with a relay board.

  In recent years, a relay board called an interposer is interposed between the wiring board and the motherboard, instead of directly connecting the wiring board (IC chip mounting board or IC package) on which the IC chip is mounted and a printed board such as a motherboard. Various structures are known in which these are connected to each other (see, for example, Patent Document 1).

  An IC chip used for this type of structure is generally formed using a semiconductor material (for example, silicon) having a thermal expansion coefficient of about 2.0 ppm / ° C. to 5.0 ppm / ° C. The wiring board is formed using a resin material having a considerably larger thermal expansion coefficient, and the interposer is formed using an inorganic material (for example, a ceramic material) having an intermediate thermal expansion coefficient value.

  In addition, as a candidate for the ceramic material for manufacturing the interposer, there are an alumina substrate, a low-temperature fired ceramic substrate (LTCC substrate), and the like. For example, when an alumina substrate is selected, an interposer is formed by filling a through hole provided in an unsintered alumina substrate with a paste of a refractory metal such as tungsten (W) or molybdenum (Mo) and performing simultaneous firing. Can be manufactured. When an LTCC substrate is selected, an interposer can be manufactured by filling a through hole provided in an unsintered LTCC substrate with a paste of a low resistance metal such as copper (Cu) or silver (Ag) and simultaneously firing the paste. It is.

However, a structure in which a ceramic interposer is interposed between an IC mounting substrate and a motherboard is known, but a structure in which a ceramic interposer is interposed between an IC chip and an IC mounting substrate is Not yet known. In other words, a ceramic interposer responsible for connection at the second level has been conventionally proposed, but a ceramic interposer responsible for connection at the first level has not been proposed conventionally.
Japanese Unexamined Patent Publication No. 2000-208661 (FIG. 2 (d), etc.)

  By the way, the above interposer is interposed between two members having a difference in thermal expansion coefficient. Therefore, it is considered that the interposer is easily affected by thermal stress during heating or cooling, and cracks or the like are likely to occur at the joint portion with other members. The occurrence of such cracks leads to a decrease in reliability. Therefore, it is required to increase the rigidity of the ceramic substrate in order to reduce the influence of thermal stress. In recent years, IC chip operations have become increasingly faster due to advances in integrated circuit technology, and it is desirable that the interposer also has a structure that can maximize the performance of an IC chip that is faster. Specifically, the conductor in the interposer is required to have a low resistance.

However, an interposer made of an alumina substrate has an advantage of being excellent in rigidity and strength (for example, a flexural modulus of 300 MPa or more), but has a drawback that metals that can be used as a conductor are limited to W, Mo, and the like. This is because low resistance metals such as copper and silver have a low melting point and cannot be fired simultaneously with alumina. Therefore, in this case, the resistivity of the conductor becomes as high as about 10 × 10 ⁻⁸ Ωm, and it becomes impossible to sufficiently impart suitable electrical characteristics to the interposer. In addition, an interposer made of an LTCC substrate has an advantage that the conductor resistance is low, but has a drawback that it has lower rigidity and strength (for example, a bending elastic modulus of about 200 MPa) than an alumina substrate.

  From the above, an interposer excellent in both reliability and electrical characteristics is desired. In addition, development of a technique for manufacturing such an excellent interposer at as low a cost as possible is also desired.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and its object is to provide a relay substrate with a semiconductor element that has excellent electrical characteristics because of low conductor resistance and that can impart high reliability to a junction with a semiconductor element. It is to provide a relay board. Furthermore, still another object of the present invention is to provide a manufacturing method capable of manufacturing the above excellent relay substrate relatively easily and at low cost.

And as a means for solving the above-mentioned subject, it has the 1st surface where the semiconductor element which has a surface connection terminal should be mounted, and the 2nd surface, and a plurality of which makes the 1st surface and the 2nd surface communicate A relay board body having a substantially plate shape made of a ceramic sintered body having a through-hole and a flexural modulus of 250 MPa or more, and a resistivity formed by filling and firing the metal paste into the plurality of through-holes is 5 There is a relay substrate, which is made of a metal sintered body having a size of 0.0 × 10 ⁻⁸ Ωm or less and includes a plurality of conductive columns to be electrically connected to the surface connection terminals. As another means for solving the above-described problem, the substrate includes a substrate having a surface connection pad, and has a first surface and a second surface mounted on the surface of the substrate, the first surface and A plurality of through-holes communicating with the second surface, a substantially plate-shaped relay substrate body made of a ceramic sintered body having a flexural modulus of 250 MPa or more, and filling of the plurality of through-holes with a metal paste, A relay substrate comprising a sintered metal body having a resistivity of 5.0 × 10 ⁻⁸ Ωm or less formed by firing and having a plurality of conductive columns electrically connected to the surface connection pads. There is a board with a relay board.

  Therefore, according to these inventions, low electrical resistance is imparted to the plurality of conductor pillars, and high rigidity and strength are imparted to the relay substrate body. Therefore, it is possible to provide a relay substrate and a substrate with a relay substrate that have excellent electrical characteristics and can impart high reliability to the joint portion with the semiconductor element.

  The relay board main body constituting the relay board or the board with the relay board is a substantially plate-shaped member having a first surface and a second surface.

  The first surface of the relay board body is a surface on which a semiconductor element having surface connection terminals is to be mounted, in other words, a surface on which a semiconductor element having surface connection terminals is to be mounted. As the semiconductor element, for example, one having a thermal expansion coefficient of 2.0 ppm / ° C. or more and less than 5.0 ppm / ° C. is used. Examples of such a semiconductor element include a semiconductor integrated circuit chip (IC chip) made of silicon having a thermal expansion coefficient of about 2.6 ppm / ° C. Note that the number of semiconductor elements to be mounted on the first surface of the relay substrate body may be one or two or more.

  Here, “thermal expansion coefficient” means a thermal expansion coefficient in a direction (XY direction) perpendicular to the thickness direction (Z direction), and a TMA (thermomechanical analyzer between 0 ° C. and 100 ° C. ) Means the value measured. “TMA” refers to thermomechanical analysis, such as that defined in JPCA-BU01.

  The surface connection terminal refers to a terminal for electrical connection, which is connected by surface connection. In addition, surface connection refers to the case where pads or terminals are formed in a line shape or a lattice shape (including a staggered shape) on the plane of an object to be connected, and these are connected to each other. The size and shape of the semiconductor element are not particularly limited, but at least one side is preferably 10.0 mm or more. This is because in such a large semiconductor element, the amount of heat generation is likely to increase, and the influence of thermal stress gradually increases, so that problems specific to the present application, such as the occurrence of cracks, are likely to occur.

  On the other hand, the second surface of the relay substrate main body constituting the substrate with the relay substrate is a surface mounted on the surface of the substrate having the surface connection pads. The second surface of the relay substrate main body constituting the relay substrate is a surface to be mounted on the surface of the substrate having the surface connection pads, in other words, a surface to be mounted on the surface of the substrate having the surface connection pads. is there. The surface connection pad is a terminal pad for electrical connection, which is connected by surface connection. Such surface connection pads are formed in, for example, a linear shape or a lattice shape (including a staggered shape).

  As the substrate, for example, a substrate having a thermal expansion coefficient of 5.0 ppm / ° C. or more and having a surface connection pad is used. Examples of the substrate include a substrate on which a semiconductor element or other electronic component is mounted, and particularly a wiring substrate on which a semiconductor element or other electronic component is mounted and having a conductor circuit that electrically connects them. . The material for forming the substrate is not particularly limited, and can be appropriately selected in consideration of cost, workability, insulation, mechanical strength, and the like. Examples of the substrate include a resin substrate, a ceramic substrate, and a metal substrate.

  The relay substrate body has a plurality of through holes that allow the first surface and the second surface to communicate with each other. The diameter of the through hole is not particularly limited, but is preferably 125 μm or less, for example, and more preferably 100 μm or less (however, 0 μm is not included). The center-to-center distance between the adjacent through holes is not particularly limited, but is preferably, for example, 250 μm or less, and more preferably 200 μm or less (however, 0 μm is not included). This is because, if the diameter and the distance between the centers are too large, there is a possibility that the semiconductor elements that are expected in the future cannot be sufficiently refined. In other words, if the diameter and the distance between the centers are set too large, a large number of conductor columns cannot be formed within a limited area. Furthermore, the diameter of the through hole is preferably 85 μm or less, and the center-to-center distance between the adjacent through holes is preferably 150 μm or less (however, 0 μm is not included).

  The thickness of the relay substrate main body is not particularly limited, but to be strong, it is preferably 0.1 mm or more and 0.7 mm or less, and more preferably 0.2 mm or more and 0.5 mm or less. Within such a thickness range, when a semiconductor element is mounted, the thermal stress applied to the element bonding portion becomes relatively small, which is advantageous for preventing warpage of the relay substrate body itself and cracks at the bonding portion of the semiconductor element. Become.

  The relay substrate body is made of a ceramic sintered body having a flexural modulus of 250 MPa or more, and preferably made of a ceramic sintered body having a 300 MPa or more. The reason is as follows. That is, if the flexural modulus is 250 MPa or more, high rigidity can be imparted to the relay substrate body, and it is possible to withstand large thermal stress. As a result, it is possible to prevent warping of the relay substrate body itself and cracks at the joint portion of the semiconductor element. In addition, if the flexural modulus is lower than 250 MPa, the rigidity is not so different from that of the low-temperature fired ceramic, which is not preferable.

  The ceramic sintered body having a flexural modulus of 250 MPa or more includes an alumina sintered body (flexural modulus = 350 MPa), an aluminum nitride sintered body (flexural modulus = 350 MPa), and a silicon nitride sintered body (flexural modulus). = 690 MPa).

  The relay substrate body is preferably made of a ceramic sintered body having a Young's modulus of 250 GPa or more, and more preferably made of a ceramic sintered body having a Young's modulus of 300 GPa or more. The reason is that if the Young's modulus is 250 GPa or more, high rigidity can be imparted to the relay substrate body, and it is possible to withstand large thermal stress. As a result, it is possible to prevent warping of the relay substrate body itself and cracks at the joint portion of the semiconductor element. Further, if the Young's modulus is lower than 250 GPa, the rigidity is not much different from that of a semiconductor element, and the semiconductor element cannot be sufficiently protected. Examples of the ceramic sintered body having a Young's modulus of 250 GPa or more include alumina (Young's modulus = 280 GPa), aluminum nitride (Young's modulus = 350 GPa), and silicon nitride (Young's modulus = 300 GPa).

  By the way, in addition to being highly rigid as described above, the relay substrate main body preferably has low thermal expansion. The thermal expansion coefficient of the relay substrate body is preferably an intermediate value between the semiconductor element and the substrate, and is preferably 2.0 ppm / ° C. or more and less than 8.0 ppm / ° C., for example. The reason is that if the thermal expansion coefficient of the relay substrate body exceeds 8.0 ppm / ° C., the difference in thermal expansion coefficient from the semiconductor element is not sufficiently reduced, and the influence of thermal stress on the semiconductor element cannot be sufficiently reduced. It is. Therefore, for example, when a silicon IC chip having a thermal expansion coefficient of about 2.6 ppm / ° C. is selected, it is preferable to use a relay substrate body having a thermal expansion coefficient of 3.0 ppm / ° C. or more and less than 8.0 ppm / ° C. It can be said that. Incidentally, the thermal expansion coefficient of alumina is 7.6 ppm / ° C., the thermal expansion coefficient of aluminum nitride is 4.4 ppm / ° C., and the thermal expansion coefficient of silicon nitride is 3.0 ppm / ° C.

  In summary, the relay substrate body is preferably made of an alumina-based ceramic sintered body. This is because the alumina-based ceramic sintered body is suitable for use as a relay substrate body (ie, high rigidity and low thermal expansion), and is cheaper than a non-oxide ceramic sintered body. . Therefore, if a relay board or a board with a relay board is configured using such a relay board main body, it is possible to achieve cost reduction while maintaining suitable performance.

  The relay substrate body preferably has not only high rigidity and low thermal expansion, but also insulation. The reason for this is that when a relay substrate body that does not have insulation is used, it is necessary to form an insulating layer in order to insulate it from the conductor pillars, resulting in a complicated structure and associated high cost. This is because problems arise. On the other hand, if the relay substrate body itself has an insulating property, an insulating layer is not necessary, so that simplification and cost reduction can be achieved. In view of this point, it can be said that the use of an alumina-based ceramic sintered body is preferable.

Here, the “alumina-based ceramic sintered body” refers to a ceramic sintered body having a main crystal made of α-alumina (corundum), and includes 80% by weight or more of alumina (Al ₂ O ₃ ). Therefore, if it is a small amount, components other than alumina, for example, silica, calcia, magnesia, titania, zirconia and the like may be contained in the sintered body in one or more kinds.

  The relay board and the board with the relay board have a plurality of conductor pillars. One end of each of the plurality of conductor pillars in the substrate with the relay substrate is to be electrically connected to the surface connection terminal of the semiconductor element, and the other end is electrically connected to the surface connection pad of the substrate. One end of the plurality of conductor pillars in the relay substrate is to be electrically connected to the surface connection terminal of the semiconductor element, and the other end is to be electrically connected to the surface connection pad of the substrate.

The plurality of conductor pillars are made of a metal sintered body formed by filling and firing a metal paste and having a resistivity of 5.0 × 10 ⁻⁸ Ωm or less (excluding 0 × 10 ⁻⁸ Ωm). . Here, “resistivity” means resistivity at 20 ° C. If the resistivity of the sintered metal exceeds 5.0 × 10 ⁻⁸ Ωm, it is not possible to sufficiently reduce the resistance of the conductor pillars, and suitable electrical characteristics are obtained by using a relay board or a board with a relay board. It is because it becomes impossible to give enough. The resistivity of the sintered metal body is more preferably 1.0 × 10 ⁻⁸ Ωm or more and 4.0 × 10 ⁻⁸ Ωm or less.

The plurality of conductor pillars are sintered metal satisfying a condition that resistivity is 5.0 × 10 ⁻⁸ Ωm or less, specifically copper, silver or gold alone, copper, silver or gold alloy, It may be selected from sintered bodies of copper, silver, or gold compounds (for example, oxides). Among these, it is more preferable to select a sintered body of a simple substance of copper or a simple substance of silver. The reason for this is that copper and silver are not as expensive as gold and are advantageous for cost reduction, and it is easy to achieve low resistance.

  A solder layer may be formed on at least one end face of the plurality of conductor pillars, specifically, on the first face side end face on which the semiconductor element is to be mounted. A solder bump protruding from the first surface is suitable as the solder layer. This is because the presence of such solder bumps makes it possible to mount bumpless semiconductor elements. Of course, the solder layer may be formed on both end faces of the plurality of conductor pillars. The solder used for forming the solder layer is not particularly limited, and can be arbitrarily selected according to the application.

  The solder layer may be formed, for example, after a barrier metal layer is formed in advance on the end face of the conductor pillar. The structure in which the barrier metal layer is interposed between the solder layer and the conductor column can improve the solder wettability of the conductor column, so that the adhesion between the solder layer and the conductor column can be improved. is there. Examples of such a barrier metal layer include a nickel layer, a chromium layer, an aluminum layer, a gold layer, and the like formed by plating.

  Further, when the conductor column is made of, for example, high-purity silver, the solder layer may be directly formed on the end surface of the conductor column without interposing a barrier metal layer. This is because high-purity silver has good solder wettability, and high adhesion can be obtained between the two even without a barrier metal layer. Further, by omitting the barrier metal layer, the structure of the conductor pillar can be simplified, which is advantageous for cost reduction of the relay substrate and the substrate with the relay substrate.

  Further, one or more electronic components and elements other than semiconductor elements may be provided on the surface of the relay substrate body, particularly on the first surface and the second surface. Specific examples of the electronic component include a chip transistor, a chip diode, a chip resistor, a chip capacitor, and a chip coil. These electronic components may be active components or passive components. Specific examples of the element include a thin film transistor, a thin film diode, a thin film resistor, a thin film capacitor, and a thin film coil. These elements may be active elements or passive elements. And even if the wiring layer which connects the said electronic components, the said elements, or the said electronic components, the said element, and a conductor pillar is formed on the 1st surface or the 2nd surface of the said relay substrate main body. Good. Note that by providing electronic components and elements, the added value of the relay substrate or the substrate with the relay substrate can be increased.

  For example, in the case of a relay substrate with a thin film capacitor or a substrate with a relay substrate, the thin film capacitor is arranged on the power line (that is, on the wiring connecting the power circuit on the substrate side and the power terminal on the semiconductor element side). Is good. With this configuration, noise (voltage fluctuation) on the power supply line can be absorbed. Therefore, high frequency noise in the GHz band can be reduced, and the semiconductor element can be operated at high speed. Here, the thin film capacitor means a capacitor having a structure in which a ferroelectric thin film is sandwiched between conductors.

  When the thin film capacitor is formed, it is preferable that a layer denser than the ceramic sintered body constituting the relay substrate body is formed in advance on the surface of the relay substrate body. That is, the surface of the relay substrate body is in a state suitable for forming a thin film capacitor. In this case, the dense layer is preferably made of a low dielectric constant material. The dense layer can be produced, for example, by applying a low dielectric constant glass on the surface of the ceramic green body and firing them simultaneously. A dense layer made of glass has an advantage that it can be formed at a relatively low cost.

Further, as means for solving the above-described another problem, the semiconductor device having the surface connection terminal has a first surface and a second surface to be mounted, and the first surface and the second surface are arranged. In a method of manufacturing a relay board comprising a substantially plate-shaped relay board body having a plurality of through-holes to be communicated and a plurality of conductor pillars arranged in the plurality of through-holes, the ceramic unsintered body has the plurality of A through-hole forming step of forming a through-hole, a primary firing step of firing the ceramic unsintered body to produce a ceramic sintered body having a flexural modulus of 250 MPa or more, and the ceramic sintered body A paste filling step of filling a metal paste containing unsintered metal into a plurality of through holes, and firing the metal paste to form a sintered metal body having a resistivity of 5.0 × 10 ⁻⁸ Ωm or less. The plurality of conductor pillars A method of manufacturing a relay board, which comprises a secondary firing step of forming, there is.

  In the above manufacturing method, after performing a primary firing step of firing a ceramic unsintered body to produce a relay substrate body in advance, a secondary firing step of firing a metal paste to form a plurality of conductor columns It is carried out. That is, in sintering the metal in the metal paste, a post-firing method is adopted instead of the simultaneous firing method. Therefore, unlike the case of employing the co-firing method, the use of a refractory metal paste is not essential. Therefore, the degree of freedom of the combination of the ceramic used for the relay board body and the metal used for the conductor pillars is increased, and both high rigidity of the relay board body and low resistance of the plurality of conductor pillars can be achieved.

  Further, in the above manufacturing method, since the through hole is formed in the unsintered unsintered ceramic material, the through hole can be formed relatively easily and inexpensively.

  Hereinafter, this manufacturing method will be described.

  In the through hole forming step, a plurality of through holes penetrating the front and back of the ceramic green body are formed. In forming the through hole, a conventionally known method such as drilling, punching, or laser processing can be employed. For example, when forming a through-hole having a diameter of 125 μm or less, it is possible to perform drilling with high accuracy and efficiency by adopting laser processing.

  In the primary firing step, the ceramic unsintered body that has been drilled is fired to produce a ceramic sintered body having a flexural modulus of 250 MPa or more. The firing conditions at this time (firing time, firing temperature, ambient atmosphere, etc.) are appropriately set according to the type of ceramic material used.

  In the paste filling step, a metal paste containing unsintered metal is filled into the plurality of through holes in the ceramic sintered body obtained through the primary firing step. As the metal paste containing an unsintered metal, for example, a paste containing copper, silver or gold powder as a main component is used. This type of paste may contain, as a main component, a powder of an alloy of copper, silver or gold or a compound of copper, silver or gold (for example, an oxide). In this case, you may use what is called a metal nano paste containing the fine metal particle whose particle diameter is 100 nm or less. The use of metal nanopaste also contributes to reducing the resistance of the conductive pillar. Moreover, as a method of filling the metal paste into the through hole, for example, there is a printing method.

In the secondary firing step, the metal paste is fired to obtain a sintered metal body having a resistivity of 5.0 × 10 ⁻⁸ Ωm or less. That is, in this step, the metal in the metal paste is sintered by a post-baking method to form a plurality of conductor columns. In this case, the firing conditions (firing time, firing temperature, ambient atmosphere, etc.) are appropriately set according to the type of metal paste used. In order to reduce the resistance of the metal sintered body, it is preferable to prevent oxidation of the metal sintered body by firing in an inert atmosphere such as nitrogen.

  Thereafter, if a solder layer is formed on the end face of the conductor pillar as necessary, a desired relay substrate is completed. The solder layer can be formed by, for example, performing reflow after printing a solder paste on the end face of the conductor pillar.

[First Embodiment]

  Hereinafter, an embodiment embodying the present invention will be described in detail with reference to FIGS. FIG. 1 is a schematic cross-sectional view showing a semiconductor package 11 of this embodiment including an IC chip (semiconductor element) 21, an interposer (relay substrate) 31, and a wiring substrate (substrate) 41. 2, 3, 4, 5, and 6 are schematic cross-sectional views for explaining the manufacturing process of the interposer 31. FIG. 7 is a schematic cross-sectional view showing the completed interposer 31. FIG. 8 is a schematic cross-sectional view showing a state where an interposer with an IC chip (a relay board with a semiconductor element) 61 constituting the semiconductor package 11 is mounted on the wiring board 41.

  As shown in FIG. 1, the semiconductor package 11 of this embodiment is an LGA (land grid array) including the IC chip 21, the interposer 31, and the wiring substrate 41 as described above. Note that the form of the semiconductor package 11 is not limited to LGA alone, and may be, for example, BGA (ball grid array), PGA (pin grid array), or the like. The IC chip 21 having a function as an MPU is a rectangular flat plate having a length of 12.0 mm, a width of 10.0 mm, and a thickness of 0.7 mm, and is made of silicon having a thermal expansion coefficient of about 2.6 ppm / ° C. Circuit elements (not shown) are formed on the lower surface layer of the IC chip 21. A plurality of surface connection terminals 22 are provided in a lattice pattern on the lower surface side of the IC chip 21.

  The wiring board 41 is a so-called multilayer wiring board made of a rectangular flat plate member (45 mm square) having an upper surface 42 and a lower surface 43 and having a plurality of resin insulation layers 44 and a plurality of layers of conductor circuits 45. In the case of this embodiment, specifically, the resin insulating layer 44 is formed of an insulating base material obtained by impregnating a glass cloth with an epoxy resin, and the conductor circuit 45 is formed of a copper foil or a copper plating layer. The thermal expansion coefficient of the wiring board 41 is 13.0 ppm / ° C. or more and less than 16.0 ppm / ° C. On the upper surface 42 of the wiring substrate 41, a plurality of surface connection pads 46 for electrical connection with the interposer 31 side are formed in a lattice shape. On the lower surface 43 of the wiring substrate 41, a plurality of surface connection pads 47 for electrical connection with a mother board (not shown) are formed in a lattice shape. The surface connection pads 47 for connecting the motherboard have a wider area and a wider pitch than the surface connection pads 46 for interposer connection. Via hole conductors 48 are provided in the resin insulating layer 44, and the conductor circuits 45, the surface connection pads 46, and the surface connection pads 47 of different layers are electrically connected to each other via these via hole conductors 48. . In addition to the interposer 61 with an IC chip shown in FIG. 8, a chip capacitor, a semiconductor element, and other electronic components (all not shown) are mounted on the upper surface 42 of the wiring board 41.

  The interposer 31 of this embodiment is to be called a so-called first level interposer, and includes a rectangular flat plate-shaped interposer body 38 (relay board body) having an upper surface 32 (first surface) and a lower surface 33 (second surface). Have. The interposer body 38 is made of an alumina sintered body substrate having a thickness of about 0.3 mm. Such an alumina sintered body substrate has a thermal expansion coefficient of about 7.6 ppm / ° C., a Young's modulus of about 280 GPa, and a flexural modulus of about 350 MPa. Therefore, the thermal expansion coefficient of the interposer body 38 is smaller than the thermal expansion coefficient of the wiring substrate 41 and larger than the thermal expansion coefficient of the IC chip 21. That is, it can be said that the interposer 31 of the present embodiment has lower thermal expansion than the wiring board 41. Moreover, since the Young's modulus of the alumina sintered body substrate is higher than that of the IC chip 21 (that is, 190 GPa or more), the interposer 31 of this embodiment has at least higher rigidity than silicon.

In the interposer main body 38 constituting the interposer 31, a plurality of vias 34 (through holes) penetrating the upper surface 32 and the lower surface 33 are formed in a lattice shape. These vias 34 correspond to the positions of the surface connection pads 46 of the wiring board 41. In the via 34, a conductor column 35 made of a sintered body of high-purity silver (Ag) is provided. Resistivity at 20 ° C. of the metal sintered body constituting the conductor columns 35 has a ^{1.6 × 10 -8 Ωm~3.0 × 10 -8} Ωm order. An interposer-side solder bump 36 (solder layer) having a substantially hemispherical shape is provided on the upper end surface of each conductor column 35. The interposer-side solder bump 36 is formed so as to be in direct contact with the conductor column 35 without interposing a barrier metal layer or the like. These interposer-side solder bumps 36 protrude from the upper surface 32 by about 50 μm to 300 μm and are electrically connected to each surface connection terminal 22 on the IC chip 21 side. On the other hand, board-side solder bumps 37 are provided on the surface connection pads 46 on the wiring board 41 side. The lower end surface of each conductor column 35 is electrically connected to each surface connection pad 46 via these board-side solder bumps 37. In the present embodiment, the interposer-side solder bumps 36 are not particularly provided on the lower end surface of each conductor pillar 35, but a configuration in which this is provided may be employed.

  In the semiconductor package 11 having such a structure, the wiring substrate 41 side and the IC chip 21 side are electrically connected via the conductor pillar 35 of the interposer 31. Therefore, signals are input / output between the wiring board 41 and the IC chip 21 via the interposer 31, and power for operating the IC chip 21 as an MPU is supplied.

  Here, a procedure for manufacturing the semiconductor package 11 having the above structure will be described.

  The interposer 31 is produced through the following procedure, for example. First, an alumina green sheet 51 (ceramic unsintered body) as shown in FIG. 2 is manufactured by a known ceramic green sheet forming technique (unsintered body manufacturing step).

  In the subsequent through-hole forming step, vias 34 (through-holes) penetrating the front and back are provided at predetermined positions in the alumina green sheet 51 by laser processing using a carbon dioxide gas laser (see FIG. 3). In this embodiment, since drilling is performed at the stage of an unsintered body, drilling is performed relatively easily and at a lower cost than the method of drilling at the stage of becoming a sintered body. Can do.

  In the subsequent primary firing step, the alumina green sheet 51 that has been drilled is fired in an oxidizing atmosphere at a predetermined temperature for a predetermined time to produce an interposer body 38 made of a ceramic sintered body (see FIG. 4).

  In the subsequent paste filling step, the silver paste 52 is printed on the interposer body 38 using a screen printing device or the like, and the silver paste 52 is filled in each via 34 (see FIG. 5). Specifically, in this embodiment, a silver paste 52 containing high-purity silver as a main component is used.

  In the subsequent secondary firing step, the interposer body 38 after filling the paste is heated to 800 ° C. to 900 ° C. in an inert atmosphere to sinter the silver in the silver paste 52 to form a plurality of conductor pillars 35 (FIG. 6).

  In the subsequent bump formation step, the interposer body 38 on which the conductor pillars 35 are formed is set in a screen printing apparatus, and a predetermined mask provided with an opening corresponding to a position where the conductor pillars 35 are located on the surface of the interposer body 38. To place. In this state, the solder paste is printed on the interposer body 38, and a solder paste print layer is formed on the upper end surface of the conductor column 35 through the opening of the mask. In the present embodiment, a high melting point solder paste having a composition of 90% Pb-10% Sn is used. Next, the interposer body 38 is transferred to a reflow furnace where it is heated to a predetermined temperature to reflow the solder paste printed layer. As a result, a substantially hemispherical solder bump 36 is directly formed on the upper end surface of each conductor column 35, and the desired interposer 31 shown in FIG. 7 is completed. Since the conductor column 35 is made of a high-purity silver sintered body excellent in solder wettability, the solder bump 36 can be reliably adhered to the conductor column 35 without interposing a barrier metal layer.

  Next, the IC chip 21 is placed on the upper surface 32 of the completed interposer 31. At this time, the surface connection terminals 22 on the IC chip 21 side and the interposer side solder bumps 36 are aligned. The interposer-side solder bumps 36 and the surface connection terminals 22 are joined by heating and reflowing the interposer-side solder bumps 36. As a result, the interposer 61 with IC chip shown in FIG. 8 is completed.

  Next, the lower end surface of each conductor column 35 on the interposer 31 side and each board-side solder bump 37 on the wiring board 41 side are aligned (see FIG. 8), and the interposer 61 with IC chip is placed on the wiring board 41. Is placed. And the lower end surface of each conductor pillar 35 and each surface connection pad 46 are joined via each board side solder bump 37, respectively. Thereafter, if necessary, the interface is sealed with an underfill (not shown) to complete the semiconductor package 11 shown in FIG.

  Therefore, according to the present embodiment, the following effects can be obtained.

(1) In this embodiment, as described above, the resistivity of the metal sintered body derived from the silver paste 52 is set to an extremely low value of 5.0 × 10 ⁻⁸ Ωm or less. Therefore, it can be said that a low conductive resistance is imparted to the plurality of conductor pillars 35, and electrical characteristics suitable for the interposer 31 are sufficiently imparted. Therefore, it is possible to realize the interposer 31 having a structure capable of maximizing the performance of the IC chip 21 that will be speeded up in the future.

  (2) Moreover, in this embodiment, as described above, the bending elastic modulus of the ceramic sintered body constituting the interposer body 38 is set to an extremely high value of 250 MPa or more. Therefore, the interposer body 38 is provided with high rigidity and strength, so that it can withstand a large thermal stress. Therefore, it is possible to prevent warping of the interposer body 38 itself and cracks at the joint portion between the IC chip 21 and the interposer 31 in advance. Therefore, the interposer 31 that can impart high reliability to the chip bonding portion can be realized. For this reason, it becomes possible to obtain the semiconductor package 11 excellent in reliability and durability.

  (3) In this embodiment, since the interposer body 38 is made of an inexpensive alumina-based ceramic sintered body, the cost reduction of the interposer 31 can be easily achieved. Further, since the alumina-based ceramic sintered body itself has an insulating property, it is not necessary to form a resin insulating layer or the like on the interposer body 38 in particular. As a result of eliminating the need for the insulating layer, the structure of the interposer 31 can be simplified and the cost can be reduced.

(4) In this embodiment, since the post-firing method is adopted in manufacturing the interposer 31, the use of a refractory metal paste containing tungsten, molybdenum or the like is not essential. Therefore, the degree of freedom of the combination of the ceramic used for the interposer body 38 and the metal used for the conductor column 35 is increased, and both the high rigidity of the interposer body 38 and the low resistance of the plurality of conductor columns 35 can be achieved. it can. Further, in the manufacturing method of the present embodiment, the via 34 is formed on the unsintered unsintered ceramic material. Therefore, the via 34 can be formed relatively easily and inexpensively. Therefore, the interposer 31 can be manufactured relatively easily and at low cost.
[Second Embodiment]

  Next, the interposer 71 of the second embodiment will be described with reference to FIG. Here, the difference from the first embodiment will be mainly described.

In the interposer 71 of the present embodiment, a conductor column 35 made of a sintered body of high purity copper (Cu) is provided in each via 34. Resistivity at 20 ° C. of the metal sintered body constituting the conductor columns 35 has a ^{1.8 × 10 -8 Ωm~3.2 × 10 -8} Ωm order. An interposer-side solder bump 36 (solder layer) having a substantially hemispherical shape is provided on the upper end surface of each conductor column 35. However, unlike the first embodiment, a barrier metal layer 72 is interposed between the interposer-side solder bump 36 and the upper end surface of the conductor column 35. The barrier metal layer 72 in the present embodiment is specifically a nickel plating layer having a thickness of about 0.1 μm to 5 μm and a gold plating layer having a thickness of about 0.1 μm to 5 μm. With this structure, the solder wettability of the conductor column 35 is improved, so that the adhesion between the interposer-side solder bump 36 and the conductor column 35 can be improved. This also contributes to improving the reliability of the interposer 31 and thus improving the reliability of the semiconductor package 11.
[Third Embodiment]

  Next, the interposer 81 according to the third embodiment will be described with reference to FIG. Here again, the description will focus on the differences from the first embodiment.

  In the case of the interposer 81 of the present embodiment, the dense layer 82 is formed in the outer peripheral portion of the upper surface 32 of the interposer body 38, that is, in the region where the plurality of conductor columns 35 are not present on the upper surface 32. The dense layer 82 is denser than the alumina sintered body constituting the interposer body 38, and is specifically made of a low dielectric constant glass sintered body (glass ceramic). The thickness of the dense layer 82 is set to about 1 μm to 30 μm.

  A method of manufacturing such an interposer 81 will be described. First, a mask that covers the center of one side surface of the alumina green sheet 51 after performing the green body manufacturing step and the through hole forming step as in the first embodiment. Is provided. And this mask is a position state, and applies a glass paste uniformly to the outer peripheral part of one side of the alumina green sheet 51. Examples of the coating method include screen printing, curtain coating, and spin coating. Thereafter, by performing the primary firing step, the alumina green sheet 51 and the glass paste layer are simultaneously fired to obtain the interposer body 38 having the dense layer 82. Thereafter, a desired interposer 81 can be obtained by sequentially performing a paste filling step and the like.

  And the interposer 81 of such a structure will be in the state suitable for formation of a thin film capacitor in the upper surface 32 outer peripheral part. Therefore, if a thin film capacitor is provided in such a portion, the IC chip 21 can be operated at high speed, and the added value of the interposer 81 can be increased.

  In addition, you may change embodiment of this invention as follows.

  For example, the semiconductor package 11 of the first embodiment may be manufactured by the following procedure. First, the interposer 31 is joined to the upper surface 42 of the wiring substrate 41 by soldering or the like, so that a wiring substrate with an interposer (substrate with a relay substrate) is produced in advance. Thereafter, the IC chip 21 is bonded to the upper surface 32 of the wiring board with an interposer to obtain a desired semiconductor package 11.

  Next, the technical ideas grasped by the embodiment described above are listed below.

  (1) A first surface on which a semiconductor element having a surface connection terminal is to be mounted and a second surface; a plurality of through holes that communicate the first surface and the second surface; A substantially plate-shaped relay substrate body made of a ceramic sintered body, and a metal sintered body formed by filling and firing silver paste or copper paste into the plurality of through holes, and electrically connecting the surface connection terminals And a plurality of conductor pillars to be connected to the relay board.

(2) having a first surface and a second surface on which a semiconductor element having surface connection terminals is to be mounted, and having a plurality of through-holes communicating the first surface and the second surface, and a flexural modulus A substantially plate-shaped relay substrate body made of an insulating ceramic sintered body having a thickness of 250 MPa or more, and a resistivity formed by filling and firing the metal paste into the plurality of through holes is 5.0 × 10 ⁻⁸ Ωm While comprising the following metal sintered body and comprising a plurality of conductor columns to be electrically connected to the surface connection terminals, on the first surface, on the second surface and the inner periphery of the plurality of through holes A relay substrate characterized in that no insulating layer is provided on any of the surfaces.

  (3) The relay substrate according to the technical idea 1 or 2, wherein the relay substrate body is made of a ceramic sintered body having a Young's modulus of 250 GPa or more.

  (4) The relay substrate according to the technical idea 1 or 2, wherein the semiconductor element has a thermal expansion coefficient of 2.0 ppm / ° C. or more and less than 5.0 ppm / ° C.

  (5) The relay substrate according to the technical idea 1 or 2, wherein at least one side of the semiconductor element is 10 mm or more.

  (6) The relay board according to the technical idea 1 or 2, wherein the thickness of the relay board body is 0.1 mm or more and 0.7 mm or less.

  (7) The relay substrate according to the technical idea 1 or 2, wherein a diameter of the through hole is 100 μm or less, and a center-to-center distance between the adjacent through holes is 200 μm or less.

  (8) The relay according to the technical idea 1 or 2, wherein the solder layer is a solder bump that is directly formed on the first surface side end surface of the conductor column and protrudes from the first surface. substrate.

  (9) The relay substrate according to the technical idea 1 or 2, wherein a thin film capacitor is formed on a surface of the relay substrate body.

(10) A plurality of through-holes including a semiconductor element having a surface connection terminal, having a first surface and a second surface on which the semiconductor element is mounted, and communicating the first surface and the second surface. A relay substrate body having a substantially plate shape made of a ceramic sintered body having a flexural modulus of 250 MPa or more, and a resistivity formed by filling and firing the metal paste into the plurality of through holes. A relay substrate with a semiconductor element, comprising a relay substrate made of a metal sintered body of × 10 ⁻⁸ Ωm or less and having a plurality of conductive columns electrically connected to the surface connection terminals.

(11) A semiconductor element having surface connection terminals, a substrate having surface connection pads, a first surface on which the semiconductor element is mounted, and a second surface mounted on the surface of the substrate. A substantially plate-shaped relay substrate body made of a ceramic sintered body having a plurality of through-holes communicating with the first surface and the second surface and having a flexural modulus of 250 MPa or more; and the inside of the plurality of through-holes A metal paste having a resistivity of 5.0 × 10 ⁻⁸ Ωm or less formed by filling and baking a metal paste, and being electrically connected to the surface connection terminals and the surface connection pads A structure comprising a semiconductor element, a relay substrate, and a substrate, comprising a relay substrate having a conductor post.

1 is a schematic cross-sectional view showing a semiconductor package of a first embodiment including an IC chip (semiconductor element), an interposer (relay substrate), and a wiring substrate (substrate). The schematic sectional drawing for demonstrating the manufacturing process of the interposer of 1st Embodiment. The schematic sectional drawing for demonstrating the manufacturing process of the interposer of 1st Embodiment. The schematic sectional drawing for demonstrating the manufacturing process of the interposer of 1st Embodiment. The schematic sectional drawing for demonstrating the manufacturing process of the interposer of 1st Embodiment. The schematic sectional drawing for demonstrating the manufacturing process of the interposer of 1st Embodiment. FIG. 3 is a schematic cross-sectional view showing the completed interposer according to the first embodiment. The schematic sectional drawing which shows the state when mounting the interposer with an IC chip (intermediate board with a semiconductor element) which comprises the semiconductor package of 1st Embodiment on a wiring board. The schematic sectional drawing which shows the interposer of 2nd Embodiment. The schematic sectional drawing which shows the interposer of 3rd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 21 ... IC chip as a semiconductor element 22 ... Surface connection terminal 31, 71, 81 ... Interposer as a relay substrate 32 ... Upper surface as 1st surface 33 ... Lower surface as 2nd surface 34 ... Via as a through hole 35 ... Conductor Pillar 36 ... Interposer side solder bump 38 as a solder layer 38 ... Interposer body 41 as a relay board body 41 ... Wiring board 46 as a substrate 46 ... Surface connection pad 51 ... Alumina green sheet 52 as ceramic unsintered body 52 ... As metal paste Silver paste 61 ... Wiring board with interposer as a board with relay board 82 ... Barrier metal layer

Claims (3)

A semiconductor element having a surface connection terminal has a first surface and a second surface to be mounted, and has a plurality of through-holes communicating the first surface and the second surface, and a flexural modulus of 250 MPa or more. A substantially plate-shaped relay substrate body made of a ceramic sintered body of
It is made of a metal sintered body having a resistivity of 5.0 × 10 ⁻⁸ Ωm or less formed by filling and firing the metal paste into the plurality of through holes, and should be electrically connected to the surface connection terminal A relay board comprising a plurality of conductor pillars. Comprising a substrate having surface connection pads, and
A ceramic surface having a first surface and a second surface mounted on the surface of the substrate, having a plurality of through-holes communicating the first surface and the second surface, and having a flexural modulus of 250 MPa or more. It consists of a substantially plate-shaped relay substrate body composed of a bonded body, and a metal sintered body having a resistivity of 5.0 × 10 ⁻⁸ Ωm or less formed by filling and firing the metal paste into the plurality of through holes. And a relay board having a plurality of conductor pillars electrically connected to the surface connection pads. A substantially plate-shaped relay substrate body having a first surface and a second surface on which a semiconductor element having a surface connection terminal is to be mounted, and having a plurality of through-holes communicating the first surface and the second surface; In a method for manufacturing a relay board comprising a plurality of conductor pillars arranged in the plurality of through holes,
A through hole forming step of forming the plurality of through holes in the ceramic green body,
A primary firing step of firing the ceramic unsintered body to produce a ceramic sintered body having a flexural modulus of 250 MPa or more;
In the plurality of through holes in the ceramic sintered body, a paste filling step of filling a metal paste containing an unsintered metal,
A secondary firing step of forming the plurality of conductor columns by firing the metal paste to form a sintered metal having a resistivity of 5.0 × 10 ⁻⁸ Ωm or less. A method for manufacturing a relay board.

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