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JP2005166764A - Multilayer printed wiring board and method for producing multilayer printed wiring board - Google Patents

Multilayer printed wiring board and method for producing multilayer printed wiring board Download PDF

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Publication number
JP2005166764A
JP2005166764A JP2003400905A JP2003400905A JP2005166764A JP 2005166764 A JP2005166764 A JP 2005166764A JP 2003400905 A JP2003400905 A JP 2003400905A JP 2003400905 A JP2003400905 A JP 2003400905A JP 2005166764 A JP2005166764 A JP 2005166764A
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land
wiring board
printed wiring
layer
core
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Akihiko Happoya
明彦 八甫谷
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Toshiba Corp
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Toshiba Corp
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Priority to JP2003400905A priority Critical patent/JP2005166764A/en
Priority to TW093124206A priority patent/TWI293015B/en
Priority to KR1020040068426A priority patent/KR100654283B1/en
Priority to CNB2004100683724A priority patent/CN100428873C/en
Publication of JP2005166764A publication Critical patent/JP2005166764A/en
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/421Blind plated via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0044Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0047Drilling of holes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4602Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/09454Inner lands, i.e. lands around via or plated through-hole in internal layer of multilayer PCB
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/09509Blind vias, i.e. vias having one side closed

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

【課題】信頼性の高いブラインドビアを設けた多層プリント配線板、および信頼性の高いブラインドビアを容易に形成可能な多層プリント配線板の製造方法を提供することを課題とする。
【解決手段】コア部材10の第3層(L3)に、配線パターン14の導体厚Th1より厚い、導体厚Th2のビア受けランド12を形成し、上記ビア受けランド12を設けたコア部材10に、ドリル加工で、絶縁層18を介して上記ビア受けランド12と対向する面方向より、上記ビア受けランド12に接する深さまで所定径の孔を穿設し、その孔の内壁に所定のめっきを施してL1,L3間を回路接続するブラインドビア11を形成する。
【選択図】 図1
It is an object of the present invention to provide a multilayer printed wiring board provided with a highly reliable blind via and a method for manufacturing a multilayer printed wiring board capable of easily forming a highly reliable blind via.
A via receiving land having a conductor thickness Th2 that is thicker than a conductor thickness Th1 of a wiring pattern 14 is formed in a third layer (L3) of the core member 10, and the core member 10 provided with the via receiving land 12 is provided. Then, by drilling, a hole with a predetermined diameter is drilled from the surface direction facing the via receiving land 12 through the insulating layer 18 to a depth in contact with the via receiving land 12, and predetermined plating is applied to the inner wall of the hole As a result, the blind via 11 for connecting the circuits between L1 and L3 is formed.
[Selection] Figure 1

Description

本発明は各種の電子回路に適用される多層プリント配線板および多層プリント配線板の製造方法に関する。   The present invention relates to a multilayer printed wiring board applied to various electronic circuits and a method for manufacturing the multilayer printed wiring board.

情報処理機器をはじめ各種の小型電子機器に於いては、絶縁層(プリプレグ)とコア(銅張積層板)とを交互に積層した多層プリント配線板が広く用いられる。この種、多層プリント配線板には、配線パターンに加え、上記積層された配線板を貫通するスルーホール、上記配線板を貫通しないブラインドビア(blind via hole)等が設けられる。   In various small electronic devices including information processing devices, multilayer printed wiring boards in which insulating layers (prepregs) and cores (copper-clad laminates) are alternately laminated are widely used. In this type of multilayer printed wiring board, in addition to the wiring pattern, a through hole that penetrates the laminated wiring board, a blind via hole that does not penetrate the wiring board, and the like are provided.

多層プリント配線板に於けるブラインドビアの成形技術として、従来では、絶縁層に、コア部材に向けて穴加工を施し、この穴の先端をコア部材に形成した内層ランドに当接させてブラインドビアを形成する際に、ブラインドビア内壁のめっき層と絶縁層との熱膨張係数の違いに起因する熱ストレスによるめっき層の亀裂を低減するため、ビア形成周部(穴形成周部)に導体層を設けてビア形成周部の絶縁層を薄くする技術が存在する。このように従来技術では、絶縁層よりコア部材に向けて穴加工を施して形成するブラインドビアに対して、絶縁層の膜厚を薄くすることで、ブラインドビア内壁のめっき層と絶縁層との熱膨張係数の違いに起因する熱ストレスによるめっき層の亀裂の低減を図っている。   As a technique for forming blind vias in multilayer printed wiring boards, conventionally, via holes are drilled in the insulating layer toward the core member, and the tip of each hole is brought into contact with an inner land formed in the core member to blind blind vias. In order to reduce cracks in the plating layer due to thermal stress due to the difference in thermal expansion coefficient between the plating layer on the inner wall of the blind via and the insulating layer, the conductor layer is formed on the via formation peripheral part (hole formation peripheral part). There is a technique for thinning the insulating layer in the periphery of the via formation. As described above, in the prior art, the thickness of the insulating layer is reduced with respect to the blind via formed by drilling the insulating layer toward the core member. The crack of the plating layer due to the thermal stress caused by the difference in thermal expansion coefficient is reduced.

しかしながら、従来では、ドリル加工でコア部材に所定径の孔を穿設し、その孔の穿設方向先端をコア部材に形成したランドに当接させてブラインドビアを形成するブラインドビアの加工技術に関して、歩留まりを改善する効果的な技術が存在しなかった。   However, conventionally, a blind via processing technique in which a hole having a predetermined diameter is formed in a core member by drilling, and a tip of the hole in the drilling direction is brought into contact with a land formed in the core member to form a blind via. There was no effective technique to improve the yield.

特に、近年、プリント配線板の信号パターンは、高密度配線をするため、益々細くなる傾向がある。細い信号パターン(配線パターン)を形成するには、配線パターンの厚さ(導体厚)を薄くすることがパターン形成並びに歩留まりの面から望ましい。通常、上記ブラインドビアの受けランドはパターンエッチング等により同層の配線パターンと同時に形成される。従って配線パターンの厚さを薄くすると上記ブラインドビアの受けランドもその導体厚が薄くなってしまう。上記ブラインドビア受けランドの導体厚が薄くなると、上記したようなドリル加工でコア部材に穿設し、その穿設方向先端をコア部材に形成したランドに当接させてブラインドビアを形成するブラインドビアの加工技術に於いて、ドリル加工の深さ制御が正常なブラインドビア形成に大きく影響し、歩留まりの問題が派生する。具体的にはコア部材に形成した穴が浅い場合は回路の未接続による不良を招き、上記穴が深い場合はその穿設方向先端にある他層との回路接続による不良を招くという歩留まりの問題が生じる。さらに、この際、絶縁層を表層とした積層構造が一般的であり、コアの厚さ方向の寸法精度に対して絶縁層の厚さ方向の寸法精度が劣ることから、上記した問題点がより顕著になる。
特開平8−32233号公報
In particular, in recent years, signal patterns on printed wiring boards tend to become thinner and thinner due to high density wiring. In order to form a thin signal pattern (wiring pattern), it is desirable in terms of pattern formation and yield to reduce the thickness of the wiring pattern (conductor thickness). Usually, the blind via receiving land is formed simultaneously with the wiring pattern of the same layer by pattern etching or the like. Therefore, if the thickness of the wiring pattern is reduced, the conductor land of the blind via receiving land is also reduced. When the conductor thickness of the blind via receiving land is reduced, the blind via is formed in the core member by drilling as described above and the tip in the drilling direction is brought into contact with the land formed in the core member. In this processing technology, drilling depth control greatly affects the formation of normal blind vias, resulting in yield problems. Specifically, when the hole formed in the core member is shallow, a defect due to unconnected circuit is caused, and when the hole is deep, a defect due to circuit connection with another layer at the tip of the drilling direction is caused. Occurs. Further, at this time, a laminated structure with the insulating layer as a surface layer is common, and the dimensional accuracy in the thickness direction of the insulating layer is inferior to the dimensional accuracy in the thickness direction of the core. Become prominent.
Japanese Patent Laid-Open No. 8-32233

上述したように、従来では、ドリル加工でコア部材に穿設し、その穿設方向先端をコア部材に形成したランドに当接させてブラインドビアを形成するブラインドビアの加工技術に於いて、ドリル加工の深さ制御が正常なブラインドビア形成に大きく影響し、ブラインドビア加工の容易化並びに歩留まりの面で問題があった。   As described above, conventionally, in the blind via machining technique in which a drill is drilled in a core member and a blind via is formed by abutting a tip formed in the drilling direction on a land formed in the core member. Control of the processing depth has a great influence on the formation of normal blind vias, and there are problems in terms of ease of blind via processing and yield.

本発明は上記実情に鑑みなされたもので、信頼性の高いブラインドビアを設けた多層プリント配線板、および信頼性の高いブラインドビアを容易に形成可能な多層プリント配線板の製造方法を提供することを目的とする。   The present invention has been made in view of the above circumstances, and provides a multilayer printed wiring board provided with a highly reliable blind via and a method for manufacturing a multilayer printed wiring board capable of easily forming a highly reliable blind via. With the goal.

本発明は、ドリル加工でコア部材に穿設し、その穿設方向先端をコア部材に形成したランドに当接させてブラインドビアを形成する多層プリント配線板に於いて、コアと、前記コアに形成された配線パターンと、前記コアに前記配線パターンの面より突出する方向に肉厚に形成されたブラインドビアの受けランドと、前記コアに前記受けランドと対向する面より穿設され、その穿設方向先端が前記受けランドに当接して形成されたブラインドビアとを具備したことを特徴とする。   The present invention relates to a multilayer printed wiring board in which a drill is drilled in a core member and a blind via is formed by contacting a tip formed in the drilling direction with a land formed in the core member. The formed wiring pattern, the receiving land of the blind via formed in the core in a direction protruding from the surface of the wiring pattern, and the core are formed from the surface facing the receiving land, And a blind via formed at its front end in contact with the receiving land.

また本発明は、コア部にブラインドビアを受けるランドおよび配線パターンを形成し、前記コア部の前記ランド形成面と対向する面からドリル加工により所定径の孔を穿設し、前記穿設した孔の内壁とその孔に当接した前記ランド面とにめっきを施して前記コア部に絶縁層を介しブラインドビアを形成するプリント配線板の製造方法に於いて、前記ブラインドビアの穿設方向先端部に設けられる前記ブラインドビアを受けるランドの導体厚を同層の前記配線パターンより厚くしたことを特徴とする。   In the present invention, a land and a wiring pattern for receiving a blind via are formed in the core portion, a hole having a predetermined diameter is drilled from a surface of the core portion facing the land forming surface, and the drilled hole is formed. In the method of manufacturing a printed wiring board, in which a blind via is formed on the core portion through an insulating layer by plating the inner wall of the substrate and the land surface in contact with the hole, the tip end portion of the blind via in the drilling direction The land receiving the via via is provided with a conductor thickness larger than that of the wiring pattern in the same layer.

ドリル加工でコア部材に所定径の穿設し、その孔の穿設方向先端をコア部材に形成したランドに当接させてブラインドビアを形成した多層プリント配線板に於いて、信頼性の高いブラインドビアを設けた多層プリント配線板を歩留まり良く容易に実現できる。   A highly reliable blind in a multilayer printed wiring board in which a drill hole is drilled to a predetermined diameter in the core member, and a blind via is formed by contacting the tip of the hole in the drilling direction with a land formed in the core member. A multilayer printed wiring board provided with vias can be easily realized with a high yield.

以下図面を参照して本発明の実施形態を説明する。   Embodiments of the present invention will be described below with reference to the drawings.

本発明は、ドリル加工でコア部材に所定径の孔を穿設し、その孔の穿設方向先端をコア部材に形成したランドに当接させてブラインドビアを形成する際に、コア部材に形成した上記ランド(ブラインドビアの受けランド)を上記コア部材に形成した配線パターンの厚さより厚く形成することで、ドリル加工に要求される深さ方向の寸法精度の許容範囲を拡げることができるとともに、ブラインドビアとその受けランドとの間に十分な接合面積を確保でき、これによって歩留まりの良い状態で信頼性の高いブラインドビアを容易に形成できるようにしている。   In the present invention, a hole having a predetermined diameter is drilled in a core member by drilling, and a blind via is formed in the core member when a tip in the drilling direction is brought into contact with a land formed in the core member. By forming the land (the receiving land of the blind via) thicker than the thickness of the wiring pattern formed on the core member, it is possible to expand the allowable range of dimensional accuracy in the depth direction required for drilling, A sufficient bonding area can be ensured between the blind via and its receiving land, so that a highly reliable blind via can be easily formed in a high yield state.

図1に本発明の第1実施形態による多層プリント配線板1Aのブラインドビア構造を示している。この多層プリント配線板1Aは、絶縁層(プリプレグ)18と、コア部材(銅張積層板)10とを交互に温度および圧力をかけて積層したn層で構成している。このn層構成の多層プリント配線板1Aには、全層を貫通するスルーホール13と、所定の層までしか貫通しないブラインドビア11と、配線パターン14(内層配線パターン14−1,14−2,…)とを有して構成される。   FIG. 1 shows a blind via structure of a multilayer printed wiring board 1A according to the first embodiment of the present invention. This multilayer printed wiring board 1A is composed of n layers in which insulating layers (prepregs) 18 and core members (copper-clad laminates) 10 are alternately laminated by applying temperature and pressure. The n-layer multilayer printed wiring board 1A includes a through hole 13 that penetrates all layers, a blind via 11 that penetrates only to a predetermined layer, and a wiring pattern 14 (inner wiring patterns 14-1, 14-2, ...).

図1に示す多層プリント配線板1Aは、第2層(L2)と第3層(L3)に設けられるコア部材10の第3層(L3)、および第n−1層(Ln−1)と第n−2層(Ln−2)に設けられるコア部材10の第n−2層(Ln−2)に、それぞれ上記ブラインドビア11,11の受けランド12,12を設けて、そのブラインドビア11,11により、第1層(表層)と第3層(L3)、および第n層(表層)と第n−2層(Ln−2)をそれぞれ回路接続した例を示している。   A multilayer printed wiring board 1A shown in FIG. 1 includes a third layer (L3) and a (n-1) th layer (Ln-1) of the core member 10 provided in the second layer (L2) and the third layer (L3). Receiving lands 12 and 12 for the blind vias 11 and 11 are provided in the n-2th layer (Ln-2) of the core member 10 provided in the n-2th layer (Ln-2). , 11 shows an example in which the first layer (surface layer) and the third layer (L3), and the n-th layer (surface layer) and the n-2th layer (Ln-2) are connected to each other.

ここで上記各ブラインドビア11,11の受けランド(以下ビア受けランドと称す)12,12は、図示するように、それぞれ同層の内層配線パターン厚より肉厚に形成される。例えば第3層(L3)の配線パターン14−3の導体厚をTh1とすると、コア部材10の第3層(L3)には上記導体厚Th1より厚い、導体厚Th2のビア受けランド12が形成される。上記第n−2層(Ln−2)にも上記第3層(L3)と同様の導体厚(Th2)をもつビア受けランド12が形成される。   Here, the receiving lands (hereinafter referred to as via receiving lands) 12 and 12 of the blind vias 11 and 11 are formed thicker than the inner layer wiring pattern thickness of the same layer as shown in the figure. For example, if the conductor thickness of the wiring pattern 14-3 on the third layer (L3) is Th1, the via receiving land 12 having a conductor thickness Th2 that is thicker than the conductor thickness Th1 is formed on the third layer (L3) of the core member 10. Is done. Via receiving lands 12 having the same conductor thickness (Th2) as the third layer (L3) are also formed in the n-2th layer (Ln-2).

上記ビア受けランド12,12を設けたコア部材10,10に、ドリル加工で、絶縁層18,18を介して上記ビア受けランド12,12と対向する面方向より、上記ビア受けランド12,12に接する深さまで所定径の孔を穿設し、その孔の内壁に所定のめっきを施すことで、上記各層間(L1,L3間、およびLn,Ln−2間)を回路接続するブラインドビア11,11が形成される。この際のドリル加工工程とめっき工程を図4(a),(b)に例示している。   The core members 10 and 10 provided with the via receiving lands 12 and 12 are drilled to the via receiving lands 12 and 12 from the surface direction facing the via receiving lands 12 and 12 through the insulating layers 18 and 18. Blind vias 11 for connecting circuits between the layers (between L1 and L3 and between Ln and Ln-2) by drilling holes with a predetermined diameter to a depth in contact with each other and applying predetermined plating to the inner walls of the holes , 11 are formed. The drilling process and the plating process at this time are illustrated in FIGS. 4 (a) and 4 (b).

上記したように、ビア受けランド12,12の導体厚を配線パターン14の導体厚より厚くした(TH1<TH2)ことにより、上記ドリル加工に要求される深さ方向の寸法精度の許容範囲を拡げることができることから、常に歩留まりの良い状態で信頼性の高いブラインドビアを有した多層プリント配線板を製造できる。さらにビア受けランド12,12の導体厚を配線パターン14の導体厚より厚くしたことにより、ブラインドビア11,11に於けるビア受けランド12,12の接合面積が増し、電気的抵抗の少ない安定したブラインドビアの回路を構成できるとともに、ビア受けランドの導体厚を意識することなく配線パターンの導体厚を薄くすることができることから多層プリント配線板1Aの薄型化に寄与できる。さらに、この実施形態によるブラインドビア構造はコア部材に穿設した孔にブラインドビアが形成されることから、上述した従来技術のようなブラインドビア内壁のめっき層と絶縁層との熱膨張係数の違いに起因する熱ストレスによるめっき層の亀裂を招く虞のない信頼性の高いブラインドビアを構成できる。   As described above, by making the conductor thickness of the via receiving lands 12 and 12 larger than the conductor thickness of the wiring pattern 14 (TH1 <TH2), the allowable range of the dimensional accuracy in the depth direction required for the drilling process is expanded. Therefore, it is possible to manufacture a multilayer printed wiring board having blind vias with high reliability at a high yield. Furthermore, by making the conductor thickness of the via receiving lands 12 and 12 thicker than the conductor thickness of the wiring pattern 14, the junction area of the via receiving lands 12 and 12 in the blind vias 11 and 11 is increased, and the electrical resistance is stable and less. A circuit of a blind via can be configured, and the conductor thickness of the wiring pattern can be reduced without being aware of the conductor thickness of the via receiving land, which can contribute to the thinning of the multilayer printed wiring board 1A. Further, in the blind via structure according to this embodiment, since the blind via is formed in the hole drilled in the core member, the difference in thermal expansion coefficient between the plated layer and the insulating layer of the inner wall of the blind via as described above. Thus, a highly reliable blind via can be configured without the risk of causing cracks in the plating layer due to thermal stress caused by the above.

上記した配線パターンの導体厚Th1より厚い、導体厚Th2のビア受けランド12を形成する際のビア受けランド12,12の加工例を図3に示している。尚、この図3に示す工程は、コア部材10となる銅張積層板30の両面に上記したような肉厚のビア受けランドを形成する例を示している。   FIG. 3 shows a processing example of the via receiving lands 12 and 12 when forming the via receiving lands 12 having the conductor thickness Th2 which is thicker than the conductor thickness Th1 of the wiring pattern described above. The process shown in FIG. 3 shows an example in which the above-described thick via receiving lands are formed on both surfaces of the copper-clad laminate 30 serving as the core member 10.

この図3に示すビア受けランドの加工工程は、先ずコア部材10となる銅張積層板30の各面の銅泊31を各々面毎にエッチングして(図3(a)参照)、各面毎に、配線パターン31−1,31−1,…、31−2,31−2,…と、上記ビア受けランド12の基となるランド32−1、32−2とを同時に形成する(図3(b)参照)。その後、スキージ40により、上記ランド32−1、32−2の上にそれぞれ導電ペースト41−1、41−2を印刷し、硬化する(図3(c)から(e)参照)。このの工程により、ブラインドビア11,11を受けるビア受けランド12,12の部分だけ導体厚を厚くすることができる。   The via receiving land processing step shown in FIG. 3 is performed by first etching the copper stays 31 on each surface of the copper clad laminate 30 serving as the core member 10 for each surface (see FIG. 3A). Each of the wiring patterns 31-1, 31-1,..., 31-2, 31-2,... And the lands 32-1 and 32-2 that form the basis of the via receiving land 12 are simultaneously formed (see FIG. 3 (b)). Thereafter, the conductive pastes 41-1 and 41-2 are printed on the lands 32-1 and 32-2, respectively, by the squeegee 40 and cured (see FIGS. 3C to 3E). With this process, the conductor thickness can be increased only in the via receiving lands 12 and 12 that receive the blind vias 11 and 11.

図2に本発明の第2実施形態による多層プリント配線板1Bのブラインドビア構造を示している。この多層プリント配線板1Bは、上述の第1実施形態とは異なり、コア部材20により表層を形成して、絶縁層28とコア部材20との交互の積層によりn層を構成している。このn層構成の多層プリント配線板1Bには、全層を貫通するスルーホール23と、上記表層を形成したコア部材20に設けたブラインドビア21と、配線パターン24(24−1,24−2,…)とを有して構成される。   FIG. 2 shows a blind via structure of the multilayer printed wiring board 1B according to the second embodiment of the present invention. Unlike the above-described first embodiment, the multilayer printed wiring board 1 </ b> B forms a surface layer by the core member 20, and forms an n layer by alternately stacking the insulating layers 28 and the core member 20. In this multilayer printed wiring board 1B having an n-layer structure, through holes 23 penetrating all layers, blind vias 21 provided in the core member 20 on which the surface layer is formed, and wiring patterns 24 (24-1, 24-2). ,...

図2に示す多層プリント配線板1Bは、表層となる第1層(L1)と第2層(L2)に設けられるコア部材20の第2層(L2)、および表層となる第n層(Ln)と第n−1層(Ln−1)に設けられるコア部材20の第n−1層(Ln−1)に、それぞれ上記ブラインドビア21,21の受けランド22,22を設けて、ブラインドビア21,21により、第1層(表層)と第2層(L2)、および第n層(表層)と第n−1層(Ln−1)をそれぞれ回路接続した例を示している。   A multilayer printed wiring board 1B shown in FIG. 2 includes a first layer (L1) serving as a surface layer, a second layer (L2) of the core member 20 provided on the second layer (L2), and an nth layer (Ln) serving as a surface layer. ) And the n-1 layer (Ln-1) of the core member 20 provided in the n-1 layer (Ln-1) are provided with receiving lands 22 and 22 for the blind vias 21 and 21, respectively. 21 and 21 show an example in which the first layer (surface layer) and the second layer (L2), and the n-th layer (surface layer) and the n-1th layer (Ln-1) are connected to each other.

この第2実施形態に於いても上記第1実施形態と同様に、上記各ブラインドビア21,21の受けランド22,22をそれぞれ同層の内層配線パターン厚より肉厚に形成している。これにより、ブラインドビア21,21を形成する際のドリル加工に要求される深さ方向の寸法精度の許容範囲を拡げることができ、常に歩留まりの良い状態で信頼性の高いブラインドビアを有した多層プリント配線板を製造できる。さらにビア受けランド22,22の導体厚を配線パターン24の導体厚より厚くしたことにより、ブラインドビア21,21に於けるビア受けランド22,22の接合面積が増し、電気的抵抗の少ない安定したブラインドビアの回路を構成できるとともに、ビア受けランドの導体厚を意識することなく配線パターンの導体厚を薄くすることができることから多層プリント配線板1Bを薄型化することができる。さらに、この実施形態によるブラインドビア構造はコア部材に穿設した孔によってブラインドビアを形成することから、上述した従来技術のようなブラインドビア内壁のめっき層と絶縁層との熱膨張係数の違いに起因する熱ストレスによるめっき層の亀裂を招く虞のない信頼性の高いブラインドビアを構成できる。   In the second embodiment, as in the first embodiment, the receiving lands 22 and 22 of the blind vias 21 and 21 are formed thicker than the inner wiring pattern thickness of the same layer. As a result, the tolerance range of the dimensional accuracy in the depth direction required for drilling when forming the blind vias 21 and 21 can be expanded, and a multilayer having a highly reliable blind via always in a good yield state. A printed wiring board can be manufactured. Furthermore, by making the conductor thickness of the via receiving lands 22 and 22 thicker than the conductor thickness of the wiring pattern 24, the junction area of the via receiving lands 22 and 22 in the blind vias 21 and 21 is increased, and the electrical resistance is stable and less. The circuit of the blind via can be configured, and the thickness of the wiring pattern conductor can be reduced without being aware of the conductor thickness of the via receiving land, so that the multilayer printed wiring board 1B can be reduced in thickness. Furthermore, since the blind via structure according to this embodiment forms the blind via by the hole drilled in the core member, the difference in the thermal expansion coefficient between the plating layer and the insulating layer of the inner wall of the blind via as described above. A highly reliable blind via that does not cause a crack of the plating layer due to the resulting thermal stress can be configured.

本発明の第1実施形態に係る多層プリント配線板の構成を示す断面図。Sectional drawing which shows the structure of the multilayer printed wiring board which concerns on 1st Embodiment of this invention. 本発明の第2実施形態に係る多層プリント配線板の構成を示す断面図。Sectional drawing which shows the structure of the multilayer printed wiring board which concerns on 2nd Embodiment of this invention. 本発明の実施形態に係るビア受けランドの加工工程を示す工程図。Process drawing which shows the processing process of the via receiving land which concerns on embodiment of this invention. 本発明の実施形態に係るビア受けランドのドリル加工およびめっき工程を示す工程図。Process drawing which shows the drill process and plating process of the via receiving land which concern on embodiment of this invention.

符号の説明Explanation of symbols

1A,1B…多層プリント配線板、10,20…コア部材(銅張積層板)、11,21…ブラインドビア、12,22…ビア受けランド、13,23…スルーホール、14−1,14−2,24−1,24−2,24−3…配線パターン、18,28…絶縁層(プリプレグ)、TH1…配線パターンの導体厚、TH2…ビア受けランドの導体厚。   1A, 1B ... multilayer printed wiring board, 10, 20 ... core member (copper-clad laminate), 11, 21 ... blind via, 12, 22 ... via receiving land, 13, 23 ... through hole, 14-1, 14- 2, 24-1, 24-2, 24-3 ... wiring pattern, 18, 28 ... insulating layer (prepreg), TH1 ... conductor thickness of wiring pattern, TH2 ... conductor thickness of via receiving land.

Claims (6)

コアと、
前記コアに形成された配線パターン、および当該配線パターンより肉厚のランドと、
前記コアに前記ランドと対向する面方向より穿設され、その穿設方向先端が前記ランドに当接して形成されたブラインドビアと
を具備したことを特徴とする多層プリント配線板。
The core,
A wiring pattern formed on the core, and a land thicker than the wiring pattern;
A multilayer printed wiring board, comprising: a blind via formed in the core in a surface direction opposite to the land, the tip of the drilling direction being in contact with the land.
前記ブラインドビアは、ドリル加工により、前記コアの前記ランド形成面と対向する面から前記ランド内に達する穴を穿設し、その穴の内壁にめっきを施して形成した請求項1記載の多層プリント配線板。   2. The multilayer print according to claim 1, wherein the blind via is formed by drilling a hole reaching the land from a surface facing the land forming surface of the core and plating the inner wall of the hole. Wiring board. 前記ブラインドビアは、絶縁層により形成した表層から、前記ランドを設けた内層コアを介して、前記内層コアに設けたランドに至る穴の内壁にめっきを施して形成した請求項2記載の多層プリント配線板。   3. The multilayer print according to claim 2, wherein the blind via is formed by plating an inner wall of a hole extending from a surface layer formed of an insulating layer to a land provided in the inner layer core through an inner layer core provided with the land. Wiring board. 前記ブラインドビアは、前記コアにより形成した表層から、前記コアを介して、前記コアに設けたランドに至る穴の内壁にめっきを施して形成した請求項2記載の多層プリント配線板。   The multilayer printed wiring board according to claim 2, wherein the blind via is formed by plating an inner wall of a hole extending from a surface layer formed by the core to a land provided in the core via the core. コア部にブラインドビアを受けるランドおよび配線パターンを形成し、前記コア部の前記ランド形成面と対向する面方向からドリル加工により所定径の孔を穿設し、前記穿設した孔の内壁とその孔に当接した前記ランド面とにめっきを施して前記コア部に絶縁層を介して若しくは絶縁層を介さずにブラインドビアを形成するプリント配線板の製造方法に於いて、
前記ブラインドビアの穿設方向先端部に設けられる前記ブラインドビアを受けるランドの導体厚を同層の前記配線パターンより厚くしたことを特徴とする多層プリント配線板の製造方法。
A land and a wiring pattern for receiving blind vias are formed in the core portion, a hole having a predetermined diameter is drilled from a surface direction of the core portion facing the land forming surface, and an inner wall of the drilled hole and its inner wall In the method of manufacturing a printed wiring board in which the land surface in contact with the hole is plated and a blind via is formed in the core portion without an insulating layer or an insulating layer.
A method of manufacturing a multilayer printed wiring board, wherein a conductor thickness of a land that receives the blind via provided at a front end portion of the blind via is made thicker than the wiring pattern of the same layer.
前記ブラインドビアを受けるランドは、前記コア部に内層パターンをエッチングで形成し、その後、ブラインドビアを受けるランドにあたる内層パターン部分の面上に導電ペーストを印刷し、硬化することによって、所定の導体厚に形成したことを特徴とする請求項5記載の多層プリント配線板の製造方法。   The land that receives the blind via is formed by etching an inner layer pattern on the core portion, and then printed and cured with a conductive paste on the surface of the inner layer pattern portion that corresponds to the land that receives the blind via. The method for producing a multilayer printed wiring board according to claim 5, wherein the multilayer printed wiring board is formed.
JP2003400905A 2003-11-28 2003-11-28 Multilayer printed wiring board and method for producing multilayer printed wiring board Pending JP2005166764A (en)

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TW093124206A TWI293015B (en) 2003-11-28 2004-08-12 Multilayered printed wiring board and method for manufacturing the multilayered printed wiring board
KR1020040068426A KR100654283B1 (en) 2003-11-28 2004-08-30 Multilayered printed wiring board and method for manufacturing the multilayered printed wiring board
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KR100745520B1 (en) * 2006-01-20 2007-08-02 삼성전기주식회사 Multilayer printed circuit board and its manufacturing method
JP5165265B2 (en) * 2007-03-23 2013-03-21 日本メクトロン株式会社 Manufacturing method of multilayer printed wiring board
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