JP2000031644A - Circuit board - Google Patents
Circuit boardInfo
- Publication number
- JP2000031644A JP2000031644A JP19823298A JP19823298A JP2000031644A JP 2000031644 A JP2000031644 A JP 2000031644A JP 19823298 A JP19823298 A JP 19823298A JP 19823298 A JP19823298 A JP 19823298A JP 2000031644 A JP2000031644 A JP 2000031644A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- circuit board
- copper
- connection
- connection hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 54
- 238000007747 plating Methods 0.000 claims abstract description 52
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 27
- 229910052802 copper Inorganic materials 0.000 claims abstract description 26
- 239000010949 copper Substances 0.000 claims abstract description 26
- 239000012212 insulator Substances 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 10
- 230000006866 deterioration Effects 0.000 claims abstract description 7
- 230000005684 electric field Effects 0.000 claims abstract description 5
- 239000004020 conductor Substances 0.000 claims description 8
- 239000011889 copper foil Substances 0.000 claims description 8
- 238000007772 electroless plating Methods 0.000 claims description 4
- 239000010953 base metal Substances 0.000 claims description 2
- 239000003822 epoxy resin Substances 0.000 abstract description 3
- 229920000647 polyepoxide Polymers 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 8
- 230000007797 corrosion Effects 0.000 description 7
- 238000005260 corrosion Methods 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 230000035515 penetration Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 2
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 2
- 229910001431 copper ion Inorganic materials 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000007654 immersion Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000006071 cream Substances 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- FBAFATDZDUQKNH-UHFFFAOYSA-M iron chloride Chemical compound [Cl-].[Fe] FBAFATDZDUQKNH-UHFFFAOYSA-M 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、回路基板に係る高
温多湿な高電界環境下において、特に、経由導通接続穴
の電気的な接続特性に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrical connection characteristic of a via connection hole in a high-temperature, high-humidity, high-field environment relating to a circuit board.
【0002】[0002]
【従来の技術】近年、電子機器の多機能化用途にともな
い高温多湿な高電界環境下において、より一層の電気的
接続信頼性の向上が要求され、この対応としてまず下地
銅めっき膜を形成し、これにニッケルめっき膜を被覆形
成する製造方法等が用いられ、下記に示す製造工程にて
作製されている。以下、従来の技術に係る製造工程にお
いて、図5に基づき説明する。2. Description of the Related Art In recent years, further improvements in electrical connection reliability have been demanded in a high-temperature, high-humidity, high-electric-field environment accompanying multifunctional use of electronic devices. A manufacturing method or the like of coating a nickel plating film thereon is used, and is manufactured by the following manufacturing process. Hereinafter, a manufacturing process according to a conventional technique will be described with reference to FIG.
【0003】先ず、従来技術の回路配線板38として
は、図5に示すように表裏銅箔29,絶縁基板28とか
ら構成された銅張ガラス積層板を用い、これにドリルに
よって選択的に貫通穴30を穿設して、この貫通穴30
内壁及び表裏上に化学めっきと電解銅めっきを併用施
し、下地銅めっき膜31から形成された導通接続穴32
を得、この下地上に電解めっき液に浸漬してニッケルめ
っき膜34を被覆してなる経由導通接続穴36を形成す
る。First, as a conventional circuit wiring board 38, as shown in FIG. 5, a copper-clad glass laminated board composed of a front and back copper foil 29 and an insulating substrate 28 is used, and is selectively penetrated by a drill. A hole 30 is formed, and the through hole 30 is formed.
A conductive connection hole 32 formed from a base copper plating film 31 by simultaneously performing chemical plating and electrolytic copper plating on the inner wall and the front and back.
Then, the via connection hole 36 formed by coating the nickel plating film 34 by dipping in the electrolytic plating solution is formed on the base.
【0004】次いで、感光性ドライフィルムを用い、露
光・現像・エッチング(塩化鉄溶液や過硫酸アンモニウ
ム溶液を用いる。)・剥離工程を経てなる導通接続穴ラ
ンド37や外層ランドを形成した後、スクリーン印刷法
を用い、ソルダーレジスト33を塗布形成し得た従来の
技術に係る回路基板38が得られる。Then, using a photosensitive dry film, a conductive connection hole land 37 and an outer layer land formed through exposure, development, etching (using an iron chloride solution or an ammonium persulfate solution) and a stripping process, and then screen printing. A circuit board 38 according to the prior art, in which the solder resist 33 is applied and formed by the method, is obtained.
【0005】[0005]
【発明が解決しようとする課題】しかしながら、上述し
た従来の技術に係る回路基板38では、まず、第1とし
ては、前記貫通穴30の内壁表面に存在する前記絶縁基
板28内のガラス繊維に沿って、前記化学めっき処理を
施す場合に用いる銅化学めっき液が中心部へ移行浸入す
ることにより、高温多湿な高電界環境下において使用さ
れる場合に、電気的特性劣化(耐電食性の劣化)が起き
るという問題がある。However, in the circuit board 38 according to the prior art described above, firstly, first, along the glass fiber in the insulating substrate 28 existing on the inner wall surface of the through hole 30. In addition, the copper chemical plating solution used in performing the chemical plating treatment migrates and penetrates into the central portion, so that when used in a high-temperature, high-humidity, high-electric field environment, electrical characteristic deterioration (deterioration of electrolytic corrosion resistance) is reduced. There is a problem of getting up.
【0006】次いで、第2としては、実装部品搭載後3
回リフロー炉を通過する場合に高温(約180〜280
℃範囲)環境下において、前記貫通穴30の内壁と銅め
っき膜31へ生ずる熱応力の集中に起因する圧縮応力を
受けて銅めっき膜31の疲労により穴中央全周にバレル
クラックが生じ、導通接続穴32・36の電気的接続信
頼性の低下の要因になるという問題がある。[0006] Second, after mounting the mounted components, 3
High temperature (about 180-280)
Under the environment, a compressive stress caused by a concentration of thermal stress generated on the inner wall of the through hole 30 and the copper plating film 31 is received, and a fatigue of the copper plating film 31 causes a barrel crack around the entire center of the hole due to fatigue of the copper plating film 31. There is a problem that the electrical connection reliability of the connection holes 32 and 36 is reduced.
【0007】また、前記銅めっき膜31のバレルクラッ
クの発生を防止するために、銅めっき膜31の膜厚を厚
く形成する必要が生ずるが微細配線が要求されている現
状においては、適していない。Further, in order to prevent the occurrence of barrel cracks in the copper plating film 31, it is necessary to form the copper plating film 31 with a large thickness, but this is not suitable in the current situation where fine wiring is required. .
【0008】この発明は、上記の事情を鑑みてなされた
ものであり、この目的とするところは、高温多湿な高電
界環境下での特性劣化防止もしくは経由導通接続穴16
・17の電気的接続信頼性により一層優れた回路基板2
7を提供することにある。The present invention has been made in view of the above circumstances, and an object of the present invention is to prevent deterioration of characteristics in a high-temperature, high-humidity, high-electric-field environment, or to provide a via hole 16.
・ Circuit board 2 with better electrical connection reliability of 17
7 is provided.
【0009】[0009]
【課題を解決するための手段】本発明では、内層銅箔1
・2,有機絶縁層5・6,内層導体3・4とから構成さ
れる両面または多層有機銅張積層板7を用い、前記内層
導体3・4に電気的に接続された経由導通接続穴17,
外層ランド24・25とをもつ回路基板にあって、前記
表裏全面及び導通接続穴16の下地金属膜厚は、0.6
〜12μm範囲のダイレクト式電解ニッケルめっき膜9
・10によって形成されており、この下地ニッケルめっ
き膜9・10の表面を金属膜厚15〜35μm範囲の電
解銅めっき膜11・12により被覆された経由導通接続
穴17を形成して、この穴17内に有機絶縁体13を形
成し、これにフォトエッチング法により、外層ランド1
4・15,導通接続ランド18・19とを形成した後、
無電解めっき永久レジスト20・21を形成して、実装
部品固定に用いる最外層接続パッド22・23とを有
し、さらに高温多湿な高電界な環境下においても耐電食
性や電気的接続信頼性の劣化を防止しようとするもので
ある。According to the present invention, an inner copper foil 1 is provided.
A via connection hole 17 electrically connected to the inner conductors 3, 4 using a double-sided or multi-layer organic copper-clad laminate 7 composed of organic insulation layers 5, 6 and inner conductors 3, 4; ,
In the circuit board having the outer layer lands 24 and 25, the thickness of the base metal film of the entire front and back surfaces and the conductive connection holes 16 is 0.6.
Direct electrolytic nickel plating film 9 in the range of 12 μm
And via holes 17 formed by covering the surfaces of the base nickel plating films 9 and 10 with electrolytic copper plating films 11 and 12 having a metal film thickness of 15 to 35 μm. 17, an organic insulator 13 is formed, and an outer land 1 is formed on the organic insulator 13 by a photo-etching method.
After forming 4.15 and conductive connection lands 18 and 19,
Electroless plating permanent resists 20 and 21 are formed to have outermost layer connection pads 22 and 23 used for fixing mounted components. Further, even in a high-temperature, high-humidity, and high-field environment, the electrolytic corrosion resistance and electrical connection reliability are improved. It is intended to prevent deterioration.
【0010】[0010]
【発明の実施の形態】本発明の回路基板27は図1に示
すように、有機絶縁層5・6に形成した内層銅箔1・
2,内装導体3・4とこれらの内層銅箔1・2,内層導
体3・4と電気的に接続された導通接続穴16・17を
有し、この穴17内に有機絶縁体13を充填・形成し、
金属めっき膜11・12を保護し、この穴17上の導通
接続穴ランド18・19の表裏上に最外層接続パッド2
2・23を形成し得、実装部品固定用の占有面積を小さ
く構成でき得るとともに経由導通接続穴17を有するも
のである。DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, a circuit board 27 according to the present invention has an inner copper foil 1 formed on organic insulating layers 5 and 6.
2, inner conductors 3 and 4, conductive connection holes 16 and 17 electrically connected to inner copper foils 1.2 and inner conductors 3.4, respectively, and filled with organic insulator 13 in holes 17;・ Form,
The outermost layer connection pads 2 are protected on the front and back surfaces of the conductive connection hole lands 18 and 19 on the holes 17 by protecting the metal plating films 11 and 12.
2 and 23 can be formed, the occupied area for mounting component fixing can be reduced, and the via connection hole 17 is provided.
【0011】また前記貫通穴8の内壁には、膜厚0.6
〜12μm範囲の下地ニッケルめっき膜9・10によっ
て被覆され、この被覆表面上を電気銅めっき膜11・1
2により被覆され、この膜厚15〜35μm範囲に形成
されている。上述により高温多湿な高電界環境下におい
て、銅めっき液のしみ込み量35による電気的な特性の
劣化を防止できる。The inner wall of the through hole 8 has a thickness of 0.6.
1212 μm of the underlying nickel plating film 9.1, and the surface of this coating is covered with the electrolytic copper plating film 9.1.
2 and has a thickness of 15 to 35 μm. As described above, it is possible to prevent the deterioration of the electrical characteristics due to the penetration amount 35 of the copper plating solution under the high electric field environment of high temperature and humidity.
【0012】さらに、高リフロー炉通過する場合に、前
記導通接続穴16・17の中央部における銅めっき膜1
1・12が疲労し導通接続穴17の全周にわたって連続
するバレルクラックの発生を防止し、前記穴17内に有
機絶縁体13を充填形成したことにより、前記銅めっき
膜11・12への物理的なストレスを保護して、電気的
な接続信頼性の向上が実現可能になり得るものである。Further, when passing through the high reflow furnace, the copper plating film 1 at the center of the conductive connection holes 16 and 17 is formed.
1 and 12 are fatigued to prevent the occurrence of a continuous barrel crack over the entire circumference of the conductive connection hole 17, and the hole 17 is filled with the organic insulator 13 so that the copper plating films 11 and 12 can be physically protected. It is possible that the electrical connection reliability can be improved by protecting the electrical stress.
【0013】上述の発明により、回路基板27の耐電食
性,めっき液しみ込み量の防止及び、電気的な接続信頼
性のより一層の向上が実現可能になり得るものである
(表1参照)。According to the above-mentioned invention, the corrosion resistance of the circuit board 27, the prevention of the amount of plating solution permeation, and the further improvement of the electrical connection reliability can be realized (see Table 1).
【0014】[0014]
【実施例】以下、本発明の実施例を示す図2,図3及び
図4に基づいて、詳細に説明するが実施例1としては、
下地ニッケルめっき膜9・10膜厚約0.6μm,実施
例2としては、下地ニッケルめっき膜9・10膜厚約5
μm,実施例3としては、下地ニッケルめっき膜9・1
0膜厚約12μmにして以後の製造工程は、同一工程・
同一製造方法によって以下に記載のように作製した。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a detailed description will be given based on FIGS. 2, 3 and 4 showing an embodiment of the present invention.
The thickness of the underlying nickel plating film 9/10 is about 0.6 μm.
μm, as Example 3, the base nickel plating film 9.1
0 The film thickness is about 12 μm and the subsequent manufacturing steps are the same.
It was prepared as described below by the same manufacturing method.
【0015】(実施例1)まず、図2に示すように、有
機銅張積層板7(日立化成工業(株)社商品名:MCL
−E−67S)は、内層導体3・4,内層銅箔1・2及
び有機絶縁層5・6を積層接着して構成し、これに選択
的にドリルを使用し、自動数値穴明け機(日立精工機)
を用い、ステップ式により、穴径0.6mmの貫通穴8を
穿設した。Example 1 First, as shown in FIG. 2, an organic copper-clad laminate 7 (trade name: MCL, manufactured by Hitachi Chemical Co., Ltd.)
-E-67S) is constructed by laminating and bonding the inner conductors 3,4, the inner copper foils 1,2 and the organic insulating layers 5,6, and selectively using a drill, and using an automatic numerical drilling machine ( Hitachi Seiko Machine)
, A through hole 8 having a hole diameter of 0.6 mm was formed by a step method.
【0016】次に前記貫通穴8の内壁と表裏上をスミア
ー処理し、ダイレクト電解めっき法によってニッケルめ
っき膜9・10の膜厚0.6μmの下地を形成した。こ
れにより銅イオン移行をニッケル膜9・10により防止
可能になった。このニッケルめっき方法としては、例え
ば無電解ニッケルめっき法やダイレクトパネル電解ニッ
ケルめっき法とがあるが本実施例では、パネルダイレク
ト電解めっき法が電食抑制や均一性めっき付き回り性に
おいて優れているので適しているが無電解ニッケルめっ
き液でもよい。またニッケルめっき液としては、例え
ば、日本カニゼン製や奥野製薬製や上村工業製でよくこ
れに本発明では限定するものではない。Next, the inner wall and the upper and lower surfaces of the through hole 8 were subjected to a smear treatment, and a 0.6 μm-thick base of the nickel plating films 9 and 10 was formed by direct electrolytic plating. As a result, the migration of copper ions can be prevented by the nickel films 9 and 10. As the nickel plating method, for example, there is an electroless nickel plating method or a direct panel electrolytic nickel plating method. Although suitable, an electroless nickel plating solution may be used. The nickel plating solution may be, for example, Nippon Kanigen, Okuno Pharmaceutical or Uemura Kogyo, and is not limited to this in the present invention.
【0017】また、実施例2及び実施例3にて、貫通穴
8の内壁に下地ニッケルめっき膜9・10の形成を上述
の製造方法により作製した。In Examples 2 and 3, the nickel plating films 9 and 10 were formed on the inner walls of the through holes 8 by the above-described manufacturing method.
【0018】次いで、図3に示すように、電解銅めっき
を施し、導通接続穴(ニッケル)16の内壁及び表裏全
面上に金属(銅)めっき膜11・12膜厚約15〜35
μm範囲にて被覆形成する。Next, as shown in FIG. 3, electrolytic copper plating is performed, and metal (copper) plating films 11 and 12 are formed on the inner wall of the conductive connection hole (nickel) 16 and on the entire front and back surfaces to have a thickness of about 15 to 35.
A coating is formed in a range of μm.
【0019】また、前記経由導通接続穴17の穴内に前
記導通接続穴16・17の金属めっき膜11・12の疲
労によって穴17の全周にバレルクラックの発生を防止
するため、変性エポキシ樹脂とからなる有機絶縁体13
を充填・形成した後に、この表裏をフォト・エッチング
製法(エッチング工程:塩化第2鉄液,感光性ドライフ
ィルム:フオテックH−240)を用い、外層ランド1
4・15及び導通接続穴ランド18・19を形成する。Further, in order to prevent the occurrence of barrel cracks around the hole 17 due to the fatigue of the metal plating films 11 and 12 of the conductive connection holes 16 and 17 in the via connection hole 17, a modified epoxy resin is used. Organic insulator 13 consisting of
After filling and forming, the outer layer land 1 is covered with a photo-etching method (etching step: ferric chloride solution, photosensitive dry film: PHOTEC H-240).
4.15 and conductive connection hole lands 18 and 19 are formed.
【0020】次いで、図4に示すように、無電解めっき
永久レジスト20・21(日立化成工業(株)社製商品
名:SR−3000)の形成は、真空ラミネータ(日立
エーアイシー(株)社製商品名:HLM−V570)に
よりラミネートした後に本硬化して、露光・水系の現像
・剥離工程を経て形成する。Next, as shown in FIG. 4, the formation of the electroless plating permanent resists 20 and 21 (trade name: SR-3000 manufactured by Hitachi Chemical Co., Ltd.) was performed by using a vacuum laminator (Hitachi AIC Co., Ltd.). (Product name: HLM-V570), and after being fully cured, it is formed through an exposure / water-based development / peeling step.
【0021】次いで、粗化した後に無電解めっき液CC
−41(日立エーアイシー(株)製)を用い、穴17上
に膜厚20〜25μm程に最外層ランド24・25及び
最外層接続パッド22・23と形成し耐電食性・電気的
接続信頼性に優れた本発明の回路基板27が得られ、メ
タルスクリーン版を用い、前記回路基板27の表裏上に
はんだクリームを塗布した後に、フュージング工程を経
て、最外層接続パッド22・23及び最外層ランド24
・25上に膜厚70μmのはんだ層26が得られるもの
である。Next, after roughening, the electroless plating solution CC
Using -41 (manufactured by Hitachi AIC Co., Ltd.), the outermost layer lands 24 and 25 and the outermost layer connection pads 22 and 23 are formed on the hole 17 to a film thickness of about 20 to 25 μm, and the corrosion resistance and electrical connection reliability are formed. Circuit board 27 of the present invention is obtained, and after applying a solder cream on the front and back of the circuit board 27 using a metal screen plate, the outermost layer connection pads 22 and 23 and the outermost land 24
A solder layer 26 having a film thickness of 70 μm is obtained on 25.
【0022】以上、実施例1,実施例2及び実施例3で
得られた回路基板27と従来技術例38において、貫通
穴8・30内壁への下地無電解銅めっき35と下地ニッ
ケルめっき9・10とのそれぞれのめっき液のしみ込み
量,次に隣り合った穴17−穴17と穴36−穴36と
の電食性、次いで、ホットオイル試験による接続信頼性
を評価し、その結果を表1に示す。As described above, in the circuit board 27 obtained in Examples 1, 2 and 3 and the prior art example 38, the base electroless copper plating 35 and the base nickel plating 9 10 and the electrolytic corrosion of the adjacent holes 17 to 17 and the holes 36 to 36, and the connection reliability by the hot oil test were evaluated. It is shown in FIG.
【0023】まためっき液しみ込み量は、貫通穴8・
30の内壁断面を光学顕微鏡で倍率400倍にて観察し
て測定した。電食性は、導通接続穴17・36導通接
続穴17・36間にDC50V印加し、85℃,85%
RHで1000時間放置した後の絶縁抵抗値(Ω)。
接続信頼性(ホットオイル試験)は、260℃オイル1
0秒浸漬,移行15秒,20℃流水中60秒浸漬,移行
15秒を1サイクルとし、800穴のシリーズ抵抗値を
測定し、抵抗値が初期値の10%以上上昇したサイクル
数を不合格とした。The amount of the plating solution soaked in the through hole 8
30 were measured by observing the cross section of the inner wall with an optical microscope at a magnification of 400 times. For electrolytic corrosion, apply DC 50 V between the conductive connection holes 17 and 36, 85 ° C., 85%
Insulation resistance value (Ω) after standing at RH for 1000 hours.
Connection reliability (hot oil test) is 260 ° C oil 1
One cycle of immersion for 0 seconds, 15 seconds for transition, 60 seconds for immersion for 60 seconds in running water at 20 ° C, and 15 seconds for transition, measure the series resistance value of 800 holes and reject the number of cycles in which the resistance value increased by 10% or more of the initial value And
【0024】評価結果を表1に記載する。The evaluation results are shown in Table 1.
【表1】 [Table 1]
【0025】表1から明らかなように、本発明によれ
ば、貫通穴8の内壁への下地ニッケルめっき液9・10
のしみ込み量がなくなり、高温多湿の高電界下における
耐電食性に優れ、さらに電気的な接続信頼性を向上させ
ることが実現可能な最適実施例2からなる回路基板27
を得ることができる。As apparent from Table 1, according to the present invention, the nickel plating solutions 9 and 10 are applied to the inner walls of the through holes 8.
The circuit board 27 according to the second embodiment which can eliminate the amount of penetration, has excellent corrosion resistance under a high temperature and high humidity and high electric field, and can further improve electrical connection reliability.
Can be obtained.
【0026】[0026]
【発明の効果】(1)本発明によれば、貫通穴8内壁に
下地ニッケルめっき膜9・10で被覆し、これに銅めっ
き液を施すことにより穴8内壁部への銅めっき液のしみ
込み量を防止でき、高温多湿な高電界下における耐電食
性が優れ、また経由導通接続穴17の内に変性エポキシ
樹脂からなる有機絶縁体13を充填・形成することによ
り金属めっき膜11・12の疲労によるバレルクラック
の防止とともに、電気的な接続信頼性に優れた回路基板
27が得られ、産業上寄与する効果は極めて大きい。(1) According to the present invention, the inner wall of the through-hole 8 is covered with the nickel plating films 9 and 10 and the copper plating solution is applied to the through-hole. It is possible to prevent the penetration of the metal plating films 11 and 12 by filling and forming an organic insulator 13 made of a modified epoxy resin in the via connection holes 17. In addition to preventing barrel cracks due to fatigue, a circuit board 27 having excellent electrical connection reliability is obtained, and the effect of contributing to industry is extremely large.
【図1】本発明の実施例を示す断面図。FIG. 1 is a sectional view showing an embodiment of the present invention.
【図2】本発明の製造工程を示す断面図。FIG. 2 is a cross-sectional view illustrating a manufacturing process of the present invention.
【図3】本発明の製造工程を示す断面図。FIG. 3 is a sectional view showing a manufacturing process of the present invention.
【図4】本発明の製造工程を示す断面図。FIG. 4 is a sectional view showing a manufacturing process of the present invention.
【図5】従来の製造工程を示す断面図。FIG. 5 is a sectional view showing a conventional manufacturing process.
【符号の説明】 1・2…内層銅箔 3・4…内層導体 5・6…有機絶縁
層 7…有機銅張り積層板 8…貫通穴 9・10…ニッケル
めっき膜(下地) 11・12…金属めっき膜(銅) 13…有機絶縁体 14・15…外層ランド 16…導通接続穴(ニッケ
ル) 17…経由導通接続穴(銅) 18・19…導通接続穴
ランド 20・21…めっき永久レジスト 22・23…最外層
接続パッド 24・25…最外層ランド 26…はんだ層 27…本発
明の回路基板 28…絶縁基板 29…銅箔 30…貫通穴 31…銅め
っき膜(下地) 32…導通接続穴(銅) 33…ソルダーレジスト 34…ニッケルめっき膜(無電解) 35…銅めっき液しみこみ量(銅イオンの移行) 36…経由導通接続穴(ニッケル) 37…導通接続穴
ランド 38…従来の技術に係る回路基板 整理番号p2461[Description of Signs] 1.2 Internal copper foil 3.4 Internal conductor 5.6 Organic insulating layer 7 Organic copper-clad laminate 8 Through hole 9.10 Nickel plating film (base) 11.12 Metal plated film (copper) 13 Organic insulator 14 15 Outer land 16 Conductive connection hole (nickel) 17 Via conductive connection hole (copper) 18 19 Conductive connection hole land 20 21 Plating permanent resist 22 · 23 · · · Outermost layer connection pad 24 · 25 · · · Outermost layer land 26 ... Solder layer 27 ... Circuit board of the present invention 28 ... Insulating substrate 29 ... Copper foil 30 ... Through hole 31 ... Copper plating film (base) 32 ... Conductive connection hole (Copper) 33 ... solder resist 34 ... nickel plating film (electroless) 35 ... coupling amount of copper plating solution (migration of copper ions) 36 ... through connection hole (nickel) 37 ... continuous connection hole land 38 ... conventional technology Such a circuit board, reference number p2461
───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5E317 AA11 AA24 BB12 BB15 CC32 CD27 GG09 GG16 5E343 AA02 AA07 AA15 BB24 BB44 CC62 DD33 GG20 5E346 AA06 AA54 CC32 CC37 FF12 FF15 GG15 GG17 GG22 HH13 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)
Claims (2)
(5)・(6),内層導体(3)・(4)とから構成さ
れる両面または多層有機銅張積層板(7)を用い、前記
内層導体(3)・(4)に電気的に接続された経由導通
接続穴(17),外層ランド(24)・(25)とをも
つ回路基板にあって、前記表裏全面及び導通接続穴(1
6)の下地金属膜厚は、0.6〜12μm範囲のニッケ
ルめっき膜(9)・(10)によって形成されており、
この下地ニッケルめっき膜(9)・(10)表裏全表面
を金属膜厚15〜35μm範囲の電解銅めっき膜(1
1)・(12)により被覆された経由導通接続穴(1
7)を形成して、この穴内に有機絶縁体(13)を形成
し、これにフォトエッチング法により、外層ランド(1
4)・(15),導通接続穴ランド(18)・(19)
とを形成後、無電解めっき永久レジスト(20)・(2
1)を形成して、実装部品固定に用いる外層接続パッド
(22)・(23)とを有することを特徴とする本発明
の回路基板(27)。1. A double-sided or multilayer organic copper-clad laminate comprising an inner layer copper foil (1) and (2), organic insulating layers (5) and (6), and inner layer conductors (3) and (4). 7) A circuit board having via connection connection holes (17) electrically connected to the inner layer conductors (3) and (4) and outer layer lands (24) and (25). The whole surface and the conductive connection hole (1
The base metal film thickness of 6) is formed by nickel plating films (9) and (10) in the range of 0.6 to 12 μm.
The entire surface of the underlying nickel plating films (9) and (10) is coated with an electrolytic copper plating film (1) having a metal film thickness of 15 to 35 μm.
1) Via via connection hole (1) covered by (12)
7) is formed, and an organic insulator (13) is formed in the hole.
4) · (15), land of conductive connection hole (18) · (19)
After forming the resist, the electroless plating permanent resist (20).
A circuit board (27) according to the present invention, comprising: (1) forming outer layer connection pads (22) and (23) used for fixing mounted components.
電界環境下のリフロー炉を通過させる場合に、前記導通
接続穴(17)の金属めっき膜(11)・(12)の電
気的な接続信頼性の劣化防止のため、この穴(17)内
に有機絶縁体(13)を形成することを特徴とする本発
明の回路基板(27)。2. The electric connection of the metal plating films (11) and (12) in the conductive connection hole (17) when passing through a reflow furnace under a high temperature, high humidity and high electric field environment. A circuit board (27) according to the present invention, wherein an organic insulator (13) is formed in the hole (17) to prevent deterioration of connection reliability.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19823298A JP2000031644A (en) | 1998-07-14 | 1998-07-14 | Circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19823298A JP2000031644A (en) | 1998-07-14 | 1998-07-14 | Circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000031644A true JP2000031644A (en) | 2000-01-28 |
Family
ID=16387714
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19823298A Pending JP2000031644A (en) | 1998-07-14 | 1998-07-14 | Circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000031644A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100428873C (en) * | 2003-11-28 | 2008-10-22 | 株式会社东芝 | Multilayer printed wiring board and method for manufacturing the multilayer printed wiring board |
-
1998
- 1998-07-14 JP JP19823298A patent/JP2000031644A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100428873C (en) * | 2003-11-28 | 2008-10-22 | 株式会社东芝 | Multilayer printed wiring board and method for manufacturing the multilayer printed wiring board |
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