JP2005079162A - Integrated circuit device performance simulation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable the performance simulation of an integrated circuit device to be improved in simulation accuracy, and to enable the integrated circuit device to be easily designed even when it is increased in scale and density. <P>SOLUTION: A variation of the layout of gate dimensions is computed on the basis of the variation of the gate dimensions dependent on or independent of the designed values of a gate length and a gate width (gate dimensions), the process variation of the gate dimensions correlated with a dopant fluctuation is computed, information on the variation in the gate dimensions is stored in a storage device, and the performance of the integrated circuit device is computed through a simulation using the above information on the variation in the gate dimensions. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a performance simulation method and a simulation method in consideration of variations in layout of an integrated circuit device.

  In recent years, as integrated circuit devices have become larger (higher functions), higher density, and lower power, design engineers can design integrated circuit devices under conditions where the margin of characteristics of semiconductor elements is extremely small. It is a situation that must be done. An integrated circuit device is usually designed in consideration of variations in performance of semiconductor elements. That is, it is designed such that the performance variation of the semiconductor element is predicted, and the integrated circuit device operates reliably and exhibits a predetermined performance within the variation range. Therefore, design engineers need to consider highly accurate model parameters and variations in process conditions when performing circuit simulation and estimating circuit performance in the initial development stage after creating a process specification draft. Become. The model parameter here is a parameter that determines the relationship between the voltage between the terminals of the semiconductor element and the current flowing between the terminals. For example, it is known that variation in threshold voltage of the MIS transistor occurs due to statistical fluctuations in the impurity concentration and shape of the channel region of the MIS transistor. It has become very important.

In the conventional technique, for a semiconductor element (MIS transistor), the maximum possible deviation value from the design value of the gate length and gate width is calculated using information on the structure and electrical characteristics of the MIS transistor, and the deviation value is calculated. Is used to simulate the performance of an integrated circuit device.
JP 2001-188816 A

  In the above conventional technique, the dimension value of an element of the semiconductor element and the performance of the electrical characteristics corresponding to the dimension value are calculated, and the dimension value (for example, the gate) that is the most severe with respect to the performance (for example, the delay value). By performing a simulation by selecting a length of 0.128 μm), a margin when variations occur is expected. As a result, in the above conventional technique, an excessive margin is provided for the structure and process conditions such as the gate dimension, and conversely, the margin in the design of the integrated circuit device becomes extremely small. In other words, with the increase in scale and density of integrated circuit devices, the performance simulation performance of integrated circuit devices decreases, and the design itself is becoming difficult in practice.

  The object of the present invention is to clearly understand the factors that cause variations in performance of integrated circuit devices, and to perform performance simulations of integrated circuit devices in consideration of variations, thereby improving performance simulation accuracy and facilitating design. There is to plan.

  The performance simulation method for an integrated circuit device according to the present invention is a method for storing information on variations in gate dimensions in a storage device and using the information on variations in gate dimensions to calculate the performance of the integrated circuit device by simulation. is there.

  With this method, the results of simulation, such as delay time and power consumption, can be obtained with high accuracy, not just a single point, even when integrated circuit devices are scaled up and densified. It is done. In addition, since an excessive margin is not provided for gate dimensions and process conditions unlike the conventional simulation method, it is sufficient for manufacturing an integrated circuit device even when the integrated circuit device is increased in scale and density. It becomes possible to design with a margin.

  Information on the variation in gate dimensions stored in the storage device includes random variations in gate dimensions and process variations in gate dimensions. The random variations include variations in gate dimensions depending on the design value of the gate dimensions, and gate dimensions. There are variations in gate dimensions that do not depend on

  Further, as process variations, there are variations in gate dimensions having a correlation with impurity fluctuations.

  There are two methods to determine the variation of the gate size depending on the design value: a method of calculating the gate size variation based on the correlation between the drain current and the gate width / gate length ratio, and the drain current and gate width / gate length ratio. And a method for calculating the variation in gate dimensions based on the correlation between the transconductance and the gate width / gate length ratio, and the variation in the gate dimensions of an existing integrated circuit device. There are a method for determining variations in gate dimensions, and a method for calculating variations in gate dimensions from the trend of variations in the gate dimensions of a plurality of existing process generations.

  Moreover, you may use the measured value of the dispersion | variation in a gate dimension.

  According to the performance simulation method of the integrated circuit device of the present invention, it is possible to improve the performance simulation accuracy and facilitate the design.

  FIG. 1 is a flowchart showing a performance simulation method for an integrated circuit device according to the first embodiment. The rough procedure of the simulation in the present embodiment will be described below along the flowchart of FIG.

  First, in step ST101, an environment in which the model formula and TCAD used for the simulation can be used is prepared. The model formula here refers to a relational expression between the structure of the semiconductor element and the electrical characteristics as described later, and various well-known model formulas can be used.

  Next, in step ST102, information regarding the gate length L and gate width L of each MIS transistor is extracted from the net list of the storage device (cell library). FIG. 2 is a diagram illustrating a part of a netlist stored in advance in a storage device. As shown in the figure, the netlist stores information on the gate length L, gate width W, etc. of each transistor MN, MP,. In this example, the gate lengths L of the MIS transistors MN and MP are both equal to 0.13 μm, and the gate widths W are different from 0.8 μm and 1.28 μm, respectively.

  Then, in step ST104, using the gate length and gate width extracted in step ST102, the model formula and TCAD adopted in step ST101, variations depending on the design values of the gate length L and the gate width W, and their variations Random variations in gate length and gate width, including variations that do not depend on design values, are obtained. A specific method for obtaining random variations in the gate length L and the gate width W will be described later.

  In step ST103, the design value of the concentration of the impurity (dopant) in each part of each MIS transistor is taken out from the storage device, and the gate length and gate width having correlation with the impurity fluctuation of each MIS transistor are obtained from this design value. The variation of is calculated. At this time, variation having correlation with impurity fluctuations can be calculated by a well-known TCAD simulation (Selete ENEXSS), particle simulation using molecular dynamics or Monte Carlo method, and the like.

  FIG. 3 is a diagram showing the channel doping amount dependency of threshold voltage variation obtained as a result of the TCAD simulation. As shown in the figure, the threshold voltage increases as the impurity concentration in the channel region increases.

  FIG. 4 is a diagram showing the gate length dependence of the threshold voltage variation obtained as a result of the TCAD simulation. FIG. 5 is a diagram showing the gate width dependence of the threshold voltage variation obtained as a result of the TCAD simulation. As can be seen from FIG. 3, the threshold voltage variation has a dependency on the channel doping amount. On the other hand, as can be seen from FIGS. 4 and 5, the threshold voltage variation also has a dependency on the gate length and the gate width. In other words, the impurity concentration, the gate length L, and the gate width W are correlated through the threshold voltage variation. Therefore, the variation in the gate length L and the gate width W can be obtained by obtaining the fluctuation of the impurity concentration.

  Next, in step ST105, the correlation between the variation in gate length and gate width having a correlation with the impurity fluctuation obtained in step ST103 and the impurity fluctuation obtained using the model formula and TCAD in step ST101 are calculated. The process variation (lot variation) of the gate length L and the gate width W is obtained from the variation that does not exist.

  Next, at step ST106, random variations in the gate length and gate width obtained at step ST104 and process variations at the gate length and gate width obtained at step ST105 are used, respectively, and layout variations (specifically, (Variation in gate length L and gate width W).

  Next, in step ST107, variations in electrical characteristics (delay time, etc.) of the semiconductor elements are obtained using the model formula and TCAD in step ST101.

  Next, in step ST108, the layout variation obtained in step ST106 (specifically, variation in gate length L and gate width W) and variation in electrical characteristics of the semiconductor element obtained in step ST107 are incorporated. A net list (variation net list) of the integrated circuit device is created and stored in the storage device.

  FIG. 6 is a diagram illustrating an example of the variation netlist. As shown in the figure, for the MIS transistors MN and MP, the variation in the gate length L is stored in the variation netlist as L # var and the variation in the gate width W is stored as W # var.

  Next, in step ST109, circuit simulation is performed using the circuit netlist (variation netlist) in consideration of the layout variation and electrical property variation created in step ST108.

  In step ST110, based on the result of the circuit simulation in step ST109, the performance of the integrated circuit device, such as delay time, power consumption, and chip area, is predicted.

  Here, since there are several types of procedures from step ST102 and step ST104 to step ST106 in the flowchart, various specific examples will be described. There are the following methods for obtaining variations in gate length and gate width.

-First method-
The first method uses a relational expression between the drain current Ids and the ratio of the gate width / gate length (W / L) to determine the gate width / gate length ratio (W / L). According to an analysis model such as BSIM (Berkeley Short-channel IGFET Model), the drain current Ids of the MIS transistor is expressed by the following equation (1).
Ids = (W / L) · A · (Vgs−Vth) ^B
∝ (W / L) (1)
Represented by Here, Vgs is a gate-source voltage, Vth is a threshold voltage, and A and B are coefficients.

  From the model equation (1), it can be seen that the drain current Ids and the gate width / gate length ratio W / L are in a proportional relationship. The variation in the drain current Ids can be obtained by measuring N semiconductor elements. From the viewpoint of statistical reliability, if more than 30 semiconductor elements are measured, highly accurate variation information can be obtained. Therefore, it is assumed that the drain current Ids can be obtained by the model equation (1). The values of the coefficients A and B, which are proportional constants, and the value of the threshold voltage Vth are extracted so that the error due to the alignment of each semiconductor element is minimized. In other words, random variations in the gate width / gate length ratio (W / L) can also be obtained by obtaining variations in the drain current Ids and the proportional coefficients A, B, and Vth in the equation (1). Therefore, this is used as a random variation component when obtaining the layout variation (specifically, variation in gate length L and gate width W) in step ST106.

-Second method-
The second method is a method for obtaining the variation in the gate width / gate length ratio (W / L) from the variation in the measured value of the current and the variation in the measured value of the mutual conductance. The ratio of change in drain current (dIds / dVg) to change in gate voltage is expressed by the following equation (2) as mutual conductance gm.
gm = dIds / dVg (2)
It is represented by

  Here, the threshold voltage Vth can be extracted using the following various methods. That is, the extrapolation method using the relationship between the mutual conductance and the gate voltage, the change method using the gate voltage at which the change in the mutual conductance is maximized as the threshold voltage, and the on-state drain current and gate voltage characteristics are affected. For example, a linear extrapolation method may be used in which the mobility is corrected so as to remove the gate voltage dependence and the threshold voltage is obtained from the characteristics. The gate width / gate length ratio (W / L) can be obtained by using the threshold voltage Vth thus obtained and the model equation (1). The relationship between the drain current Ids and the gate voltage Vg can be obtained by measuring N (for example, 30) semiconductor elements.

  Therefore, assuming that the variation of the threshold voltage Vth can be obtained using the equation (2), the coefficient in the equation (1) is set so that the error due to the fitting in the N semiconductor elements is minimized. Extract the values of A and B. That is, by using the model equations (1) and (2), the variation in the gate width / gate length ratio (W / L) can be obtained. Therefore, this is used as a random variation component when obtaining the layout variation (specifically, variation in gate length L and gate width W) in step ST106.

-Third method-
The third method is a method of providing variation information on the gate length L and gate width W of an existing integrated circuit device as variation in the gate width / gate length ratio (W / L) for simulation. In addition, the existing integrated circuit device may use an integrated circuit device configured with almost the same elements as the integrated circuit device whose circuit characteristics are to be predicted, or an integrated circuit device configured with completely different elements. Also good. Further, the number of existing integrated circuit devices may be any number, and the average of variations in gate length and gate width is obtained based on variation information of a plurality of existing integrated circuit devices, and the integrated circuit device to be predicted is calculated. It can also be given as variations in gate length and gate width. Therefore, this is used as a random variation component when obtaining the layout variation (specifically, variation in gate length L and gate width W) in step ST106.

-Fourth method-
The fourth method is a method for obtaining variations in gate length and gate width of an integrated circuit device to be predicted from trends in variations in gate length and gate width between existing process generations.

  FIG. 7 is a diagram illustrating variation in each process generation of the integrated circuit device to be predicted. In the figure, the horizontal axis indicates the change in the gate length L when the process generation changes, and the vertical axis indicates the variation in the gate length. As shown in the figure, there is a correlation (variation trend) represented by an approximate straight line or an approximate curve between the gate length of the process generation and the variation trend. Therefore, when the process generation (gate length) to which the integrated circuit device to be predicted belongs is given as a condition, variations in the gate length and gate width of the integrated circuit device can be obtained by prediction. Therefore, this is used as a random variation component when obtaining the layout variation (specifically, variation in gate length L and gate width W) in step ST106.

  According to the performance simulation method of the integrated circuit device of the present embodiment, the performance simulation of the integrated circuit device is performed in consideration of the variation in the gate length and the gate width. A shortage of margin can be compensated.

  FIGS. 8A and 8B are diagrams for explaining the difference between the conventional simulation method and the simulation method of the present embodiment. 8A and 8B show, as an example, dependency of delay time (or power consumption) on gate length (or gate width). As shown in FIG. 8A, in the case of the conventional simulation method, the simulation is performed assuming a certain value as the gate length (or gate width) which is a parameter necessary for performance simulation. The obtained delay time (or power consumption) is one value. On the other hand, as shown in FIG. 8B, in the simulation of the present embodiment, the simulation for many values in the variation range of the gate length (or gate width) can be performed several times. Therefore, with respect to performance such as delay time and power consumption obtained as a result of simulation, simulation results within a certain range can be obtained with high accuracy instead of one point.

  FIG. 9 is a diagram showing a variation state of the gate length as a histogram. As shown in the figure, the gate length varies with a certain frequency every 0.001 μm from the design value (for example, 0.122 μm) due to variations within the wafer and between processes. In the conventional integrated circuit device performance simulation method, a margin when variations occur by selecting a value (for example, gate length 0.128 μm) that is the most severe for the performance (for example, delay value) is performed. Will be expected. As a result, an excessive margin is provided for the structure and process conditions such as gate dimensions, and conversely, the margin in the design of the integrated circuit device is extremely small.

  On the other hand, when the integrated circuit device simulation method according to the present embodiment is used, for example, if it is determined in advance whether the expected yield is acceptable or not, there is a sufficient margin for manufacturing the integrated circuit device. Design can be performed.

(Second Embodiment)
FIG. 10 is a flowchart illustrating a performance simulation method for an integrated circuit device according to the second embodiment.

  As shown in the figure, in this embodiment, instead of the processing of step ST101 in the first embodiment, in step ST101 ′, the dimensions and impurity concentrations of the respective parts of the MIS transistor in the integrated circuit device are measured. Do. Then, in accordance with the result of this actual measurement, the processing from step ST102 onward as in the first embodiment is performed.

  Therefore, according to the present embodiment as well as the first embodiment, the performance simulation of the integrated circuit device can be performed with high accuracy, and the design having a sufficient margin for manufacturing the integrated circuit device should be performed. Is possible.

  The integrated circuit device simulation method of the present invention can be used to design an integrated circuit device having a large number of MIS transistors.

3 is a flowchart illustrating a performance simulation method for the integrated circuit device according to the first embodiment. It is a figure which illustrates a part of netlist previously stored in the memory | storage device used in the case of the performance simulation of the integrated circuit device which concerns on 1st Embodiment. It is a figure which shows the channel dope amount dependence of the threshold voltage variation calculated | required as a result of TCAD simulation. It is a figure which shows the gate length dependence of the threshold voltage variation calculated | required as a result of TCAD simulation. It is a figure which shows the gate width dependence of the threshold voltage variation calculated | required as a result of TCAD simulation. It is a figure which shows the example of the dispersion | distribution net list produced in the case of the performance simulation of 1st Embodiment. It is a figure which shows the dispersion | variation in each process generation of the integrated circuit device which is a prediction object. (A), (b) is a figure for demonstrating the difference of the simulation method of the past and this embodiment. It is a figure showing the variation state of gate length as a histogram. 6 is a flowchart illustrating a performance simulation method for an integrated circuit device according to a second embodiment.

Claims (10)

A method for simulating the performance of an integrated circuit device having a plurality of MIS transistors,
Storing in a storage device information relating to variations in gate dimensions of at least one of the gate length and gate width of the plurality of MIS transistors;
(B) extracting information on the variation in the gate size stored in the storage device and calculating the performance of the integrated circuit device by simulation using the variation in the gate size. Simulation method. The integrated circuit device performance simulation method according to claim 1,
Before step (a) above,
Calculating a random variation in the gate dimensions of the plurality of MIS transistors;
Calculating a process variation of the gate dimensions of the plurality of MIS transistors;
(E) storing the random variation of the gate size and the process variation calculated in the steps (c) and (d) in the storage device as the variation of the gate size,
In the step (a), the performance simulation method for an integrated circuit device, wherein the variation in the gate size stored in the step (e) is extracted from the storage device. The integrated circuit device performance simulation method according to claim 2,
In the step (c), the design value of the gate dimension previously stored in the storage device is taken out, the variation of the gate dimension depending on the design value of the gate dimension, and the gate dimension independent of the gate dimension. A performance simulation method for an integrated circuit device, wherein the variation in the above is calculated as a random variation in the gate dimensions. The integrated circuit device performance simulation method according to claim 2,
In the step (d), a performance simulation method for an integrated circuit device, wherein the variation in the gate dimension having a correlation with the impurity fluctuation is calculated as a process variation in the gate dimension. The integrated circuit device performance simulation method according to claim 3,
In the step (c), a performance simulation method for an integrated circuit device, wherein the variation in the gate size is calculated from the variation in the measured value of the drain current based on the correlation between the drain current and the gate width / gate length ratio. The integrated circuit device performance simulation method according to claim 3,
In the step (c), based on the correlation between the drain current and the gate width / gate length ratio, and the correlation between the mutual conductance and the gate width / gate length ratio, the variation in the measured drain current with respect to the gate voltage is varied. A method for simulating the performance of an integrated circuit device, which calculates the variation in gate dimensions from the above. The integrated circuit device performance simulation method according to claim 3,
In the step (c), the performance simulation method for an integrated circuit device, wherein the variation in the gate size of the existing integrated circuit device is defined as the variation in the gate size of the MIS transistor of the integrated circuit device to be simulated. The integrated circuit device performance simulation method according to claim 3,
In the step (c), the variation in the gate size of the plurality of existing process generations stored in the storage device in advance is extracted, and the simulation target is calculated from the trend of the variation in the gate size of the plurality of existing process generations. A method for simulating the performance of an integrated circuit device, wherein the variation in the gate size of the MIS transistor of the integrated circuit device is calculated. The integrated circuit device performance simulation method according to claim 1,
In the step (a), a performance simulation method for an integrated circuit device, wherein an actual measurement value of the variation in the gate size of the plurality of MIS transistors stored in the storage device is extracted from the storage device as the variation in the gate size. In the performance simulation method of the integrated circuit device according to any one of claims 1 to 9,
In the step (b), a performance simulation method for an integrated circuit device, wherein at least one of delay time, power consumption, and chip area of each circuit in the integrated circuit device is simulated as the performance of the integrated circuit device.

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