JP2005062601A - Photomask pattern verification and correction method - Google Patents

Abstract

In evaluation of a circuit design pattern having a plurality of design patterns, proximity effect correction can be reliably and easily performed while achieving desired miniaturization of an LSI.
A shape of each transfer pattern corresponding to each of a gate wiring design pattern 11A and a connection hole design pattern 12A overlapping with the gate wiring design pattern 11A, that is, a gate wiring pattern 11D and a connection hole pattern 12D. After the prediction, the connection hole pattern 12D is expanded to include a region (alignment margin) in which the connection hole pattern 12D may be formed, and then whether or not there is an overlapping region of the gate wiring pattern and the connection hole pattern figure. The positional relationship between the transfer patterns is evaluated by inspection.
[Selection] Figure 2

Description

  The present invention relates to a circuit design pattern verification and correction method having a plurality of design patterns overlapping each other.

  In recent years, along with the miniaturization of large-scale integrated circuit devices (hereinafter referred to as LSIs) using semiconductors, the lithography process, which is one of the LSI manufacturing processes, is affected by the optical proximity effect on the reticle. An error between the dimension of the design pattern provided as the mask pattern (that is, the design dimension) and the dimension of the transfer pattern obtained by transferring the design pattern onto the exposed material such as a resist (that is, the processing dimension) cannot be ignored. It is coming. On the other hand, in order to reduce an error between a design dimension and a processing dimension, proximity effect correction (Optical Proximity Correction: OPC), which is a technique for applying a minute deformation to a mask pattern, is used.

  Usually, a processing process such as lithography or dry etching has different processing conditions for each pattern layer such as a wiring, a gate, or a connection hole. For this reason, in OPC, data relating to the aforementioned error is acquired for each pattern layer, and a deformation to be added to the mask pattern, that is, an OPC specification is set. FIG. 6 shows an exposure apparatus for lithography, 21 is an illumination light source, 22 is a fly-eye lens, 23 is a variable illumination stop, 24 is a condenser lens, 25 is a reticle, 26 is a reduction projection lens, 3 is a semiconductor wafer, and 27 is It is a wafer stage.

  The proximity effect measurement pattern is formed from a pattern in which the space interval with respect to the line width is changed, and creates an OPC specification for correcting the shift amount of the line width from the design dimension. Then, in order to verify whether or not the OPC specification is set appropriately, a circuit design pattern is recently evaluated using a lithography shape simulation. With the progress of miniaturization in recent years, the separation between the connection hole and the wiring is reduced, and when these are not formed at appropriate positions, a short circuit failure occurs, which becomes a big problem. In particular, when transferring a fine circuit below the exposure wavelength, the design pattern causes a displacement due to the influence of the coma aberration of the projection lens, and the connection hole and the wiring are not formed at appropriate positions. .

  For example, as shown in FIG. 7A, in the circuit design pattern in which the connection hole design pattern 12A is arranged between the wiring design patterns 11A, the positional relationship between the transfer patterns corresponding to each design pattern is considered. In order to create and verify the OPC specification, the detection points 31 and 32 of the simulation image 11C of the transfer pattern corresponding to the wiring design pattern 11A and the pattern of the design pattern 12A are shown in FIG. 7B. Distances L2a and L2b between the pattern center 30 and the detection points 33 and 34 of the simulation image 12C of the transfer pattern corresponding to the distances L1a and L1b from the center 30 and the connection hole design pattern 12A shown in FIG. And measuring the positional relationship between the transfer patterns based on the difference between the distance L2a and the distance L2b. It is necessary to worthy. Also, because the detection position of the minimum separation amount between patterns differs within the shot due to the influence of coma aberration of the projection lens, the positional deviation between the wiring and the connection hole varies depending on the measurement position, and the alignment positional deviation amount varies depending on the inspection location difference. There is a problem that it is difficult to quantify the amount of displacement.

  Conventionally, the overlay accuracy measurement pattern is different from the circuit pattern in the product, and the effect of the projection lens coma aberration on the pattern difference is different, so the overlay accuracy measurement result and the actual circuit pattern are misaligned. There is a case. Conventionally, for such a problem, the overlay accuracy measurement value is corrected based on the yield result for the overlay deviation in the actual product pattern.

There exists patent document 1 as such a prior art.
JP 2003-43666 A

  A conventional circuit design pattern evaluation method, that is, a method of detecting a shift between a design pattern and a transfer pattern (simulation image) corresponding to the design pattern is for detecting the positional relationship between transfer patterns that overlap each other. It is difficult to set the detection points appropriately, and the number of the detection points becomes enormous, so that it is difficult to apply to actual LSI development.

  When misalignment occurs between the wiring pattern layer and the connection hole pattern layer, that is, when the relative formation positions of the wiring pattern layer and the connection hole pattern layer are shifted, the wiring transfer pattern and the connection hole transfer pattern Furthermore, there is a problem that the transfer patterns overlap and a short circuit occurs between the transfer patterns. Therefore, in view of the above, the present invention is to make it possible to reliably and easily perform proximity effect correction while making desired miniaturization of LSI in the evaluation of a circuit design pattern having a plurality of design patterns overlapping each other. Objective.

  In order to achieve the above object, a first circuit design pattern evaluation method according to the present invention includes: a wiring transfer pattern formed by transferring a wiring design pattern and a connection hole design pattern by a lithography technique; The step of predicting the shape of the transfer pattern of the connection hole, the step of isotropically expanding the shape of the transfer pattern of the connection hole, the shape of the transfer pattern of the wiring, and the shape of the transfer pattern of the connection hole are expanded. The circuit design pattern is evaluated by inspecting the presence or absence of a region overlapping with the formed shape.

  In particular, the shapes of the first transfer pattern and the second transfer pattern are predicted by incorporating the lens aberration of the exposure apparatus.

  In addition, a process for predicting the shape of each of the wiring transfer pattern and the connection hole transfer pattern obtained by transferring each of the wiring design pattern and the connection hole design pattern by lithography, and the wiring transfer pattern and the connection hole transfer The step of setting the standard for determining the positional relationship between patterns, the step of inspecting the positional relationship between the transfer pattern of the wiring and the connection hole, and the location that exceeds the standard of the positional relationship between the wiring and the transfer pattern of the connection hole To do. Further, the wiring design pattern, the overlay accuracy pattern arranged in the wiring design pattern, the connection hole design pattern, and the overlay accuracy measurement pattern arranged in the connection hole design pattern are transferred by lithography technology. A step of predicting the shape of each of the wiring transfer pattern and the connection hole transfer pattern, a step of evaluating the wiring design pattern and the transfer pattern of the connection hole and the positional deviation, and an overlay arranged in the wiring design pattern. A process for evaluating misalignment between the alignment accuracy measurement pattern and the overlay accuracy measurement pattern arranged in the connection hole design pattern, and calculating each misalignment amount and wiring design pattern and connection hole according to the misalignment amount The overlay accuracy result is corrected.

  According to the present invention, in the evaluation of a circuit design pattern having a plurality of design patterns overlapping each other, proximity effect correction can be performed reliably and easily while achieving desired miniaturization of the LSI. In addition, only transfer patterns having a positional relationship that is a problem in practice can be extracted, and human evaluation of the positional relationship can be performed very easily, so that defects in the design pattern or the OPC specification can be detected efficiently.

(First embodiment)
Hereinafter, a circuit design pattern evaluation method according to a first embodiment of the present invention will be described with reference to the drawings, taking as an example a design pattern of a circuit having a connection hole between a gate wiring and a substrate separated from the gate wiring. .

  FIG. 1 is a diagram illustrating each step of the circuit design pattern evaluation method according to the first embodiment. FIG. 2 is a diagram illustrating a pattern to which the circuit design pattern evaluation method according to the first embodiment is applied.

  First, as shown in FIG. 1A, a gate wiring design pattern 11A is created, and connection holes are formed according to the design rules so as not to be short-circuited between the patterns even if misalignment occurs with the gate wiring design pattern 11A. A design pattern 12A is created.

  Next, as shown in FIG. 1B, the gate wiring mask pattern 11B and the connection hole mask pattern 12B are in contrast to the gate wiring design pattern 11A and the connection hole design pattern 12A shown in FIG. , Modified based on the OPC specification.

  Next, the exposure condition is set for the mask pattern 11B for the gate wiring and the mask pattern 12B for the connection hole, and a lithography shape simulation is performed. As a result, as shown in FIG. And a simulation image 11C of the transfer pattern corresponding to the gate pattern and a simulation image 12C of the connection hole of the transfer pattern corresponding to the design pattern 12A of the connection hole. In the lithography shape simulation, process conditions of the gate wiring creation process and the connection hole creation process are used.

  Here, since the simulation images 11C and 12C are simulation data indicating only the outline of the transfer pattern, the simulation images 11C and 12C are converted into gate wiring figures and connection hole figures that can be figured on the computer. Then, as shown in FIG. 2 (a), there is a possibility that the connection hole is formed in the case where the alignment deviation and the dimensional variation occur in the simulation image 12C of the connection hole shown in FIG. 1 (c). A connection hole pattern 12D is enlarged so as to include a range of a certain region. Similarly, as shown in FIG. 2 (b), the simulation image 11C of the gate wiring shown in FIG. 1 (c) is also enlarged to include the range of the region where the gate wiring may be formed. A gate wiring pattern 11D is used. Then, a portion where the gate wiring pattern 11D and the connection hole pattern 12D overlap is checked. The presence of an overlapping portion indicates that the gate wiring and the connection hole come into contact with each other when the connection hole overlap shift or dimensional variation occurs. In this case, the pattern is changed by OPC so as not to overlap.

  In FIG. 2A, optimum process conditions are realized in each of the gate wiring creation process and the connection hole creation process. Further, OPC is appropriately performed on the gate wiring mask pattern 11B and the connection hole mask pattern 12B. As a result, the transfer pattern of the connection hole is well formed on the transfer pattern of the gate wiring. On the other hand, when the OPC is not properly performed on the mask pattern 11B of the gate wiring and the mask pattern 12B of the connection hole, for example, the gate wiring pattern shown in FIG. As in the case of the pattern shape) 11D and the connection hole pattern (that is, the connection hole transfer pattern shape) 12D, the amount of separation is reduced and a short circuit occurs between the connection hole and the gate wiring.

  Similarly, in the case of the gate wiring simulation image (that is, wiring transfer pattern shape) 11C and the connection hole pattern (that is, connection hole transfer pattern shape) 12E shown in FIG. For example, a short circuit occurs between the connection hole and the gate wiring.

  When there is lens aberration, the wiring pattern transfer position shifts in one direction. In this case, since the overlap between the connection hole and the gate wiring pattern is asymmetrical, the OPC is optimized when lens aberration is introduced by comparing the areas on both sides of the left and right connection holes.

  Therefore, it is possible to verify whether or not the circuit design pattern is defective by determining whether or not there is an overlapping area between the transfer pattern of the gate wiring and the transfer pattern of the connection hole. Thereby, it is possible to evaluate whether the OPC specification or the OPC processing algorithm applied to the mask pattern is appropriate. For example, when the OPC specification is inappropriate, the OPC specification is reviewed.

  By evaluating the overlapping area between the transfer pattern of the gate wiring and the transfer pattern of the connection hole in the entire shot area as in the present invention, the alignment margin between the gate wiring and the connection hole is ensured over the entire exposure region. Therefore, the occurrence of a short circuit between the gate wiring and the connection hole can be eliminated.

  As described above, according to the first embodiment, the shape of each transfer pattern corresponding to each of the gate wiring design pattern 11A and the connection hole design pattern 12A overlapping the gate wiring design pattern 11A (ie, the gate pattern). After predicting the wiring pattern 11D and the connection hole pattern 12D), after enlarging the connection hole pattern, it is checked whether there is a portion where the gate wiring pattern 11D and the enlarged connection hole pattern 12D overlap. To evaluate the positional relationship between the transfer patterns. For this reason, the number of setting items such as detection points is smaller than in the conventional case where a one-dimensional deviation between a design pattern and a transfer pattern corresponding to the design pattern is detected to evaluate the positional relationship between the transfer patterns. Since the time is greatly reduced, the calculation time required to evaluate the positional relationship between the transfer patterns is shortened, and the number of items that must be judged by a human is also reduced. Therefore, in the evaluation of a circuit design pattern having a plurality of design patterns overlapping each other, proximity effect correction can be performed reliably and easily while achieving desired miniaturization of the LSI. In addition, only transfer patterns having a positional relationship that is a problem in practice can be extracted, and human evaluation of the positional relationship can be performed very easily, so that defects such as design patterns or OPC specifications can be detected efficiently.

  Further, in the first embodiment, a lithography shape simulation is performed by setting exposure conditions for the mask pattern 11B of the gate wiring and the mask pattern 12B of the connection hole, thereby, as shown in FIG. A transfer pattern simulation image 11C corresponding to the gate wiring design pattern 11A and a transfer pattern simulation image 12C corresponding to the connection hole design pattern 12A were created. The gate wiring mask pattern 11B and the connection hole mask pattern 12B were created. In addition, aberrations of the projection lens are put into the lithography shape simulation. Then, the transfer pattern of the connection hole is uniformly enlarged by the alignment margin, and it is checked whether there is an area where the gate wiring pattern and the connection hole pattern overlap over the entire exposure area. Further, the area where the gate wiring and the connection hole overlap is integrated over the entire exposure area. Then, the design pattern or the OPC specification is changed so as to minimize the accumulated overlapping area.

  Further, according to the first embodiment, the design pattern of the gate wiring pattern shape and the connection hole pattern shape and the optimization of the OPC specifications are also taken into consideration in consideration of the displacement of the transfer pattern due to the coma aberration generated in the projection lens. It can be performed. As a result, after the diffusion is completed, the positional relationship can be evaluated with high accuracy and in a short time in consideration of misalignment over the entire exposure area without performing probe inspection. Can be performed efficiently. That is, the circuit design pattern can be verified with high accuracy and in a short time only by creating an enlarged shape of the connection hole transfer pattern shape in consideration of the influence of misalignment.

(Second Embodiment)
Hereinafter, a circuit design pattern evaluation method according to a second embodiment of the present invention will be described with reference to the drawings, taking as an example a circuit design pattern having connection holes arranged on wiring.

  FIG. 3 shows each step of the circuit design pattern evaluation method according to the second embodiment.

  First, as shown in FIG. 1B, exposure conditions are set for the mask pattern 11B of the gate wiring and the mask pattern 12B of the connection hole, and a lithography shape simulation is performed. As described above, the transfer pattern simulation image 11C corresponding to the gate wiring design pattern 11A shown in FIG. 1A and the transfer pattern simulation corresponding to the connection hole design pattern 12A shown in FIG. An image 12C is created. The simulation images 11C and 12C are converted into a gate wiring pattern 11D and a connection hole pattern 12D that can be graphically calculated on a computer. Then, a design rule check is performed on the entire surface of the shot to determine whether the interval between the pattern 11D and the pattern 12D exceeds a predetermined standard value. If it exceeds the standard, the OPC is corrected so as not to exceed the standard.

  Until now, since the design rule check for the design figures was performed, the positional relationship between the transfer patterns was not checked. Therefore, when the product is diffused, the OPC is not appropriate, so that there is a problem that the distance between the masks is increased and a short circuit occurs. A positional deviation between the transfer patterns can be detected by performing a design rule check between the design figures on the transfer pattern.

  In the present invention, the shapes of the transfer pattern of the gate wiring and the transfer pattern of the connection hole transferred by the lithography technique are predicted, and the distance between the gate wiring pattern and the connection hole is detected. ) To calculate a figure after the NOR processing of the transfer pattern of the wiring design pattern and the transfer pattern of the connection hole, and set a standard for determining the minimum dimension after the NOR processing. Then, by extracting a location where the minimum dimension of the figure after NOR processing exceeds the standard of the positional relationship between the transfer pattern of the wiring and the connection hole, a location where the alignment margin is insufficient between the wiring and the connection hole can be extracted. it can.

(Third embodiment)
Hereinafter, a circuit design pattern evaluation method according to a third embodiment of the present invention will be described with reference to the drawings, taking as an example a circuit design pattern having connection holes arranged on wiring.

  4 and 5 show the respective steps of the circuit design pattern evaluation method according to the third embodiment.

  The gate wiring design pattern 11A and the connection hole design pattern 12A shown in FIG. 4A, and the gate wiring overlay accuracy pattern 14A and the connection hole overlay accuracy pattern 15A shown in FIG. 4B are designed. It is formed in the mask pattern. A lithography shape simulation is performed by setting exposure conditions for these patterns.

  Accordingly, as shown in FIGS. 5A and 5B, a simulation image 11C of the transfer pattern corresponding to the gate wiring design pattern 11A shown in FIG. 4A is shown in FIG. 4A. Transfer pattern simulation image 12C corresponding to the connection hole design pattern 12A, transfer pattern simulation image 14B corresponding to the gate wiring overlay accuracy pattern 14A shown in FIG. 4B, and FIG. The simulation image 15B of the transfer pattern corresponding to the connection hole overlay accuracy pattern 14B is converted into a figure that can be figured on the computer. Then, the positional deviation amount between the simulation image 11C of the gate wiring and the simulation image 12C of the connection hole is evaluated, and the overlay deviation between the design pattern of the gate wiring and the design pattern of the connection hole is calculated from the simulation images 14B and 15B. . Then, the difference between the respective misregistration amounts is calculated, and the measurement result of the overlay accuracy measurement pattern between the transfer pattern of the gate wiring and the connection hole is corrected according to the misregistration amount difference calculated by the simulation.

  The shape of each of the transfer pattern of the first gate wiring and the transfer pattern of the second connection hole is predicted by performing simulation by taking into account the lens aberration of the exposure apparatus, so that the conventional overlay accuracy measurement result and the position of the transfer pattern Misalignment can be detected nondestructively.

  The photomask pattern verification and correction method of the present invention is useful for a method for evaluating a circuit design pattern having a plurality of design patterns overlapping each other.

(A)-(c) is a figure which shows each process of the evaluation method of the circuit design pattern which concerns on the 1st Embodiment of this invention. (A)-(c) is a figure which shows the pattern which applied the evaluation method of the circuit design pattern based on the 1st Embodiment of this invention (A)-(b) is a figure which shows each process of the evaluation method of the circuit design pattern based on the 2nd Embodiment of this invention. (A)-(b) is a figure which shows each process of the evaluation method of the circuit design pattern which concerns on the 3rd Embodiment of this invention. (A)-(b) is a figure which shows each process of the evaluation method of the circuit design pattern which concerns on the 3rd Embodiment of this invention. Configuration diagram of lithography exposure apparatus The figure which shows the process of the evaluation method of the conventional wiring and a connection hole transcription pattern

Explanation of symbols

3 Semiconductor wafer 11A Design pattern 11B Mask pattern 11C Simulation image 11D pattern 12A Design pattern 12B Mask pattern 12C Simulation image 12D Pattern 12E Pattern 14A Overlay accuracy measurement pattern 14B Simulation image 15A Overlay accuracy measurement pattern 15B Simulation image 21 Illumination light source 22 Fly Eye lens 23 Variable illumination stop 24 Condenser lens 25 Reticle 26 Reduction projection lens 27 Wafer stage 30 Pattern center 31 Detection point 32 Detection point 33 Detection point 34 Detection point

Claims (9)

Predicting the shape of each of the wiring transfer pattern and the connection hole transfer pattern formed by transferring the wiring design pattern and the connection hole design pattern by a lithography technique;
A step of isotropically expanding the shape of the transfer pattern of the connection hole;
A method for verifying and correcting a photomask pattern, comprising the step of inspecting for the presence or absence of a region where the shape of the transfer pattern of the wiring and the shape of the transfer pattern of the connection hole are enlarged. The step of isotropically expanding the shape of the transfer pattern of the connection hole is to expand the shape of the transfer pattern of the connection hole within a range equal to or less than the alignment margin between the transfer pattern of the wiring and the transfer pattern of the connection hole. The photomask pattern verification and correction method according to claim 1, further comprising a step. The position of the first transfer pattern and the second transfer pattern is detected by detecting the asymmetry of the area of the region where the shape of the first transfer pattern and the shape of the second transfer pattern overlap. The photomask pattern verification and correction method according to claim 1, further comprising a step of evaluating the relationship. The design pattern position of the connection hole is such that the area of the region where the shape of the first transfer pattern and the shape of the second transfer pattern overlap is integrated over the entire exposure region, and the integrated area is minimized. The photomask pattern verification and correction method according to claim 1, wherein: 2. The photomask pattern verification and correction method according to claim 1, wherein the shape of each of the first transfer pattern and the second transfer pattern is predicted by incorporating lens aberration of the exposure apparatus. A step of predicting the shape of each of the wiring transfer pattern and the connection hole transfer pattern formed by transferring the wiring design pattern and the connection hole design pattern by a lithography technique; A step of setting a standard for determining a positional relationship between transfer patterns of the connection holes, a step of inspecting a positional relationship of the transfer patterns of the wirings and the connection holes,
A method of verifying and correcting a photomask pattern, wherein a portion exceeding a standard of a positional relationship between the wiring and the transfer pattern of the connection hole is extracted. A step of predicting the shape of each of the wiring transfer pattern and the connection hole transfer pattern obtained by transferring the wiring design pattern and the connection hole design pattern by a lithography technique; and a wiring design pattern transfer pattern. And a step of calculating a minimum dimension of the figure after NOR processing of the transfer pattern of the connection hole, a step of setting a standard for determining a minimum dimension of the wiring and the connection hole after NOR processing, and a minimum dimension of the figure after the NOR processing 7. The photomask pattern verification and correction method according to claim 6, wherein a portion exceeding a standard of a positional relationship between the wiring and the transfer pattern of the connection hole is extracted. Each of the wiring design pattern, the overlay accuracy pattern arranged in the wiring design pattern, the connection hole design pattern, and the overlay accuracy measurement pattern arranged in the connection hole design pattern is transferred by lithography technology. A step of predicting the shapes of the transfer pattern of the wiring and the transfer pattern of the connection hole, a step of evaluating the positional deviation between the design pattern of the wiring and the transfer pattern of the connection hole, and the design pattern of the wiring A step of evaluating misalignment between the overlay accuracy measurement pattern disposed in the connection hole and the overlay accuracy measurement pattern disposed in the design pattern of the connection hole, and calculating each of the misalignment amounts, and calculating the misalignment amount Accordingly, the overlay design result of the wiring design pattern and the connection hole is corrected. Photo mask pattern verification and correction method to be. 8. The method for verifying and correcting a photomask pattern according to claim 7, wherein the shapes of the first transfer pattern and the second transfer pattern are predicted by taking into account lens aberration of the exposure apparatus.

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