JP2005045263A - Pin field effect transistor and method of forming the same - Google Patents

Abstract

A pin field effect transistor and a method of forming the same are provided.
The transistor includes a pin pattern including a multilayer pattern composed of a plurality of first semiconductor patterns and second semiconductor patterns arranged on a support substrate and stacked at least alternately. A gate electrode is disposed across the top of the pin pattern, and a gate insulating film is interposed between the pin pattern and the gate electrode. A pair of impurity diffusion layers are formed in the pin pattern on both sides of the gate electrode. The first and second semiconductor patterns have a lattice width that is wider in at least one direction than the lattice width of silicon. Accordingly, the charge mobility is increased in the channel region formed in the pin pattern, and the performance of the pin field effect transistor can be improved.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a method for forming the same, and more particularly to a pin field effect transistor and a method for forming the same.

  A field effect transistor (hereinafter referred to as a transistor) is a semiconductor element, that is, one of important single elements constituting a semiconductor integrated circuit. In general, the transistor includes a source region and a drain region that are spaced apart from each other on a semiconductor substrate, and a gate electrode that is formed above a channel region between the source region and the drain region.

  Due to the trend toward higher integration of semiconductor devices, the size of the transistor gradually decreases, and many problems have emerged. For example, the deterioration of punch-through characteristics between the source / drain regions is deepened due to the decrease in channel length. In addition, a control capability of the gate electrode with respect to the channel region may be reduced, and a leakage current may be generated. As a method for solving such a problem, a transistor having a double gate structure has been proposed. The double gate transistor refers to a transistor that controls the channel region by providing all gates on both sides (upper and lower surfaces or both side surfaces) of the channel region.

  On the other hand, Chenning Hu et al. Disclosed a FinFET transistor in Patent Document 1 under the title “Structure and manufacturing method of a FinFET transistor having a double gate channel extending vertically from a substrate”.

  The FinFET transistor includes a silicon source region and a silicon drain region that are spaced apart from each other on a semiconductor substrate. The silicon source region and the silicon drain region are connected by a silicon pin. The silicon pin, the silicon source region, and the silicon drain region protrude from the semiconductor substrate. A gate electrode is disposed across the silicon pin. That is, the gate electrode passes through both side walls of the silicon pin. Therefore, the channel region is composed of both side walls of the silicon pin, and the gate electrode can be controlled on both sides of the channel region. As a result, the control capability of the gate electrode with respect to the channel region is improved.

On the other hand, contrary to the trend toward higher integration of semiconductor devices, there is a growing demand for improved performance of the transistors. When the on-current of the transistor increases, the speed of the transistor may increase and the performance of the transistor may improve. The FinFET transistor can have a larger amount of on-current than a general planar transistor by using both side walls of the silicon pin as a channel region. However, when the size of the FinFET transistor is reduced, the amount of on-current is also reduced. Therefore, research on a method capable of improving the performance of the FinFET transistor even when the physical size of the FinFET transistor is reduced is being actively pursued.
US Pat. No. 6,413,802

  The problem to be solved by the present invention is to provide a pin field effect transistor capable of improving the performance of the transistor by increasing the mobility of the charge.

  Another problem to be solved by the present invention is to provide a method for forming a pin field effect transistor that can increase the mobility of charges and improve the performance of the transistor.

  In order to solve the above technical problem, a pin field effect transistor is provided. According to an embodiment of the present invention, the pin field effect transistor includes a pin pattern protruding from the semiconductor substrate. The pin pattern may include stacked first and second semiconductor patterns. The first and second semiconductor patterns may have a lattice width that is larger than the lattice width of the substrate material in at least one direction.

  In one embodiment, a plurality of first and second semiconductor patterns may be alternately stacked to increase the height of the pin. One of the first and second semiconductor patterns can reduce stress caused by the other. In addition, along the length direction of the pin field effect transistor channel, the lattice width of the first and second semiconductor patterns may be larger than the lattice width of the substrate. In addition, one of the first and second semiconductor patterns may be formed of expanded silicon, and the other may be formed of silicon germanium. The silicon germanium pattern may reduce the stress of the expanded silicon pattern.

  In one embodiment, the transistor may further include a buffer semiconductor layer on the semiconductor substrate and a relaxed semiconductor device on the buffer semiconductor layer. The substrate may be formed of silicon, the buffer semiconductor layer may be formed of grade silicon germanium, and the relaxed semiconductor layer may be formed of silicon germanium. In addition, the germanium concentration of the buffer semiconductor layer can be gradually increased as it increases from the lower surface to the upper surface. The germanium concentration of the relaxed semiconductor layer is uniform and may be the same as the maximum germanium concentration of the buffer semiconductor layer. In addition, one of the first and second semiconductor patterns may be formed of the same material as the relaxed semiconductor layer. The pin pattern may further include a third semiconductor pattern formed of the same material as the relaxed semiconductor layer.

  In one embodiment, the transistor may further include an element isolation film disposed on the semiconductor substrate and surrounding a lower portion of the pin pattern, and a gate electrode partially disposed on the element isolation film. Alternatively, the transistor may further include a hard mask film on the pin pattern.

  According to another embodiment of the present invention, the pin field effect transistor includes a semiconductor substrate having a first lattice width along the first and second directions, and a second lattice width along the first and / or second direction. And a second semiconductor pattern having a third lattice width along the first and / or second direction. The second and third lattice widths are larger than the first lattice width, and the first and second semiconductor patterns are sequentially stacked to form a pin pattern protruding from the substrate.

  In order to solve the other technical problems described above, a method for forming a pin field effect transistor is provided. According to an embodiment of the present invention, the method may include forming a pin pattern protruding from the semiconductor substrate. The pin pattern may include stacked first and second semiconductor patterns. The first and second semiconductor patterns may have a lattice width that is larger than the lattice width of the substrate material in at least one direction.

  In one embodiment, the step of forming the pin pattern may form a plurality of first and second semiconductor patterns stacked alternately so as to increase the height of the pin pattern. One of the first and second semiconductor patterns may reduce stress caused by the other one. In addition, along the length direction of the pin field effect transistor channel, the lattice width of the first and second semiconductor patterns may be larger than the lattice width of the substrate. In addition, one of the first and second semiconductor patterns may be formed of expanded silicon and the other may be formed of silicon germanium. The silicon germanium pattern can reduce stress of the expanded silicon pattern.

  In one embodiment, the method may further include forming a buffer semiconductor layer on the semiconductor substrate and forming a relaxed semiconductor layer on the buffer semiconductor layer. The semiconductor substrate can be formed of silicon. The buffer semiconductor layer may be formed of grade silicon germanium, and the relaxed semiconductor layer may be formed of silicon germanium. The germanium concentration of the buffer semiconductor layer can be gradually increased as the buffer semiconductor layer increases from the lower surface to the upper surface. The germanium concentration of the relaxed semiconductor layer is uniform and may be the same as the maximum germanium concentration of the buffer semiconductor layer. In addition, one of the first and second semiconductor patterns may be formed of the same material as the relaxed semiconductor layer. The pin pattern may further include a third semiconductor pattern formed of the same material as the relaxed semiconductor layer.

  In one embodiment, the method includes forming an element isolation film disposed on the semiconductor substrate and surrounding a lower portion of the pin pattern, and forming a gate electrode partially disposed on the element isolation film. Further comprising the step of: The method may further include forming a hard mask film on the pin pattern.

  According to another embodiment of the present invention, a method of forming a pin field effect transistor comprises preparing a semiconductor substrate having a first lattice width along a first and / or second direction, and Or forming a first semiconductor pattern having a second lattice width along the second direction; and forming a second semiconductor pattern having a third lattice width along the first and / or second direction. Can be included. The second and third lattice widths are larger than the first lattice width, and the first and second semiconductor patterns are sequentially stacked to form a pin pattern protruding from the substrate.

  The pin field effect transistor according to the present invention has a pin pattern composed of a plurality of first semiconductor patterns and second semiconductor patterns that are alternately stacked. At this time, the first and second semiconductor patterns have a larger lattice width in at least one direction than the silicon crystal. For example, the first and second semiconductor patterns are formed of an expanded silicon pattern and a silicon-germanium pattern, respectively. Accordingly, the charge mobility is increased in the channel region formed in the pin pattern, and the performance of the pin field effect transistor can be improved. In addition, the silicon-germanium pattern serves to relieve the stress of the expanded silicon pattern, thereby sufficiently increasing the height of the pin pattern.

  In addition, the expanded silicon pattern increases electron mobility, and the silicon-germanium pattern prevents hole mobility from decreasing. Therefore, the field effect transistor having the pin pattern is suitable for a CMOS device having both NMOS and PMOS transistors.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein, and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosed content will be thorough and complete, and will fully convey the spirit of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Also, when a layer is referred to as being “on” another layer or substrate, it can be formed directly on the other layer or substrate, or intervening a third layer therebetween It is also possible. Portions denoted by the same reference numerals throughout the specification indicate the same components.

  FIG. 1 is a perspective view showing a pin field effect transistor according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1, and FIG. It is sectional drawing cut | disconnected along II '.

  Referring to FIGS. 1, 2, and 3, the buried insulating film 106 is disposed on the support substrate 105, and the pin pattern 118 and the hard mask pattern 116 a are sequentially stacked on the buried insulating film 106.

  The support substrate 105 may include a semiconductor substrate 100, a buffer semiconductor layer 102 and a relaxed semiconductor layer 104 a sequentially stacked on the semiconductor substrate 100. The semiconductor substrate 100 is preferably made of a silicon substrate.

  The buffer semiconductor layer 102 includes a semiconductor layer 102 that can relieve stress (eg, tension stress) between the semiconductor substrate 100 and the relaxed semiconductor layer 104a. The relaxed semiconductor layer 104a is made of a semiconductor layer without stress. For example, the buffer semiconductor layer 102 may be a grade silicon-germanium layer, and the relaxed semiconductor layer 104a may be a relaxed silicon-germanium layer.

  As the grade silicon-germanium layer increases from the lower surface to the upper surface, the germanium concentration gradually increases, and the relaxed silicon-germanium layer has a uniform germanium concentration throughout the film. The germanium concentration of the relaxed silicon-germanium layer is preferably the same as the portion of the grade silicon-germanium layer where the germanium concentration is maximum, that is, the uppermost portion thereof.

  Germanium atoms are larger in diameter than silicon atoms. For this reason, the lattice width of the film in which silicon atoms and germanium atoms coexist is wider than that of a general silicon layer composed of only silicon atoms. As a result, the relaxed semiconductor layer 104a made of the relaxed silicon-germanium layer has a larger lattice width than the semiconductor substrate 100 made of the silicon substrate.

  On the other hand, the buffer width of the buffer semiconductor layer 102 made of the grade silicon-germanium layer gradually increases as the height increases from the lower surface to the upper surface. This is because the germanium concentration in the buffer semiconductor layer 102 gradually increases. Accordingly, the buffer semiconductor layer 102 serves as a buffer that relieves stress due to a difference in lattice width between the semiconductor substrate 100 and the relaxed semiconductor layer 104a.

  The buried insulating film 106 may be a silicon oxide film, a germanium oxide film, or a film in which a silicon oxide film and a germanium oxide film coexist as an insulating film.

  The pin pattern 118 includes a multilayer pattern 114a composed of a plurality of first semiconductor patterns 110a and second semiconductor patterns 112a that are alternately stacked. At this time, the first and second semiconductor patterns 110a and 112a have a lattice width wider in at least one direction than the lattice width of a general silicon crystal. A third semiconductor pattern 104c is preferably disposed between the multilayer pattern 114a and the buried insulating film 106. The third semiconductor pattern 104c has sidewalls aligned with the sidewalls of the multilayer pattern 114a. The third semiconductor pattern 104c may be made of the same material having the same lattice width as the relaxed semiconductor layer 104a. The pin pattern 118 may include the third semiconductor pattern 104c and the multilayer pattern 114a that are stacked.

  One of the first and second semiconductor patterns 110a and 112a may be formed of the same material having the same lattice width as the relaxed semiconductor layer 104a (or the third semiconductor pattern 104c).

  One of the first semiconductor pattern 110a and the second semiconductor pattern 112a may be an expanded silicon pattern, and the other may be a silicon-germanium pattern.

  The expanded silicon pattern is expanded such that the horizontal lattice width of the expanded silicon pattern is equal to the horizontal width of the third semiconductor pattern 104c or the relaxed semiconductor layer 104a. The silicon-germanium pattern in the pin pattern 118 has the same germanium concentration as the relaxed semiconductor layer 104a or the third semiconductor pattern 104c. That is, it is preferable that the silicon-germanium pattern in the pin pattern 118 is free from stress and has the same lattice width as the relaxed semiconductor layer 104a or the third semiconductor pattern 104c.

  As a result, the expanded silicon pattern in the pin pattern 118 has a horizontally expanded lattice width, and the silicon-germanium pattern and the relaxed semiconductor pattern 104c in the pin pattern 118 are the expanded silicon pattern. Serves as a buffer to relieve stress.

  The uppermost layer and the lowermost layer of the multilayer pattern 114a may be formed of the expanded silicon pattern. In contrast, the uppermost layer and the lowermost layer of the multilayer pattern 114a may be formed of the silicon-germanium pattern. Further, one of the uppermost layer and the lowermost layer of the multilayer pattern 114a may be formed of the expanded silicon pattern, and the other layer may be formed of the silicon-germanium pattern.

  The hard mask pattern 116a may be formed of a silicon nitride film, and may further include a buffer oxide film interposed between the silicon nitride film and the pin pattern 118.

  A gate electrode 122 is disposed across the pin pattern 118 and the hard mask pattern 116a. A gate insulating layer 120 is interposed between at least the pin pattern 118 and the gate electrode 122. The gate electrode 122 may be formed of a conductive film, for example, doped polysilicon, polycide, or a metal film. The gate insulating layer 120 is disposed on at least the exposed surface of the pin pattern 118. Due to the hard mask pattern 116a, both side walls of the pin pattern 118 below the gate electrode 122 correspond to a channel region.

  Unlike this, the hard mask pattern 116a can be omitted. In this case, both side walls and the upper surface of the pin pattern 118 located under the gate electrode 122 correspond to the channel region. At this time, the gate insulating layer 120 is also interposed between the upper surface of the pin pattern 118 and the gate electrode 122.

  The wide lattice width of the patterns 104c, 110a, and 112a in the pin pattern 118 is preferably parallel to the length direction of the channel region.

  A pair of impurity diffusion layers 125 are disposed in the pin pattern 118 on both sides of the gate electrode 122. The impurity diffusion layers 125 correspond to source / drain regions.

  In the pin field effect transistor having the above-described structure, the pin pattern 118 includes patterns 104c, 110a, and 112a having a wider lattice width than a general silicon crystal. That is, the pin pattern 118 has a structure in which silicon-germanium patterns and expanded silicon patterns are alternately stacked. This increases the mobility of carriers in the channel region and increases the on-current of the pin field effect transistor. As a result, the performance of the pin field effect transistor is improved. The mobility of carriers in the channel region of the pin pattern 118 will be described with reference to the energy band diagram of FIG.

  FIG. 4 is a schematic energy band diagram taken along the line III-III ′ of FIG.

  Referring to FIGS. 2 and 4, the energy band diagram of FIG. 4 illustrates a case where the first semiconductor pattern 110a is formed of an expanded silicon pattern and the second semiconductor pattern 112a is formed of a silicon-germanium pattern.

  A dotted line 200 indicates a Fermi level, and dotted lines 210 and 220 correspond to a valence band and a conduction band of each general single crystal silicon layer. Accordingly, the dotted lines 210 and 220 are referred to as a standard valence band and a standard conduction band, respectively. The solid lines 310 and 320 correspond to the first valence band 310 and the first conduction band 320 of the first semiconductor pattern 110a, respectively, and the solid lines 410 and 420 respectively represent the second valence band 410 and the first conduction band 320 of the second semiconductor pattern 112a. It corresponds to two conduction bands.

  As shown in FIG. 4, due to the wide lattice width of the expanded silicon pattern, the first conduction band 320 has a lower energy level than the reference conduction band 220. Accordingly, the probability that electrons are present in the first conduction band 320 is higher than that of the reference conduction band 220. Regardless of the germanium concentration of the second semiconductor pattern 112a, the second conduction band 420 has almost the same energy level as the reference conduction band 220. Accordingly, the probability that electrons exist in the second conduction band 420 is similar to the probability that electrons exist in the reference conduction band 220. As a result, there are more electrons in the channel region formed in the pin pattern 118 than in the channel region formed in the conventional silicon pin. Accordingly, the mobility of electrons in the channel region formed in the pin pattern 118 is increased as compared with the conventional one.

  Meanwhile, the first valence band 310 has a lower energy level than the reference valence band 210. That is, the probability that holes exist in the first valence band 310 is lower than that of the reference valence band 210. On the other hand, the second valence band 410 has a higher energy level than the reference valence band 210. That is, the probability that holes exist in the second valence band 310 is higher than that of the reference valence band 210. As a result, even if the first valence band 310 is lower than the reference valence band 210, the second valence band 410 is higher than the reference valence band 210. That is, even if a PMOS channel region is formed in the pin pattern 118, hole mobility does not decrease. Therefore, the pin field effect transistor having the pin pattern 118 is very suitable for a CMOS device in which NMOS and PMOS transistors are realized simultaneously.

  As a result, the pin pattern 118 includes an expanded silicon pattern and a silicon-germanium pattern that are alternately stacked. The expanded silicon pattern increases electron mobility. The silicon-germanium pattern may increase the height of the pin pattern 118 by relieving the stress of the expanded silicon pattern. In addition, the silicon-germanium pattern increases hole mobility. Therefore, the amount of on-current of the field effect transistor having the pin pattern 118 is increased, and the performance thereof is improved.

  5 to 7 are process cross-sectional views taken along the line II ′ of FIG. 2 for explaining a method of forming a pin field effect transistor according to an embodiment of the present invention.

  5 and 6, a buffer semiconductor layer (102) is formed on the semiconductor substrate 100, and a relaxed semiconductor layer (104, relaxed semiconductor layer) is formed on the buffer semiconductor layer 102. . The semiconductor substrate 100, the buffer semiconductor layer 102, and the relaxed semiconductor layer 104 may constitute a support substrate 105.

  The semiconductor substrate 100 is preferably a silicon substrate. The relaxed semiconductor layer 104 is formed of a semiconductor layer free from stress and having a lattice width wider than that of a general silicon crystal. For example, the relaxed semiconductor layer 104 is preferably formed of a relaxed silicon-germanium layer. The buffer semiconductor layer 102 is formed of a semiconductor layer that can relieve stress caused by a difference in lattice width between the semiconductor substrate 100 and the relaxed semiconductor layer 104. For example, the buffer semiconductor layer 102 is preferably formed of a grade silicon-germanium layer.

  The grade silicon-germanium layer is formed by an epitaxial growth process in which the amount of germanium source gas is gradually increased from the surface of the semiconductor substrate 100. Therefore, the higher the grade silicon-germanium layer is from the surface of the semiconductor substrate 100, the higher the germanium concentration. That is, as the grade silicon-germanium layer increases from the lower surface to the upper surface, the lattice width gradually increases.

  The relaxed silicon-germanium layer is formed on the buffer semiconductor layer 102 by an epitaxial growth process that supplies a constant amount of germanium source gas. Thus, the relaxed silicon-germanium layer has a uniform germanium concentration throughout the film. At this time, it is preferable that the germanium concentration of the relaxed silicon-germanium layer is the same as the portion where the germanium concentration of the grade silicon-germanium layer is maximum (that is, the uppermost portion of the film).

  As a result, the buffer semiconductor layer 102 absorbs stress between the relaxed semiconductor layer 104 and the semiconductor substrate 100, and the relaxed semiconductor layer 104 becomes free of stress.

  Subsequently, a predetermined element ion is implanted into the support substrate 105 to form a buried insulating film 106 in the relaxed semiconductor layer 104. At this time, the upper surface of the buried insulating film 106 is formed to be separated from the upper surface of the relaxed semiconductor layer 104 by a predetermined depth. As a result, the relaxed semiconductor layer 104 is formed of the first relaxed semiconductor layer 104a, the buried insulating film 106, and the second relaxed semiconductor layer 104b, which are sequentially stacked.

  The predetermined element ion is preferably an oxygen ion. Therefore, the buried insulating film 106 can be formed as a silicon oxide film, a germanium oxide film, or an insulating film in which a silicon oxide film and a germanium oxide film coexist.

  Subsequently, a multilayer film 114 including a plurality of first semiconductor layers 110 and second semiconductor layers 112 stacked alternately on the second relaxed semiconductor layer 104b is formed. One of the first semiconductor layer 110 and the second semiconductor layer 112 may be formed of an expanded silicon film using an epitaxial growth process, and the other may be formed of a silicon-germanium film using an epitaxial growth process. desirable.

  As a specific example of the method of forming the multilayer film 114, the first semiconductor layer 110 is formed on the second relaxed semiconductor layer 104b by an epitaxial growth process using a silicon source gas. Accordingly, the lattice width in the horizontal direction of the first semiconductor layer 110 is a single crystal silicon film having the same lattice width as the lattice width in the horizontal direction of the second relaxed semiconductor layer 104b, that is, the expanded. It is formed of a silicon film. The expanded silicon film has a lattice width in a direction parallel to the surface of the support substrate 105 due to the lattice width of the second relaxed semiconductor layer 104b. Therefore, the expanded silicon film has a larger lattice width than that of a general silicon crystal.

  After the first semiconductor layer 110 is formed with a predetermined thickness, the second semiconductor layer 112 is formed on the first semiconductor layer 110 by an epitaxial process using a silicon source gas and a germanium source gas. That is, the second semiconductor layer 112 is formed of a silicon-germanium layer. At this time, the second semiconductor layer 112 is preferably formed to have the same germanium concentration as the second relaxed semiconductor layer 104b. Accordingly, the second semiconductor layer 112 is formed to have the same lattice width as the second relaxed semiconductor layer 104b. The horizontal width of the second semiconductor layer 112 is the same as the horizontal width of the first semiconductor layer 110.

  As a result, the second relaxed semiconductor layer 104b and the second semiconductor layer 112 having no stress absorb stress due to the expanded lattice width of the first semiconductor layer 110 interposed therebetween. In other words, the second semiconductor layer 112 of the multilayer film 114 serves to absorb the stress of the adjacent first semiconductor layer 110.

  In contrast, the first semiconductor layer 110 may be formed of a silicon-germanium layer using an epitaxial growth process, and the second semiconductor layer 112 may be formed of an expanded silicon layer using an epitaxial growth process.

  The uppermost layer and the lowermost layer of the multilayer film 114 may be formed of the first semiconductor layer 110. In contrast, the uppermost layer and the lowermost layer of the multilayer film 114 may be formed of the second semiconductor layer 110. Further, one of the uppermost layer and the lowermost layer of the multilayer film 114 may be formed of the first semiconductor layer 110, and the other may be formed of the second semiconductor layer 112.

  A hard mask film 116 is formed on the multilayer film 114. The hard mask film 116 may be formed of an insulating film, for example, a silicon nitride film, which has an etching selectivity with respect to the multilayer film 114 and can also serve as an antireflection film. Of course, the hard mask film 116 may further include a buffer oxide film formed between the silicon nitride film and the multilayer film 114.

  Referring to FIG. 7, the hard mask layer 116, the multilayer layer 114, and the second relaxed semiconductor layer 104b are sequentially patterned to sequentially stack the second relaxed semiconductor pattern 104c, the multilayer pattern 114a, and the hard layer. A mask pattern 116a is formed. The multilayer pattern 114a includes a plurality of first semiconductor patterns 110a and second semiconductor patterns 112a that are alternately stacked. When one of the first and second semiconductor layers 110 and 112 is formed of the expanded silicon film and the other is formed of the silicon-germanium film, the first and second semiconductor patterns 110a are formed. , 112a is formed of an expanded silicon pattern, and the other is formed of a silicon-germanium pattern. The second relaxed semiconductor pattern 104 c and the multilayer pattern 114 a constitute a pin pattern 118. The pin pattern 118 is formed on the buried insulating film 106. Therefore, the pin pattern 118 can be separated from other adjacent pin patterns (not shown).

  Subsequently, a gate insulating layer 120 is formed on at least the exposed surface of the pin pattern 118. The gate insulating layer 120 may be formed on the exposed surface of the pin pattern 118 by performing a thermal oxidation process on the support substrate 105 having the pin pattern 118. Accordingly, the gate insulating film 120 can be formed of an insulating film in which a thermal silicon oxide film and a thermal germanium oxide film coexist.

  Meanwhile, the gate insulating layer 120 can be formed by other methods. First, a surface semiconductor layer is formed on the entire surface of the support substrate 105 having the pin pattern 118. The surface semiconductor layer can be formed by a chemical vapor deposition method or an epitaxial growth process. The surface semiconductor layer can be formed of a silicon film. When the surface semiconductor layer is formed by an epitaxial growth process, the surface semiconductor layer can be formed only on the exposed surface of the pin pattern 118. Subsequently, the gate semiconductor layer 120 is formed by thermally oxidizing the surface semiconductor layer.

  Subsequently, the gate electrode 122 shown in FIGS. 1 and 2 is formed. The gate electrode 122 is formed on the gate insulating layer 120 so as to cross the pin pattern 118 and the hard mask pattern 116a. When the gate electrode 122 is formed, the gate insulating layer 120 can also be patterned.

  Subsequently, impurity ions are implanted using the gate electrode 122 as a mask to form a pair of impurity diffusion layers 125 shown in FIGS. 1 and 3 in the pin pattern 118 on both sides of the gate electrode 122. The impurity diffusion layers 125 correspond to source / drain regions, respectively.

(Second Embodiment)
In another embodiment of the present invention, a pin field effect transistor to which an element isolation method of a form different from the above-described one embodiment is applied is shown.

  8 is a perspective view showing a pin field effect transistor according to another embodiment of the present invention, FIG. 9 is a sectional view taken along line IV-IV ′ of FIG. 8, and FIG. It is sectional drawing cut | disconnected along -V '.

  Referring to FIGS. 8, 9, and 10, a pin pattern 218 and a hard mask pattern 216 a are sequentially stacked on the support substrate 205. The hard mask pattern 216 a has sidewalls aligned with the sidewalls of the pin pattern 218.

  The support substrate 205 may include a semiconductor substrate 200, a buffer semiconductor layer 202 and a relaxed semiconductor layer 204 that are sequentially stacked on the semiconductor substrate 200. Preferably, the semiconductor substrate 100 is a silicon substrate, the buffer semiconductor layer 202 is a grade silicon-germanium layer, and the relaxed semiconductor layer 204 is a relaxed silicon-germanium layer. The grade silicon-germanium layer and the relaxed silicon-germanium layer may be made of the same material as the above-described embodiment and have the same properties. That is, in the grade silicon-germanium layer, the lattice width gradually increases as the germanium concentration gradually increases and increases from the lower surface to the upper surface. The relaxed silicon-germanium layer has a uniform germanium concentration throughout the film and a uniform lattice width throughout the film. The germanium concentration of the relaxed silicon-germanium layer is preferably the same as the portion of the grade silicon-germanium layer having the maximum germanium concentration. Therefore, the relaxed silicon-germanium layer has the same lattice width as the portion of the grade silicon-germanium layer where the germanium concentration is maximum. The buffer semiconductor layer 202 serves to buffer stress due to a difference in lattice width between the semiconductor substrate 200 and the relaxed semiconductor layer 204.

  The pin pattern 218 includes a multilayer pattern including a plurality of first semiconductor patterns 210a and second semiconductor patterns 212a that are alternately stacked. At this time, the first semiconductor pattern 210a and the second semiconductor pattern 212a have a lattice width wider in at least one direction than the lattice width of a general silicon crystal.

  One of the first and second semiconductor patterns 210a and 212a may be formed of the same material having the same lattice width as the relaxed semiconductor layer 204.

  Preferably, one of the first semiconductor pattern 210a and the second semiconductor pattern 212a is an expanded silicon pattern, and the other is a silicon-germanium pattern.

  The expanded silicon pattern and the silicon-germanium pattern may have the same structure and characteristics as the above-described embodiment. That is, a horizontal lattice width of the expanded silicon pattern is expanded to have the same lattice width as a horizontal lattice width of the relaxed semiconductor layer 204, and the silicon-germanium pattern is The relaxed semiconductor layer 204 has the same germanium concentration. As a result, the silicon-germanium pattern in the pin pattern 218 is free from stress and has the same lattice width as the relaxed semiconductor layer 204. The silicon-germanium pattern in the pin pattern 218 serves as a buffer for absorbing the stress of the expanded silicon pattern.

  The pin pattern 218 may have the same uppermost layer and lowermost layer as the multilayer pattern 114a of FIG.

  The hard mask pattern 216a may be formed of a silicon nitride film, and may further include a buffer oxide film interposed between the silicon nitride film and the pin pattern 218.

  A gate electrode 225 is disposed across the pin pattern 218 and the hard mask pattern 216a, and a gate insulating layer 222 is interposed between at least the pin pattern 218 and the gate electrode 225. The gate insulating layer 222 may be extended to be interposed between the gate electrode 225 and the hard mask pattern 216a. A pair of impurity diffusion layers 227 are disposed in the pin pattern 218 on both sides of the gate electrode 225. The impurity diffusion layer 227 corresponds to a source / drain region.

  An element isolation layer 220 a is interposed between the gate electrode 225 and the support substrate 205 around the pin pattern 218. The element isolation film 220a is made of an insulating film. For example, the device isolation layer 220a may be a silicon oxide layer. The pin pattern 218 may be electrically isolated by the device isolation layer 220a.

  In the pin field effect transistor having the above-described structure, the pin pattern 218 has a structure in which first and second semiconductor patterns 210a and 212a having a wider lattice width than a general silicon crystal are alternately stacked. Accordingly, as described with reference to FIG. 4, carrier mobility can be increased in the channel region to improve the performance of the pin field effect transistor. In addition, the lower surface of the pin pattern 218 is connected to the support substrate 205. Accordingly, the floating body effect that can be generated in the SOI substrate can be prevented, and even if heat is generated in the pin pattern 218, the heat in the pin pattern 218 is effectively released to the support substrate 205. Is done.

  11 to 13 are process cross-sectional views taken along the line IV-IV 'of FIG. 8 for explaining a method of forming a pin field effect transistor according to another embodiment of the present invention.

  Referring to FIG. 11, a buffer semiconductor layer 202 and a relaxed semiconductor layer 204 are sequentially formed on a semiconductor substrate 200. The semiconductor substrate 200, the buffer semiconductor layer 202, and the relaxed semiconductor layer 204 may constitute a support substrate 205.

  Preferably, the semiconductor substrate 200 is a silicon substrate, the buffer semiconductor layer 202 is formed of a grade silicon-germanium layer, and the relaxed semiconductor layer 204 is formed of a relaxed silicon-germanium layer. The grade silicon-germanium layer and the relaxed silicon-germanium layer can be formed in the same manner as in the above-described embodiment.

  A multilayer film 214 including a plurality of first semiconductor layers 210 and second semiconductor layers 212 stacked alternately on the relaxed semiconductor layer 204 is formed. One of the first semiconductor layer 210 and the second semiconductor layer 212 may be formed of an expanded silicon film using an epitaxial growth process, and the other may be formed of a silicon-germanium layer using an epitaxial growth process. desirable. At this time, the silicon-germanium layer in the multilayer film 214 is preferably formed to have the same germanium concentration as the relaxed semiconductor layer 204. Accordingly, the silicon-germanium layer in the multilayer film 214 has the same lattice width as the relaxed semiconductor layer 204, and the expanded silicon film in the multilayer film 214 is level with the relaxed semiconductor layer 204. It expands to have the same grid width in the direction. The silicon-germanium layer or the relaxed semiconductor layer 204 in the multilayer film 214 serves as a buffer that absorbs the stress of the expanded silicon film in the multilayer film 214.

  The multilayer film 214 may be formed in the same form as the uppermost layer and the lowermost layer of the multilayer film 114 shown in FIG.

  A hard mask film 216 is formed on the multilayer film 214.

  Referring to FIGS. 12 and 13, the hard mask layer 216 and the multilayer film are continuously patterned to form a pin pattern 218 and a hard mask pattern 216a that are sequentially stacked. The pin pattern 218 is formed as a multilayer pattern including a plurality of first semiconductor patterns 210a and second semiconductor patterns 212a that are alternately stacked.

  An element isolation insulating layer 220 is formed on the entire surface of the support substrate 205 having the pin pattern 218 and the hard mask pattern 216a. The element isolation insulating film 220 is formed of an insulating film. For example, it can be formed of a silicon oxide film.

  The element isolation insulating layer 220 is planarized until the upper surface of the hard mask pattern 216a is exposed. Subsequently, an element isolation film 220a is formed so as to selectively surround the planarized element isolation insulating film. The upper surface of the device isolation layer 220 a is formed lower than the upper surface of the pin pattern 218. As a result, the upper sidewall of the pin pattern 218 is exposed. The lower surface of the pin pattern 218 is connected to the relaxed semiconductor layer 204.

  A thermal oxidation process is performed on the support substrate 205 having the element isolation layer 220a. Accordingly, the gate insulating layer 222 is formed on the exposed upper sidewall of the pin pattern 218. At this time, a thermal silicon oxide film and a thermal germanium oxide film can coexist in the gate insulating film 222.

  The gate insulating layer 222 can be formed by other methods. First, a surface semiconductor layer is formed on the entire surface of the support substrate 205 having the element isolation layer 220a using a chemical vapor deposition method or an epitaxial growth process. Subsequently, the surface semiconductor layer can be thermally oxidized to form the gate insulating film 222. At this time, the gate insulating film 222 may be formed of a thermal oxide film having the same component. The surface semiconductor layer can be formed of a silicon film.

  Subsequently, as shown in FIG. 8, a gate electrode 225 is formed on the support substrate 205 having the gate insulating film 222 so as to cross over the pin pattern 218 and the hard mask pattern 216a. Impurity ions are implanted using the gate electrode 225 as a mask to form a pair of impurity diffusion layers 227 shown in FIG. 8 in the pin pattern 218 on both sides of the gate electrode 225.

  In the first embodiment and the second embodiment, components corresponding to each other can be formed of the same material.

1 is a perspective view illustrating a pin field effect transistor according to an embodiment of the present invention. It is sectional drawing cut | disconnected along II 'of FIG. It is sectional drawing cut | disconnected along II-II 'of FIG. FIG. 3 is a schematic energy band diagram cut along III-III ′ in FIG. 2. FIG. 3 is a process cross-sectional view taken along the line II ′ of FIG. 2 for explaining a method of forming a pin field effect transistor according to an embodiment of the present invention. FIG. 3 is a process cross-sectional view taken along the line II ′ of FIG. 2 for explaining a method of forming a pin field effect transistor according to an embodiment of the present invention. FIG. 3 is a process cross-sectional view taken along the line II ′ of FIG. 2 for explaining a method of forming a pin field effect transistor according to an embodiment of the present invention. FIG. 6 is a perspective view showing a pin field effect transistor according to another embodiment of the present invention. It is sectional drawing cut | disconnected along IV-IV 'of FIG. FIG. 10 is a cross-sectional view taken along line VV ′ of FIG. 9. FIG. 11 is a process cross-sectional view taken along the line IV-IV ′ of FIG. 8 to describe a method of forming a pin field effect transistor according to another embodiment of the present invention. FIG. 11 is a process cross-sectional view taken along the line IV-IV ′ of FIG. 8 to describe a method of forming a pin field effect transistor according to another embodiment of the present invention. FIG. 11 is a process cross-sectional view taken along the line IV-IV ′ of FIG. 8 to describe a method of forming a pin field effect transistor according to another embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor substrate 102 Buffer semiconductor layer 104a Relaxed semiconductor layer 105 Support substrate 106 Buried insulating film 116a Hard mask pattern 120 Gate insulating film 122 Gate electrode 125 Impurity diffusion layer

Claims (26)

  A pin pattern including first and second semiconductor patterns sequentially protruding from the semiconductor substrate, wherein the first and second semiconductor patterns have a lattice width larger than the lattice width of the substrate material in at least one direction; A pin field-effect transistor comprising:   The pin pattern includes a plurality of the first and second semiconductor patterns alternately stacked so that the height of the pin pattern increases, and one of the first and second semiconductor patterns is another one. 2. The pin field effect transistor according to claim 1, wherein stress is reduced.   2. The lattice width of the first and second semiconductor patterns is larger than the lattice width of the substrate along a length direction of a transistor channel defined in the pin pattern. Pin field effect transistor.   The one of the first and second semiconductor patterns is formed of expanded silicon, and the other of the first and second semiconductor patterns is formed of silicon germanium. 2. The pin field effect transistor according to 1. A buffer semiconductor layer on the substrate;
The pin field effect transistor according to claim 1, further comprising a relaxed semiconductor layer on the buffer semiconductor film.   6. The pin field effect transistor of claim 5, wherein the substrate is formed of silicon, the buffer semiconductor layer is formed of grade silicon germanium, and the relaxed semiconductor layer is formed of silicon germanium.   The germanium concentration of the buffer semiconductor layer increases gradually from the bottom surface to the top surface thereof, and the germanium concentration of the relaxed semiconductor layer is uniform, and the germanium concentration of the relaxed semiconductor layer is the buffer semiconductor layer 7. A pin field effect transistor according to claim 6, characterized in that it has the same maximum concentration of germanium in the layer.   6. The pin field effect transistor of claim 5, wherein one of the first and second semiconductor patterns is formed of the same material as the relaxed semiconductor layer.   6. The pin field effect transistor of claim 5, wherein the pin pattern further includes a third semiconductor pattern, and the third semiconductor pattern is formed of the same material as the relaxed semiconductor layer. An element isolation film disposed on the substrate and surrounding a lower portion of the pin pattern;
The pin field effect transistor according to claim 1, further comprising a gate electrode partially disposed on the device isolation film.   The pin field effect transistor according to claim 1, further comprising a hard mask film disposed on the pin pattern. A semiconductor substrate having a first lattice width along the first and / or second direction;
A first semiconductor pattern having a second lattice width along the first and / or second direction;
A second semiconductor pattern having a third lattice width along the first and / or second direction,
The pin electric field characterized in that the second and third lattice widths are larger than the first lattice width, and the first and second semiconductor patterns are sequentially stacked to form a pin pattern protruding from the substrate. Effect transistor.   Forming a pin pattern that protrudes from the semiconductor substrate and includes stacked first and second semiconductor patterns, wherein the first and second semiconductor patterns are larger in at least one direction than a lattice width of the substrate material; A method for forming a pin field-effect transistor having a width. The step of forming the pin pattern includes:
Forming a plurality of first and second semiconductor patterns alternately stacked so that a height of the pin pattern is increased, wherein one of the first and second semiconductor patterns is another 14. The method of forming a pin field effect transistor according to claim 13, wherein one of the stresses is reduced.   14. The lattice width of the first and second semiconductor patterns is larger than the lattice width of the substrate along a length direction of a transistor channel defined in the pin pattern. Of forming a pin field effect transistor.   The one of the first and second semiconductor patterns is formed of expanded silicon, and the other of the first and second semiconductor patterns is formed of silicon germanium. 14. A method for forming a pin field effect transistor according to item 13. Forming a buffer semiconductor layer on the substrate;
The method of forming a pin field effect transistor according to claim 13, further comprising: forming a buffered semiconductor layer on the buffer semiconductor film.   The method of claim 17, wherein the substrate is formed of silicon, the buffer semiconductor layer is formed of grade silicon germanium, and the relaxed semiconductor layer is formed of silicon germanium.   As the germanium concentration of the buffer semiconductor layer increases from the bottom surface to the top surface thereof, the germanium concentration gradually increases, the germanium concentration of the relaxed semiconductor layer is uniform, and the germanium concentration of the relaxed semiconductor layer is the buffer semiconductor layer 19. The method of forming a pin field effect transistor according to claim 18, wherein the same is the same as the maximum concentration of germanium.   The method of claim 17, wherein one of the first and second semiconductor patterns is formed of the same material as the relaxed semiconductor layer.   The method of claim 17, wherein the pin pattern further includes a third semiconductor pattern, and the third semiconductor pattern is formed of the same material as the relaxed semiconductor layer. Forming an element isolation film disposed on the substrate and surrounding a lower portion of the pin pattern;
The method according to claim 13, further comprising: forming a gate electrode partially disposed on the device isolation film.   The method of claim 13, further comprising forming a hard mask film disposed on the pin pattern. Providing a semiconductor substrate having a first lattice width along a first and / or second direction;
Forming a first semiconductor pattern having a second lattice width along the first and / or second direction;
Forming a second semiconductor pattern having a third lattice width along the first and / or second direction,
The pin electric field characterized in that the second and third lattice widths are larger than the first lattice width, and the first and second semiconductor patterns are sequentially stacked to form a pin pattern protruding from the substrate. Method for forming effect transistor. A support substrate including a semiconductor substrate, a buffer semiconductor layer and a relaxed semiconductor layer sequentially stacked on the semiconductor substrate;
A pin pattern including a multilayer pattern having a plurality of first and second semiconductor patterns disposed on the support substrate and alternately stacked;
A gate electrode across the pin pattern;
A gate insulating film interposed between the pin pattern and the gate electrode;
And at least one impurity diffusion layer located in the pin pattern on both sides of the gate electrode,
The pin field effect transistor according to claim 1, wherein the first and second semiconductor patterns have a lattice width wider than the lattice width of the substrate material in at least one direction. Forming a semiconductor substrate, a support substrate including a buffer semiconductor layer and a relaxed semiconductor layer sequentially stacked on the semiconductor substrate;
Forming a multilayer film having a plurality of first and second semiconductor layers alternately stacked on the support substrate;
Patterning the multilayer film to form a pin pattern including first and second semiconductor patterns;
Forming a gate insulating film on the pin pattern;
Forming a gate electrode across the pin pattern;
Forming at least one impurity diffusion layer in the pin pattern on both sides of the gate electrode,
The method of forming a pin field effect transistor, wherein the first and second semiconductor patterns have a lattice width wider than the lattice width of the substrate material in at least one direction.

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