JP2002057329A - Vertical field effect transistor and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: An object of the present invention is to provide a vertical field-effect transistor in which tensile strain is applied in all directions of a channel layer to achieve higher speed and higher performance. A substrate having one main surface, a first SiGe layer of one conductivity type provided on the one main surface,
An intermediate layer 5 made of a material having a different lattice constant from Si electrically separated from the first SiGe layer 4;
A second SiGe layer 6 of one conductivity type separated from the layer 4 and electrically separated from the intermediate layer 5, and from the first SiGe layer 4 including the surface of the intermediate layer 5 to the second SiGe Strain S having tensile strain laminated on the surface up to layer 6
A vertical field-effect transistor having an i-layer 7, a gate insulating film 8 and a gate electrode 9 provided on the strained Si layer 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical field-effect transistor in which the performance of a vertical field-effect transistor is enhanced by making the most of crystal distortion in a channel layer, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, it has been known that the operating speed of a field effect transistor can be increased by using strained Si as a channel. However, Liu, K. . C. El by etc.
electron Devices Meeting, 199
9. IEDM Technical Digest. I
international, 1999 Page
(S): “A Novel” in 3.3.1-3.3.4.
Sidewall Strained-Si Chan
nel nMOSFET "is known.

[0003] This known vertical field effect transistor is:
A columnar laminated structure in which an undoped SiGe layer is sandwiched between upper and lower layers of n-type Si serving as source and drain regions is formed on the surface of the Si substrate. Upper layer, SiGe layer, and Si
(Lower layer), a very thin strained Si film of 1200 nm or less and a gate oxide film are formed on the side surface, and a poly Si gate electrode is provided on the surface of the gate oxide film corresponding to the side surface of the SiGe layer. ing.

In such a vertical field effect transistor, since the SiGe layer is formed on the lower Si layer, the lattice constant of the SiGe layer in a direction parallel to the surface of the Si substrate is accompanied by compressive strain. It becomes equal to the lattice constant of Si. On the other hand, in the direction perpendicular to the Si substrate surface of the SiGe layer, the lattice constant becomes larger than the original lattice constant of SiGe, and the ultra-thin strained Si film serving as a channel is formed of SiG.
e The material is elastically deformed to match a lattice constant larger than the original lattice constant. Since the strained Si film has a lattice constant of Si smaller than that of SiGe, the strained Si film comes into contact with a lattice constant larger than the original lattice constant of SiGe, thereby receiving a greater stress and receiving a tensile strain in a direction perpendicular to the Si substrate surface. I have.

[0005]

However, in the above configuration, the strain is applied only to the strained Si film in a direction perpendicular to the surface of the Si substrate, and the strained Si film is formed in a direction perpendicular to the thickness direction of the Si film forming the channel. The ratio of electronic structure change of electrons and holes is smaller than that in the case where strain is applied in the direction of
As a result, there is a problem that the effect of increasing the speed and improving the performance due to the distortion of the MOS transistor is limited.

SUMMARY OF THE INVENTION The present invention has been made in view of the problem of the detailed description, and provides tensile strain in all directions perpendicular to the thickness direction of a Si layer forming a channel to increase the speed and the performance. It is an object of the present invention to provide a vertical field-effect transistor that measures the above and a method for manufacturing the same.

[0007]

To solve the above-mentioned problems, the present invention employs the following configuration.

That is, a substrate having one main surface, a first SiGe layer of one conductivity type provided on one main surface of the substrate,
An intermediate layer selectively formed on the first SiGe layer and made of a material having a different lattice constant from Si electrically separated from the first SiGe layer, and provided on the intermediate layer;
A second SiGe layer of one conductivity type separated from the first SiGe layer and electrically separated from the intermediate layer; and a second SiGe layer formed from the first SiGe layer including the intermediate layer surface.
a strained Si layer having a tensile strain laminated on a surface reaching the iGe layer, a gate insulating film provided on the strained Si layer, and a portion corresponding to a separated portion of the first and second SiGe layers. And a gate electrode formed via the gate insulating film.

In this vertical field effect transistor,
It is important for the characteristics of the SiGe layer that the first SiGe layer and the second SiGe layer have relaxed lattice strain.

If the intermediate layer is a reverse-conductivity-type SiGe layer, the first and second SiGe layers can be easily and electrically separated from each other by a PN junction.

Further, the first SiGe layer, the second SiGe layer
If the Ge layer and the intermediate layer are formed from a single layer integrally provided on one main surface of the substrate, and the single layer is selectively removed to form a columnar portion, the strain Si It is easy to ensure the flatness of the side wall of the columnar portion where the layer is formed.

In order to secure the gate width in particular,
It is preferable that the strained Si layer, the gate insulating film, and the gate electrode are formed so as to surround a side wall of the columnar portion.
Furthermore, the vertical field effect transistor of the present invention can be configured as follows. That is, a substrate having one main surface, a first SiGe layer of one conductivity type provided on one main surface of the substrate, and the first SiGe layer selectively formed on the first SiGe layer. An intermediate layer made of a material having a different lattice constant from Si electrically separated from the layer, and an intermediate layer provided on the intermediate layer and separated from the first SiGe layer;
A second SiGe layer of one conductivity type electrically separated from the intermediate layer; and the first SiG layer including a surface of the intermediate layer.
a third SiGe layer laminated on a surface from the e layer to the second SiGe layer, a strained Si layer having a tensile strain laminated on the third SiGe layer, and a third SiGe layer provided on the strained Si layer. Gate insulating film, and the first and second S
A vertical field-effect transistor having a gate electrode formed via the gate insulating film corresponding to a separated portion of the iGe layer.

In the vertical field effect transistor having such a structure, the first SiGe layer and the second SiGe
It is important for the characteristics of the SiGe layer that the layer and the third SiGe layer have relaxed lattice strain.

Further, by forming the intermediate layer from an insulating layer, electrical separation from the first SiGe layer and the second SiGe layer is reliably performed, and a higher speed operation is expected from the effect of reducing stray capacitance. it can.

Further, the first SiGe layer and the second SiGe layer
If the Ge layer and the intermediate layer are formed from a single layer integrally provided on one main surface of the substrate, and the single layer is selectively removed to form a columnar portion, the strain Si It is easy to ensure the flatness of the side wall of the columnar portion where the layer is formed.

In order to secure the gate width in particular,
It is preferable that the strained Si layer, the gate insulating film, and the gate electrode are formed so as to surround a side wall of the columnar portion.

Further, the configuration in which the element isolation insulating layer is interposed between the substrate and the first SiGe layer can substantially eliminate leak current and stray capacitance between the substrate and the drain region. This is extremely effective in reducing power consumption and operating speed.

In the above-mentioned vertical field effect transistor, a manufacturing method suitable for forming the intermediate layer into a reverse-conductivity-type SiGe layer requires the following steps.

That is, a step of preparing a substrate having one major surface, a step of forming a first SiGe layer of one conductivity type on the one major surface, and a step of forming a first conductivity type SiGe layer on the first SiGe layer. Second
Forming a third SiGe layer of one conductivity type on the second SiGe layer, and selectively removing the first to third SiGe layers from the first to third SiGe layers. Forming a columnar portion of the stacked structure of the first to third SiGe layers extending in a direction intersecting one main surface of the substrate; and forming a Si portion on a sidewall surface of the columnar portion.
Stacking layers to form a strained Si layer having tensile strain, forming a gate insulating film on the strained Si layer, and corresponding to the separated portions of the first and third SiGe layers. Forming a gate electrode via the gate insulating film.

A manufacturing method suitable for using the intermediate layer as an insulating layer requires the following steps.

That is, a step of preparing a substrate having one main surface, a step of forming a first SiGe layer of one conductivity type on the one main surface, an upper surface of the first SiGe layer, and an upper surface thereof The first SiGe is located at a position away from the bottom surface facing
Forming an insulating layer for electrically separating the layer into an upper layer and a lower layer; and selectively removing the upper layer, the lower layer, and the insulating layer of the first SiGe layer in a direction intersecting one main surface of the substrate. Forming an elongated columnar portion of the laminated structure of the first SiGe layer and the insulating layer, forming a second SiGe layer on the side wall surface of the columnar portion,
stacking a Si layer on the surface of the e layer to form a strained Si layer having a tensile strain, and forming a gate on the strained Si layer along the columnar portion side wall between the upper and lower layers of the first SiGe layer. Forming an insulating film; and forming a gate electrode on the gate insulating film.

According to the present invention, since the strained Si layer of the channel region is formed over the SiGe layer having a surface perpendicular to one main surface of the substrate, the direction perpendicular to the one main surface of the substrate and the substrate Tensile strain is also applied in a direction parallel to one principal plane of the substrate and perpendicular to the thickness direction of the strained Si layer, so that it operates at a higher speed than a vertical field-effect transistor using tensile strain only in the direction perpendicular to one principal plane of the substrate. Can be provided.

[0023]

(First Embodiment) FIG. 1 is a partial sectional view showing a vertical field effect transistor according to a first embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes p-type Si (silicon)
The substrate 2 is a graded layer of p-doped SiGe (silicon germanium), 3 is a buffer layer of similarly p-doped SiGe (silicon germanium), and 4 and 6 are lattice strain relaxed. N + type SiGe
(Silicon-germanium) layer, 5 is a p-type SiGe (silicon-germanium) layer whose lattice strain is relaxed, 7 is a strained Si (silicon) layer, 8 is a gate insulating film of silicon oxide (silicon), and 9 is many. A gate electrode of crystalline Si (silicon), 10 to 12 are gate, source and drain wiring layers made of a metal such as Al, 13 is an insulating layer, and 14 is oxidized S
It is an element isolation insulating layer of i (silicon).

As shown in the figure, a part of the center of the n + -type SiGe layer 4, the p − -type SiGe layer 5 thereabove, and the n + -type
The type SiGe layer 6 is formed in a columnar shape, and these three Si
The side surface of the columnar portion composed of the Ge layer is the strained Si layer 7.
Covered by

The n + -type SiGe layer 4 is formed so that the cross section including the columnar portion is formed in a convex shape, and has a part of the columnar portion and a continuous extension at the bottom of the portion.
Further, as described above, the strained Si layer 7 is formed so as to surround the side surface of the columnar portion, and a part thereof is n + type S
It also extends to the surface of the extending portion of the iGe layer 4. And
Since the three layers constituting the columnar portion are all SiGe layers, the strained Si layer 7 is not only subjected to tensile strain in the direction perpendicular to the substrate surface along the side surface of the columnar portion, but also to the columnar portion. Tensile strain is also applied in a direction parallel to the substrate surface along the side surface of the substrate.

In the vertical field effect transistor, when a gate voltage is applied to the gate electrode 9, a channel is formed on the surface of the strained Si layer 7 and, in some cases, the p-type SiGe layer 5 facing the gate electrode. An inversion layer is generated and operates so that a current flows between the n + -type SiGe layer 6 as the source region and the n + -type SiGe layer 4 as the drain region.

Next, a method of manufacturing the field effect transistor will be described with reference to FIGS.

First, as shown in FIG.
Si (1-y) Ge is grown thereon by epitaxial growth.
The graded layer 2 of (y) is formed. In the graded layer 2, the value of y can be changed from 0 to a range of 0.2 to 0.5, for example, a thickness of 1000 nm. Here, the case where Si is used for the substrate is described, but a material suitable for forming an epitaxial layer such as SiGe can be used.

Subsequently, a buffer layer 3 of Si (1-x) Ge (x) whose lattice strain has been relaxed by epitaxial growth
Is formed. X of the buffer layer 3 is the graded layer 2
Are selected to match the lattice constant of the upper surface of. Therefore,
A crystal structure having substantially no distortion is obtained on the surface of the buffer layer 3.

Next, on the surface of the buffer layer 3, the n + -type impurity is doped at a high concentration, the SiGe layer 5 is doped with the p-type impurity, and the n + -type impurity is doped similarly to the SiGe layer 4.
A stacked structure of the SiGe layer 6 heavily doped with the type impurity is formed by continuous epitaxial growth. Here, instead of forming the SiGe layers 4 to 6 by continuous epitaxial growth, a stacked structure may be formed by alternately performing ion implantation and epitaxial growth.

Thereafter, as shown in FIG. 3, a groove is provided at a position other than a region where an element is to be formed, and SiO 2 is formed in the groove.
The element isolation insulating layer 14 is formed by filling an insulator such as 2.

Next, as shown in FIG.
The layers 4 to 6 are made of RIE (Reactive I
(Etching) to form a columnar portion 20.

As shown in FIG. 5, a strained Si layer 7 having a thickness of 10 nm is formed on the SiGe layer 4 by epitaxial growth.
The SiGe layer 6 is formed on the side wall surface of the columnar portion 20 and on the surface of the SiGe layer 6. Then, 7
The strained Si layer 7 is oxidized by wet oxidation with oxygen dilution at 00 ° C., and a 2 nm-thick Si oxide film serving as a gate insulating film 8 is formed.

Further, as shown in FIG.
A polycrystalline Si film having a thickness of 200 nm is deposited on the entire surface including the surface of the gate insulating film 8 and the surface of the element isolation insulating layer 14 by a method, and the gate electrode 9 is patterned by anisotropic etching such as RIE. At this time, the gate electrode 9 is illustrated in advance so that the gate electrode 9 exists at least on the gate insulating film 8 provided on the side wall of the columnar portion 20 and on the region where the wiring layer 10 for extracting the gate electrode 9 is to be formed. RIE is performed by coating with no resist film.

Further, as shown in FIG.
A 500 nm Si oxide film is deposited by CVD and planarized, and a contact hole is opened by RIE. Thereafter, an aluminum film containing 1% of Si is deposited by a sputtering method, and is patterned to form the gate, source, and drain wiring layers 10 to 12 as shown in FIG.

Thereafter, the semiconductor device is completed through a passivation film forming step and the like in the same manner as in a normal semiconductor device manufacturing method.

As described above, according to the present embodiment, the strained Si with tensile strain applied in all directions perpendicular to the film thickness direction.
A vertical field-effect transistor using the layer 7 as a channel region can be manufactured. Therefore, the mobility of carriers is greatly improved as compared with the conventional vertical field effect transistor in which the effect of the distortion is limited to the direction perpendicular to the substrate along the side wall of the columnar portion 20, and the operation speed and the performance are improved. Can be planned. (Second Embodiment) FIG. 8 is a partial sectional view showing a vertical field-effect transistor according to a second embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

This embodiment is different from the first embodiment described above in that the relaxed SiGe layer in which the lattice strain is relaxed is
It is formed directly on the Si oxide film, and uses a mesa isolation instead of a trench isolation as an element isolation method.

In FIG. 8, reference numeral 1 denotes p-type Si (silicon)
The substrate, 30 is a SiGe (silicon germanium) layer,
Reference numeral 32 denotes a buried oxide film, and reference numerals 300 and 6 denote n + -type SiGe (silicon-germanium) layers in which lattice strain is relaxed.
Is a p-type SiGe (silicon-germanium) layer with relaxed lattice strain, 7 is a strained Si (silicon) layer, and 8 is S oxide
a gate insulating film of i (silicon); 9, a gate electrode of polycrystalline Si (silicon); 10 to 12, gate and source / drain wiring layers of metal such as Al;
An insulating layer made of i (silicon) or the like for element isolation.

As shown, the n + type SiGe layer 30
0, and a p- type SiGe layer 5 and an n + type SiGe layer 6 thereon are formed in a columnar shape, and the side surface of the columnar portion formed by these three SiGe layers has strained Si.
Covered by layer 7.

The n + type SiGe layer 300 has a section including the columnar portion formed in a convex shape, and is processed so as to have a part of the columnar portion and a continuous extension at the bottom of the portion. Further, as described above, the strained Si layer 7 is formed so as to surround the side surface of the columnar portion, and a part thereof is n +
It also extends to the surface of the extending portion of the type SiGe layer 300.
The three layers constituting the columnar portion are all SiG.
Because of the e-layer, the strained Si layer 7 is not only subjected to tensile strain in a direction perpendicular to the substrate surface along the side surface of the columnar portion, but also in a direction parallel to the substrate surface along the side surface of the columnar portion. Also, tensile strain is applied.

In the vertical field effect transistor, when a gate voltage is applied to the gate electrode 9, a channel is formed on the surface of the strained Si layer 7 and, in some cases, the p-type SiGe layer 5 facing the gate electrode. An inversion layer is generated and operates so that a current flows between the n + -type SiGe layer 6 as the source region and the n + -type SiGe layer 300 as the drain region.

A method of manufacturing the vertical field effect transistor according to the present embodiment will be described below with reference to FIGS.

First, as shown in FIG.
The iGe layer 30 is epitaxially grown to a thickness of 1000 nm. In this case, a thin Si layer 3 is provided on the top to protect the substrate.
Preferably there is one. Next, oxygen is supplied into the SiGe layer 30 at an acceleration energy of 180 keV and a dose of 4 ×.
Under conditions of 10E17 cm−2, Si substrate 1 and SiGe
Ion implantation is performed so that a concentration peak exists at a position away from the surface of the layer 30. Thereafter, the buried oxide film 32 is formed by annealing at a temperature of 1350 ° C. for 4 hours in a nitrogen atmosphere containing a small amount of oxygen.

By the annealing, the buried oxide film 32 is formed.
In the upper SiGe layer 30, the lattice strain is relaxed and the strain is minimized.
An oxide film 33 is formed. In addition, Ge is diffused from the SiGe layer 30 immediately below the buried oxide film 32 in the direction of the Si substrate 1 to be in a state shown in FIG.

Next, As is added as an n-type impurity to the SiGe layer 300 on the buried oxide film 32 by 50 keV,
Ions are implanted at 6.0 × 10E15 cm−2, and annealing is performed to activate impurities. After removing the oxide film on the surface generated during this annealing with hydrofluoric acid, the p-type doped SiGe layer 5 and the n-type doped Si
The Ge layer 6 is subsequently epitaxially grown to obtain a laminated structure shown in FIG.

Next, as shown in FIG.
By the method, the n + -type SiGe layer 300, the p − -type SiGe layer 5, and the n + -type SiGe layer 6 are selectively removed, and the columnar projection 200 is formed.

A strained Si layer having a thickness of 10 nm is formed by epitaxial growth on the surface of the columnar projection 200 formed in the previous step and the n + -type SiGe layer 300 connected to the bottom of the columnar projection 200. Although not shown,
The resist is patterned by photo-etching so as to protect the columnar projections 200 and the periphery thereof, and the n + type SiGe layer 300 is removed by RIE until reaching the buried oxide film 32 as shown in FIG. Perform separation.

Subsequently, as shown in FIG.
The strained Si layer 7 is oxidized by oxygen dilution wet oxidation at a temperature of 0 ° C., and a 2-nm-thick Si oxide film is formed as the gate insulating film 8.

Further, as shown in FIG.
A polycrystalline Si film having a thickness of 200 nm is deposited on the entire surface including the surface of the gate insulating film 8 and the surface of the buried oxide film by the method D, and the gate electrode 9 is patterned by anisotropic etching such as RIE. At this time, the gate electrode 9 is not shown in advance so that the gate electrode 9 exists at least on the gate insulating film 8 provided on the side wall of the columnar protrusion and in the region where the wiring layer 10 for extracting the gate electrode 9 is to be formed. RIE is performed after being covered with a resist film.

Further, as shown in FIG.
A 500 nm Si oxide film is deposited by CVD and planarized, and a contact hole is opened by RIE. Thereafter, an aluminum film containing 1% of Si is deposited by a sputtering method and is patterned to form each of the gate, source, and drain wiring layers 10 to 12.

Thereafter, the semiconductor device is completed through a passivation film forming step and the like in the same manner as in a normal semiconductor device manufacturing method.

As described above, according to the present embodiment, not only tensile strain in the direction perpendicular to the substrate surface is applied along the side surface of the columnar portion, but also in the direction parallel to the substrate surface along the side surface of the columnar portion. A vertical field-effect transistor using the strained Si layer 7 subjected to tensile strain as a channel region can be manufactured. Therefore, the mobility of carriers is greatly improved as compared with the conventional vertical field effect transistor in which the effect of distortion is limited to the direction perpendicular to the substrate surface in the direction along the side wall of the columnar protrusion, and the operating speed is increased and the performance is improved. Can be achieved.

Further, since the drain region is in direct contact with the buried oxide film, the drain capacitance can be reduced and the operation speed can be further increased as compared with the case where the drain region is separated by a PN junction. (Third Embodiment) FIG. 16 is a sectional view of an element structure showing a field effect transistor having a vertical columnar structure according to a third embodiment of the present invention. FIG. 8 according to the second embodiment.
The same reference numerals are given to the same parts as in the above, and the detailed description thereof is omitted.

This embodiment is different from the above-described second embodiment in that an insulating layer is formed instead of the p − -type SiGe layer 5. Further, the formation of the source region and the drain region is different in that they are formed by ion implantation after the formation of the gate electrode.

In FIG. 16, reference numeral 100 denotes an SOI substrate, 3
0 is a SiGe (silicon-germanium) layer, 32 is a buried oxide film, 41 is a strained SiGe (silicon-germanium) layer, 42 is a strained Si (silicon) layer, 43 is a source region, 44 is a drain region, and 8 is Si oxide. (silicon)
Is a gate electrode of polycrystalline Si (silicon), 10 is a gate, source and drain wiring layer made of metal such as Al, and 13 is an insulating layer.

In the vertical field effect transistor, when a gate voltage is applied to the gate electrode 9, an inversion layer serving as a channel is formed on the surface of the strained Si layer 42 and the surface of the strained SiGe layer 41 facing the gate electrode. It operates so that a current flows between the source region 43 and the drain region 44.

The method of manufacturing the field-effect transistor according to the present embodiment will be described below with reference to FIGS.

First, as shown in FIG. 17, SOI having a laminated structure of a Si substrate, a buried oxide film, and a Si layer
(Silicon On Insulator) Substrate 1
A SiGe layer 30 is epitaxially grown to a thickness of 1000 nm on the substrate. In this case, it is desirable that there be a thin Si layer 31 on the uppermost layer to protect the substrate.

Next, oxygen is introduced into the SiGe layer 30 at an acceleration energy of 180 keV and a dose of 4 × 10E17 cm−.
Under the conditions of 2, the buried oxide film of the SOI substrate 100 and S
Ion implantation is performed so that a concentration peak exists at a position away from the surface of the iGe layer 30. After that, the temperature is 1350 ° C
For 4 hours in a nitrogen atmosphere containing a small amount of oxygen to form a buried oxide film 32 as shown in FIG.

At the end of the annealing, the SiGe layers above and below the buried oxide film 32 are in a state where the lattice strain is relaxed, and the strain is minimized. Ge in the SiGe layer 30 immediately below the buried oxide film 32 diffuses into the Si layer of the SOI substrate 100 by the annealing, but further diffusion is prevented by the buried oxide film. Further, the surface of the SiGe layer 30 on the buried oxide film 32 is
An oxide film 33 is formed, and this oxide film 33 is removed by hydrofluoric acid.

Next, as shown in FIG. 19, the buried oxide film 32 and the upper and lower SiGe layers 30
The columnar structure 400 is selectively removed by the method E and provided. Also, on the surface thereof, strained SiGe having a thickness of 20 nm is formed.
A layer 41 and a strained Si layer 42 having a thickness of 10 nm are laminated.

Here, the SiGe layer 30 extending continuously to the bottom of the columnar structure 400 is partially left around the bottom of the columnar structure 400 together with the strained SiGe layer 41 and the strained Si layer 42 thereabove. As shown in FIG. 20, the buried oxide film of the SOI substrate 100 is selectively removed by the RIE method until the buried oxide film is exposed, and element isolation is performed by this processing as shown in FIG.

Subsequently, the surface layer of the strained Si layer 42 is oxidized by wet oxidation with oxygen dilution at 700 ° C. to have a thickness of 2 nm.
Is formed as the gate insulating film 8. Thereafter, polycrystalline Si having a thickness of 200 nm is formed by LPCVD.
A film is deposited and processed by RIE to form a gate electrode 9.
Is formed. Note that the gate electrode can be easily pulled out by forming a resist pattern on a part of the region following the side wall of the columnar structure portion 400 before processing by the RIE method and leaving the polycrystalline Si film.

Further, as shown in FIG. 21, using the gate electrode as a mask, the source region 43 and the drain region 44 are used.
Is implanted to form. The ion implantation conditions at this time are, for example, 6.0 × 1 with As at 50 keV.
What is necessary is just to set it to 0E15cm-2. Thereafter, annealing is performed to activate the ion-implanted As, so that the source region 43 and the drain region 44 are formed.

Since the subsequent manufacturing method is the same as that of FIG. 8 of the second embodiment and the above description relating to FIG.
Although the description is omitted, the structure shown in FIG. 16 is obtained by forming the insulating layer 13 and the wiring layers 10 to 12 for the gate, source, and drain.

As described above, according to this embodiment, not only tensile strain in the direction perpendicular to the substrate surface is applied along the side surface of the columnar portion, but also in the direction parallel to the substrate surface along the side surface of the columnar portion. Also, a vertical field effect transistor using the strained Si layer 42 subjected to tensile strain as a channel region can be manufactured. Therefore, as compared with the conventional vertical field-effect transistor in which the effect of the distortion is limited to the direction perpendicular to the substrate surface along the columnar projection side wall, the carrier mobility is greatly improved, and the operation speed is increased and the performance is improved. Can be achieved.

Further, since the drain region is in direct contact with the buried oxide film, the drain capacitance can be reduced and the operation speed can be further increased as compared with the case where the drain region is separated by a PN junction. Further, since the channel portion of the vertical field effect transistor is substantially shallow by the buried oxide film 32, punch-through is suppressed.

In each of the above embodiments of the present invention, an n-channel field-effect transistor has been described. However, if the conductivity type of the impurity is reversed, the p-channel field-effect transistor is configured in exactly the same manner. In addition, the same effect as in the present embodiment can be obtained. Therefore, it can be configured as a complementary field effect transistor. Also,
In addition to using the vertical field effect transistor alone, other active elements or resistors such as planar type field effect transistors and bipolar transistors, inductors,
It is also possible to use the vertical field effect transistor of the present embodiment as a part of a semiconductor integrated circuit device including a passive element such as a capacitor.

Further, the present invention is not limited to the above-described embodiments, and can be variously modified and implemented without departing from the gist thereof.

[0072]

As described above in detail, in the vertical field effect transistor of the present invention, not only the tensile strain in the direction perpendicular to the substrate surface is applied along the side surface of the columnar portion, but also the side surface of the columnar portion. A strained Si layer having tensile strain applied along a direction parallel to the substrate surface can be used as a channel region. Therefore, the mobility of the carrier is improved by the effect of the distortion, and the operation speed can be increased.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an element structure of a vertical field effect transistor according to a first embodiment.

FIG. 2 is a sectional view showing a manufacturing process of the vertical field effect transistor according to the first embodiment.

FIG. 3 is a sectional view showing the manufacturing process of the vertical field effect transistor according to the first embodiment.

FIG. 4 is a sectional view showing a manufacturing step of the vertical field-effect transistor according to the first embodiment.

FIG. 5 is a sectional view showing the manufacturing process of the vertical field-effect transistor according to the first embodiment.

FIG. 6 is a sectional view showing the manufacturing process of the vertical field-effect transistor according to the first embodiment.

FIG. 7 is a sectional view showing the manufacturing process of the vertical field-effect transistor according to the first embodiment.

FIG. 8 is a sectional view showing an element structure of a vertical field effect transistor according to a second embodiment.

FIG. 9 is a sectional view showing a manufacturing step of the vertical field-effect transistor according to the second embodiment.

FIG. 10 is a sectional view showing the manufacturing process of the vertical field-effect transistor according to the second embodiment.

FIG. 11 is a sectional view showing a manufacturing step of the vertical field-effect transistor according to the second embodiment.

FIG. 12 is a sectional view showing a manufacturing process of the vertical field-effect transistor according to the second embodiment.

FIG. 13 is a sectional view showing a manufacturing step of the vertical field-effect transistor according to the second embodiment.

FIG. 14 is a sectional view showing a manufacturing step of the vertical field-effect transistor according to the second embodiment.

FIG. 15 is a sectional view showing a manufacturing step of the vertical field-effect transistor according to the second embodiment.

FIG. 16 is a sectional view showing an element structure of a vertical field effect transistor according to a third embodiment.

FIG. 17 is a sectional view showing the manufacturing process of the vertical field-effect transistor according to the third embodiment.

FIG. 18 is a sectional view showing the manufacturing process of the vertical field-effect transistor according to the third embodiment.

FIG. 19 is a sectional view showing a manufacturing step of the vertical field-effect transistor according to the third embodiment.

FIG. 20 is a sectional view showing a manufacturing step of the vertical field-effect transistor according to the third embodiment.

FIG. 21 is a sectional view showing a manufacturing step of the vertical field-effect transistor according to the third embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Si substrate 2 ... Claide layer 3 ... Buffer layer 4,6,300 ... n + SiGe layer 5 ... p-SiGe layer 7 ... Strained Si layer 8 ... Gate insulating film 9 gate electrode 10, 11, 12 wiring layer 13 insulating layer 14 element isolation insulating layer 20 columnar part 30 SiGe layer 31 Si layer 32 ..Embedded oxide film 41: Strained SiGe layer 42: Strained Si layer 43: Source region 44: Drain region 100: SOI substrate 200: Columnar projection 400: Columnar structure

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Koji Usuda, Inventor 1 at Komukai Toshiba-cho, Saiwai-ku, Kawasaki City, Kanagawa Prefecture (72) Inventor Tsutomu Tezuka Toshiba Komukai, Sachi-ku, Kawasaki City, Kanagawa Prefecture No. 1 town Toshiba R & D Center (72) Inventor Tomohisa Mizuno 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture In-house Toshiba Yokohama office (72) Inventor Shinichi Takagi Sachi-ku, Kawasaki-shi, Kanagawa No. 1 Muko Toshiba F-term in Toshiba Research and Development Center Co., Ltd. (Reference)

Claims (16)

[Claims] A substrate having one main surface; and a first conductive type first Si provided on the one main surface of the substrate.
A Ge layer, an intermediate layer selectively formed on the first SiGe layer and made of a material having a different lattice constant from Si electrically separated from the first SiGe layer; A second SiGe layer of one conductivity type separated from the first SiGe layer and electrically separated from the intermediate layer; and a second SiGe layer including the surface of the intermediate layer and the second SiGe layer. A strained Si layer having a tensile strain laminated on a surface reaching the SiGe layer, a gate insulating film provided on the strained Si layer, and a portion separated from the first and second SiGe layers. And a gate electrode formed with the gate insulating film interposed therebetween. 2. The first SiGe layer and a second SiG layer.
2. The vertical field effect transistor according to claim 1, wherein the e layer has a lattice strain reduced. 3. The first SiGe layer has a flat portion and a projecting portion projecting in a direction perpendicular to the one main surface, and the intermediate layer is formed on the projecting portion. The vertical field-effect transistor according to claim 1 or 2, wherein 4. The vertical field effect transistor according to claim 1, wherein said intermediate layer is a SiGe layer of a reverse conductivity type. 5. The semiconductor device according to claim 1, wherein the first SiGe layer, the second SiGe layer, and the intermediate layer are formed from a single layer integrally provided on one main surface of the substrate. 5. The vertical field effect transistor according to claim 1, wherein one layer is formed to have a columnar portion selectively provided. 6. The vertical field effect transistor according to claim 5, wherein the strained Si layer, the gate insulating film, and the gate electrode are formed so as to surround a side wall of the columnar portion. 7. A substrate having one main surface, and a first conductive type first Si provided on one main surface of the substrate.
A Ge layer, an intermediate layer selectively formed on the first SiGe layer and made of a material having a different lattice constant from Si electrically separated from the first SiGe layer; A second SiGe layer of one conductivity type separated from the first SiGe layer and electrically separated from the intermediate layer; and a second SiGe layer including the surface of the intermediate layer and the second SiGe layer. SiGe laminated on the surface reaching the SiGe layer of
A layer, a strained Si layer having tensile strain laminated on the third SiGe layer, a gate insulating film provided on the strained Si layer, and the first and second SiGe layers separated from each other. A vertical field-effect transistor, comprising: a gate electrode formed via the gate insulating film at a position corresponding to the region. 8. The first SiGe layer and the second SiGe layer.
The vertical field-effect transistor according to claim 7, wherein the layer and the third SiGe layer have a lattice strain relaxed. 9. The semiconductor device according to claim 1, wherein the first SiGe layer has a flat portion and a protrusion protruding in a direction perpendicular to the one main surface, and the intermediate layer is formed on the protrusion. 9. The vertical field-effect transistor according to claim 7, wherein: 10. The vertical field effect transistor according to claim 7, wherein said intermediate layer is an insulating layer. 11. The first SiGe layer and the second SiGe layer.
The layer and the intermediate layer are formed from a single layer integrally provided on one main surface of the substrate, and the single layer is formed to have selectively provided columnar portions. The vertical field-effect transistor according to claim 7, wherein: 12. The semiconductor device according to claim 11, wherein said strained Si layer, gate insulating film, and gate electrode are formed so as to surround a side wall of said columnar portion. 13. An insulating layer for separation is interposed between said substrate and said first SiGe layer, and is electrically connected to said first SGe layer.
13. The vertical field effect transistor according to claim 1, wherein an iGe layer is separated from the substrate. 14. A step of preparing a substrate having one main surface, a step of forming a first SiGe layer of one conductivity type on the one main surface, and a step of forming a first conductivity type SiGe layer on the first SiGe layer. A step of forming a second SiGe layer; a step of forming a third SiGe layer of one conductivity type on the second SiGe layer; and selectively forming the first to third SiGe layers. Removing and forming a columnar portion of the stacked structure of the first to third SiGe layers extending in a direction intersecting one main surface of the substrate; and forming a Si layer on a side wall surface of the columnar portion. Stacking and forming a strained Si layer having a tensile strain, forming a gate insulating film on the strained Si layer, and corresponding to the separated portions of the first and third SiGe layers. Forming a gate electrode via the gate insulating film. A method for manufacturing a vertical field effect transistor, comprising: 15. A step of preparing a substrate having one main surface, a step of forming a first SiGe layer of one conductivity type on the one main surface, an upper surface of the first SiGe layer, and an upper surface thereof Forming an insulating layer that electrically separates the first SiGe layer into an upper layer and a lower layer at a position distant from the bottom surface facing the substrate; and selectively forming an upper layer, a lower layer, and an insulating layer of the first SiGe layer. Removed, extended in a direction intersecting one main surface of the substrate,
Forming a columnar portion of the stacked structure of the first SiGe layer and the insulating layer; forming a second SiGe layer on the side wall surface of the columnar portion; and forming a Si layer on the second SiGe layer surface. Stacking and forming a strained Si layer having tensile strain; and forming a gate insulating film on the strained Si layer along the columnar portion side wall between the upper and lower layers of the first SiGe layer. Forming a gate electrode on the gate insulating film. 16. The method according to claim 14, wherein the first SiGe layer is formed on the substrate with an insulating layer interposed therebetween.