JP2004140350A - Capacitor, wiring board, decoupling circuit and high frequency circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a capacitor realizing low ESL and high capacity.
SOLUTION: A first conductor layer 3 is provided on one main surface of a dielectric layer 2 and a second conductor layer 4 is provided on the other main surface of the dielectric layer 2, and in a thickness direction of the dielectric layer 2, The first through conductor 5 separated from the second conductor layer 4 by the non-conductor formation region 13 and connected to the first conductor layer 3, and the second conductor layer separated from the first conductor layer 3 by the non-conductor formation region 14 4 is formed, and the first through conductor 5 and the second through conductor 6 are exposed on the outermost surface of the dielectric layer 2 in the capacitor 10. 5 and the second through conductors 6 are alternately gathered in a lattice shape to form a through conductor group G.
[Selection diagram] Fig. 1

Description

The present invention relates to a capacitor, a wiring board, a decoupling circuit, and a high-frequency circuit, and particularly to a capacitor that can be advantageously applied in a high-frequency region, and a wiring board, a decoupling circuit, and a high-frequency circuit configured using the capacitor. It concerns the circuit.

(4) A multilayer capacitor will be described as an example of a typical capacitor.

In an equivalent circuit using a multilayer capacitor, when the capacitance of the capacitor is C and the equivalent series inductance (ESL) is L, the resonance frequency (f ₀ ) is f ₀ = 1 / [2π × (L × C) expressed in relation ^1/2], in the frequency region higher than the resonance frequency (f _0), it is known that the function of the capacitor is lost. That is, in order to maintain the capacitance (C) equal to or higher than a certain value, it is necessary to reduce ESL (L) as much as possible. That is, when the ESL is low, the resonance frequency (f ₀ ) is high, and it can be used in a higher frequency range. For this reason, in order to use the multilayer capacitor in the microwave region, a capacitor having a lower ESL is required.

Also, a multilayer capacitor which is used to supply power to an MPU chip of a micro processing unit (MPU) such as a workstation or a personal computer, and which is usually connected on a wiring board as a decoupling capacitor,
With the recent increase in speed and frequency of MPUs, lower ESL is required.

Here, a conventional multilayer capacitor will be described with reference to FIGS. (A) is a schematic diagram showing an overlapping state of the first and second conductor layers, and (b) is a cross-sectional view taken along line XX of (a).

In the conventional multilayer capacitor 50 shown in the figure, a first conductor layer 53 is formed on one main surface of a dielectric layer 52, and a second conductor layer 54 is formed on the other main surface, and a plurality of these dielectric layers 52 are laminated. Also, first and second through conductors 55 and 56 for connecting the first and second conductor layers 53 and 54 to each other are formed in the thickness direction of these dielectric layers 52, respectively.
The laminate 51 is configured. Here, the first and second through conductors 55 and 56 are exposed on one outermost surface of the multilayer body 51 and connected to the first and second connection terminals 57 and 58, respectively, to configure the multilayer capacitor 50. ing. Furthermore, in the first and second conductor layers 53 and 54, first and second non-conductor formation regions 63 and 64 that are not connected to the second and first through conductors 56 and 55, respectively, are formed.

The first and second through conductors 55 and 56 are alternately dispersed in a grid pattern over the entire area of the first and second conductor layers 53 and 54.

According to the multilayer capacitor 50, the capacitance is generated mainly in the portion surrounded by the first and second through conductors 55 and 56 in the first and second conductor layers 53 and 54 (Patent) References 1 to 4).
JP-A-7-201651 (page 3-5, FIG. 1-5) JP-A-11-204372 (page 4-6, FIG. 1-4) JP 2001-148324 A (page 4-7, FIG. 1-6) JP 2001-148325 A (page 5-7, FIG. 1-9)

However, according to the multilayer capacitor 50, to reduce the ESL, a method of increasing the number of the first and second through conductors 55 and 56 can be considered. Since the areas of the non-conductor forming regions 63 and 64 in the 53 and 54 increase, there is a problem that the capacitance of the multilayer capacitor 50 decreases.

Further, according to the multilayer capacitor 50, since the first conductor layer 53 and the second non-conductor formation region 64, or the portion where the second conductor layer 54 and the first non-conductor formation region 63 overlap, no capacitance is generated. However, there is a limit in increasing the capacitance of the multilayer capacitor 50.

The present invention has been devised in view of the above-mentioned problems, and an object of the present invention is to provide a capacitor which realizes low ESL and high capacitance.

Another object of the present invention is to provide a wiring board, a decoupling circuit, and a high-frequency circuit configured using the above-described capacitors.

In the capacitor of the present invention, the first conductor layer is provided on one main surface of the dielectric layer, and the second conductor layer is provided on the other main surface of the dielectric layer. A plurality of first through conductors separated by a second conductor layer and a second non-conductor formation region and connected to the first conductor layer; separated by the first conductor layer and the first non-conductor formation region; In a capacitor formed with a plurality of second through conductors connected to the second conductor layer,
The plurality of first and second through conductors are alternately arranged in a grid pattern.

Further, the distance between the centers of the first through conductor and the second through conductor that are adjacent to each other is P, and the center of the first through conductor and the second non-conductor formation region are located on a straight line connecting the centers. When the distance from the periphery is m2 and the distance between the center of the second through conductor and the periphery of the first non-conductor formation region is m1, the relationship of P ≦ m1 + m2 is satisfied.

The distance between the centers of the first through conductor and the second through conductor that are adjacent to each other is P, the radius of the non-conductor formation region formed in the first conductor layer is m2, and the second conductor layer is When the radius of the non-conductor formation region formed in (1) is m1, the relationship of P ≦ m1 + m2 is satisfied.

Further, the first conductor layer and the second conductor are arranged around the centrally arranged first through conductor and the second through conductor with a width equal to or larger than the distance P between the centers of the first through conductor and the second through conductor. It is characterized in that two conductor layers are present.

The present invention is also applicable to a wiring board having the above-described capacitor.

Furthermore, the capacitor according to the present invention is advantageously used as a decoupling capacitor connected to a power supply circuit for an MPU chip provided in the MPU.

The present invention can also be applied to a high-frequency circuit including the above-described capacitor.

As described above, according to the capacitor of the present invention, the first through conductors and the second through conductors are alternately gathered in a lattice form to form a group of through conductors. Since the flowing distance is short, the self-inductance component due to the magnetic flux induced by the current is low. Therefore, the equivalent series inductance (ESL) of the entire capacitor can be reduced. Further, since it is not necessary to increase the number of the first and second through conductors in order to lower the ESL, it is possible to realize a higher capacitance of the capacitor.

た め Further, since there is no region where capacitance occurs between the first through conductor and the second through conductor that are adjacent to each other, almost no current flows from the first through conductor to the other, for example, the second through conductor. As a result, the self-inductance component caused by the magnetic flux induced by the current becomes extremely low, and the ESL of the entire capacitor can be further reduced. In addition, since the non-conductor formation regions that do not contribute to the formation of the capacitance overlap with each other, the capacitance region is relatively increased from the viewpoint of the entire capacitor, so that a higher capacitance of the capacitor can be realized.

Furthermore, the first through conductor and the second through conductor that are collectively arranged, that is, around the group of through conductors, the first through conductor and the second through conductor have a width equal to or greater than the center-to-center distance P between the first and second through conductors. Since the conductor layer and the second conductor layer are present, the amount of current flowing through the first conductor layer and the second conductor layer in the capacitance region increases, and this also makes the ESL of the entire capacitor more effective. Can be lowered. In addition, since a capacitance is generated around the group of through conductors, an applied electric field can be increased, which can also increase the capacitance of the capacitor.

(4) The present invention can be applied to a wiring board provided with a capacitor, a decoupling capacitor connected to a power supply circuit for an MPU chip provided in an MPU, and further to a high-frequency circuit.

Hereinafter, the capacitor, wiring board, decoupling circuit, and high-frequency circuit of the present invention will be described in detail with reference to the drawings.

FIGS. 1A and 1B are diagrams showing a multilayer capacitor as an example of the capacitor of the present invention, in which FIG. 1A is a schematic diagram showing an overlapping state of first and second conductor layers, and FIG. 1B is an XX line of FIG. It is sectional drawing.

In the drawing, 10 is a multilayer capacitor, 2 is a dielectric layer, 3 and 4 are first and second conductor layers (internal electrode layers), 5 and 6 are first and second through conductors (via hole conductors), 7, 8 Denotes first and second connection terminals.

As shown in the figure, the multilayer capacitor 10 has a first conductor layer 3 formed on one main surface of a dielectric layer 2 and a second conductor layer 4 formed on the other main surface, and a plurality of these dielectric layers 2 are laminated. In addition, a plurality of first and second through conductors 5 and 6 for connecting the first and second conductor layers 3 and 4 to each other are formed in the thickness direction of these dielectric layers 2 to form a laminate. 1 is configured. Here, the plurality of first and second through conductors 5 and 6 are exposed on one outermost surface of the multilayer body 1 and connected to the first and second connection terminals 7 and 8, respectively, so that the multilayer capacitor 10 is formed. It is configured. Further, a plurality of first and second non-conductor formation regions 13 and 14 which are not connected to the plurality of second and first through conductors 6 and 5 are formed in the first and second conductor layers 3 and 4, respectively. I have.

(4) The plurality of first and second through conductors 5 and 6 are alternately arranged in a grid in a substantially central region of the first and second conductor layers 3 and 4.

The dielectric layer 2 is made of a non-reducing dielectric material containing barium titanate as a main component, and a dielectric material containing a glass component. Is configured. The shape, thickness, and number of layers of the dielectric layer 2 can be arbitrarily changed according to the capacitance value. The first and second conductor layers 3 and 4 are made of a material mainly containing Ni, Cu, or an alloy thereof, and have a thickness of 1 to 2 μm.

半 田 The first and second connection terminals 7 and 8 use solder bumps, solder balls, or the like.

特 徴 A characteristic of the present invention is that the first through conductors 5 and the second through conductors 6 are alternately gathered in a lattice form to form a through conductor group G as described above.

{Circle around (1)} There is no region where capacitance occurs between the first through conductor 5 and the second through conductor 6 adjacent to each other. Specifically, the distance between the center of the adjacent first through conductor 5 and the center of the second through conductor 6 is P, and the radii of the first and second non-conductor forming regions 13 and 14 are m1 and m2 (general). Specifically, when m1 = m2), the relationship of P ≦ m1 + m2 is satisfied. Here, in order to prevent an increase in equivalent series resistance (ESR), when the radii of the first and second through conductors 3 and 4 are r1 and r2, respectively, the relationship of r1 + m2 ≦ P or r2 + m1 ≦ P It is desirable to be satisfied. In order to realize a high capacity, it is desirable that the relations P> 1.4 m1 and P> 1.4 m2 be satisfied.

Further, the first through conductor 3, the second through conductor 4, and the non-conductor formation regions 13, 14 are formed around the through conductor group G in the first conductor layer 3 and the second conductor layer 4 with a width d equal to or more than the interval P. And the capacitance region A without the pattern is formed. Preferably, d ≧ 1.4P.

Next, a method for manufacturing the multilayer capacitor 10 of the present invention will be described. Note that, in the drawings, each symbol is not distinguished before and after firing.

{Circle over (1)} First, the conductor films 3 and 4 to be the first and second conductor layers are formed on the ceramic green sheet 2 to be the dielectric layer by printing and drying a conductive paste. At this time, the first and second non-conductor formation regions 13 and 14 are also formed. The dielectric layer 2 may be made of another ceramic material having a perovskite structure or an organic ferroelectric material.

Next, a required number of the green sheets 2 on which the conductor films 3 and 4 are formed are alternately stacked to form a large laminate from which the laminate 1 is extracted.

(4) Next, through holes are formed through the conductor films 3 and 4 and the ceramic green sheet 2 on the main surface of the large-sized laminate by laser irradiation or a punching method using micro drilling or punching.

Next, by filling the through-holes with the same conductive paste as the conductive paste used for the conductive layers 3 and 4, the conductor portions 5 and 6 serving as the first and second through conductors are formed.

The ceramic green sheet 2 serving as a dielectric layer is provided with through holes in advance by a punching method using a micro drill or punching, and the conductive layers 3 and 4 are formed on the ceramic green sheet 2 by a screen printing method. The conductive portions 5 and 6 may be formed and then laminated by filling the through holes with a conductive paste at the same time as printing the conductive film.

Next, the large-sized laminate is cut by a press-cutting blade process, a dicing method, or the like, to obtain a laminate 1 in an unfired state.

Next, the laminate 1 in the unfired state is fired after the binder removal process, and the first and second conductor layers 3 and 4 and the first and second through conductors 5 and 6 are formed therein. Thus, the laminated body 1 having the first and second through conductors 5 and 6 exposed on one main surface is obtained.

At this time, since the surfaces of the first and second penetrating conductors 5 and 6 exposed on one main surface of the laminate 1 are oxidized, the oxide film is removed by surface polishing.

Next, Ni plating and Sn plating are formed on the exposed portions of the first and second through conductors 5 and 6.

Next, by forming a solder to be the first and second connection terminals 7 and 8 by a method of screen printing a solder paste or a method of mounting a solder ball after applying a flux, a reflow process is performed. First and second connection terminals 7 and 8 are formed.

に し て Thus, a multilayer capacitor 10 as shown in FIG. 1 is obtained.

The present invention is not limited to the above embodiments, and various changes and improvements can be made without departing from the spirit of the present invention.

FIG. 2 is a schematic view showing another embodiment of the multilayer capacitor 10 of the present invention. As shown in the drawing, the through conductor group G may be provided in the peripheral portion of the dielectric layer 2 according to the required arrangement of the first and second connection terminals 7 and 8 at the time of mounting. At this time, it is desirable that d ≧ P, preferably d ≧ 1.4P.

FIG. 3 is a sectional view showing still another embodiment of the multilayer capacitor 10 of the present invention. As shown, the first and second through conductors 5 and 6 may be exposed on both main surfaces of the laminate 1. Thus, the present multilayer capacitor 10 can be mounted between the IC package and the IC element or inside the IC package.

FIG. 4 is a sectional view showing still another embodiment of the multilayer capacitor 10 of the present invention. As shown in the figure, a first conductor layer 3, a dielectric layer 2, a second conductor layer 4, and a protective layer 12 are sequentially formed on the surface of an insulating substrate 11, and in the thickness direction of the dielectric layer 2, A first through conductor 5 separated from the second conductor layer 4 by the non-conductor formation region 13 and connected to the first conductor layer 3, and a second conductor layer separated from the first conductor layer 3 by the non-conductor formation region 14 4 is formed, and the first through conductor 5 and the second through conductor 6 are exposed on the outermost surface of the dielectric layer 2. As described above, by applying the multilayer capacitor of the present invention to a thin film capacitor, fine processing is possible, so that a further reduction in ESL can be realized.

半径 Also, the radii r1 and r2 of the first and second through conductors and the radii m1 and m2 of the first and second non-conductor forming regions may be equal or different, respectively.

(4) In order to mount the multilayer capacitor 10 stably, a dummy terminal may be formed on one main surface of the multilayer body 1 in a region where the connection terminals 7 and 8 are not formed.

The cross-sectional shape of the first and second through conductors 5 and 6 or the shape of the first and second non-conductor forming regions 13 and 14 is not limited to a substantially circular shape, but may be an arbitrary shape such as an elliptical shape or a polygonal shape. be able to.

FIG. 5 is a cross-sectional view illustrating a structural example of the MPU 20 using the multilayer capacitor 10 of the present invention as a decoupling capacitor.

As shown in the figure, the MPU 20 includes a multilayer wiring board 21 having a cavity 22 on the lower surface side. On the upper surface of the wiring board 21, the MPU chip 40 is surface-mounted. The multilayer capacitor 10 of the present invention, which functions as a decoupling capacitor, is housed in the cavity 22 of the wiring board 21. Further, the wiring board 21 is surface-mounted on the motherboard 31.

電源 A power supply side conductor layer 23 and a ground side conductor layer 24 are formed inside the wiring board 21.

The power-supply-side conductor layer 23 is electrically connected to the first connection terminal 7 of the multilayer capacitor 10 via the power-supply-side through conductor 25, and is also electrically connected to a specific terminal 47 of the MPU chip 40. It is electrically connected to the power supply side conductor land 37 of the motherboard 31.

The ground-side conductor layer 24 is electrically connected to the second connection terminal 8 of the multilayer capacitor 10 via the ground-side through conductor 26, and is also electrically connected to a specific terminal 48 of the MPU chip 40. It is electrically connected to the ground-side conductor land 38 of the motherboard 31.

As described above, since the multilayer capacitor 10 of the present invention has a low ESL, even when it is used as a decoupling capacitor in the MPU 20, it can sufficiently cope with high-speed operation. Further, the present invention can be applied to a wiring board including the multilayer capacitor 10.

In addition, since the multilayer capacitor 10 of the present invention can have a low ESL, the resonance frequency (f ₀ ) becomes high, and it can be used at a higher frequency. From this, it is possible to sufficiently cope with an increase in the frequency of an electronic circuit, and for example, it can be advantageously used as a bypass capacitor or a decoupling capacitor in a high frequency circuit.

The present inventors made the multilayer capacitor 10 of the present invention shown in FIG. 1 and the conventional multilayer capacitor 50 shown in FIG. 6, and measured the capacitance C and the equivalent series inductance L. Here, the dimensions of both the multilayer capacitors 10 and 50 are 3.2 mm × 3.2 mm × 0.85 mm, the number of layers is 120, and the number of the first and second through conductors 3 and 4 is 36 in total. The radius of the first and second through conductors 3 and 4 was r1 = r2 = 0.07 mm, and the radius of the first and second non-conductor formation regions 13 and 14 was m1 = m2 = 0.17 mm. The distance P between the centers of the first and second penetrating conductors 3 and 4 that are close to each other is 0.25 mm for the multilayer capacitor 10 and 0.40 mm for the multilayer capacitor 50. As a result of the measurement, the conventional multilayer capacitor 50 shown in FIG. 5 has C = 7.8 μF and L = 12 pH, whereas the multilayer capacitor 10 of the present invention shown in FIG. 1 has C = 10 μF and L = 7 pH. Was.

Also, in the multilayer capacitor 10 of FIG. 1, when the shortest distance d between the through conductor group G and the outer periphery of the first and second conductor layers 3 and 4 is 0, the ESL is approximately equal to that when d ≧ P. Increased by 15%.

From these results, in the multilayer capacitor 10 of the present invention, the first and second through conductors 5 and 6 are alternately gathered in a lattice shape to form the through conductor group G, and the relationship of P ≦ m1 + m2 is obtained. , And d ≧ P, it was found that low ESL and high capacity can be realized.

According to the capacitor of the present invention, the first through conductors and the second through conductors are alternately gathered in a lattice form to form a group of through conductors. , The self-inductance component due to the magnetic flux induced by the current is reduced. Therefore, the equivalent series inductance (ESL) of the entire capacitor can be reduced. Further, since it is not necessary to increase the number of the first and second through conductors in order to lower the ESL, it is possible to realize a higher capacitance of the capacitor.

た め Further, since there is no region where capacitance occurs between the first through conductor and the second through conductor that are adjacent to each other, almost no current flows from the first through conductor to the other, for example, the second through conductor. As a result, the self-inductance component caused by the magnetic flux induced by the current becomes extremely low, and the ESL of the entire capacitor can be further reduced. In addition, since the non-conductor formation regions that do not contribute to the formation of the capacitance overlap with each other, the capacitance region is relatively increased from the viewpoint of the entire capacitor, so that a higher capacitance of the capacitor can be realized.

Furthermore, the first through conductor and the second through conductor that are collectively arranged, that is, around the group of through conductors, the first through conductor and the second through conductor have a width equal to or greater than the center-to-center distance P between the first and second through conductors. Since the conductor layer and the second conductor layer are present, the amount of current flowing through the first conductor layer and the second conductor layer in the capacitance region increases, and this also makes the ESL of the entire capacitor more effective. Can be lowered. In addition, since a capacitance is generated around the group of through conductors, an applied electric field can be increased, which can also increase the capacitance of the capacitor.

It is a figure which shows the laminated capacitor of this invention, (a) is the schematic which shows the overlapping state of the 1st, 2nd conductor layer, (b) is XX sectional drawing of FIG.1 (a). It is the schematic which shows other embodiment of the laminated capacitor of this invention. FIG. 9 is a cross-sectional view showing still another embodiment of the multilayer capacitor of the present invention. FIG. 9 is a cross-sectional view showing still another embodiment of the multilayer capacitor of the present invention. FIG. 3 is a cross-sectional view illustrating a structural example of an MPU using the multilayer capacitor of the present invention as a decoupling capacitor. It is a figure which shows the conventional laminated capacitor, (a) is the schematic which shows the overlapping state of a 1st, 2nd conductor layer, (b) is XX sectional drawing of FIG.6 (a).

Explanation of reference numerals

Reference Signs List 10 multilayer capacitor 1 multilayer body 2 dielectric layer 3 first conductor layer (internal electrode layer)
4 Second conductor layer (internal electrode layer)
5 First through conductor (via hole conductor)
6 Second through conductor (via hole conductor)
7 First connection terminal 8 Second connection terminal 13 First non-conductor formation area 14 Second non-conductor formation area A Capacitance area G Through conductor group 20 MPU
DESCRIPTION OF SYMBOLS 21 Wiring board 22 Cavity 23 Power supply side conductor layer 24 Ground side conductor layer 25 Power supply side through conductor 26 Ground side through conductor 40 MPU chip 37, 38 Terminal of MPU chip 31 Motherboard

Claims (7)

A first conductor layer is provided on one main surface of the dielectric layer, a second conductor layer is provided on the other main surface of the dielectric layer, and the second conductor layer and the second conductor layer are arranged in the thickness direction of the dielectric layer. (2) a plurality of first through conductors separated by the non-conductor formation region and connected to the first conductor layer; and a plurality of first through conductors separated by the first conductor layer and the first non-conductor formation region and connected to the second conductor layer. In a capacitor formed with a plurality of second through conductors to be connected,
The capacitor, wherein the plurality of first and second through conductors are alternately arranged in a grid pattern. The distance between the centers of the first through conductor and the second through conductor that are adjacent to each other is P, and on a straight line connecting the centers, the center of the first through conductor and the periphery of the second non-conductor formation region 2. The capacitor according to claim 1, wherein a relationship of P ≦ m1 + m2 is satisfied, where m2 is an interval of m2, and m1 is an interval between the center of the second through conductor and the periphery of the first non-conductor formation region. . The distance between the centers of the first through conductor and the second through conductor that are adjacent to each other is P, the radius of the non-conductor formation region formed in the first conductor layer is m2, and the second conductor layer is formed in the second conductor layer. 2. The capacitor according to claim 1, wherein the relationship of P ≦ m1 + m2 is satisfied when the radius of the non-conductor forming region is m1. The first conductive layer and the second conductive layer are arranged around the centrally arranged first through conductor and the second through conductor with a width equal to or larger than the distance P between the centers of the first through conductor and the second through conductor. 4. The capacitor according to claim 1, wherein a conductor layer is present. A wiring board comprising the capacitor according to claim 1. A decoupling circuit comprising the capacitor according to claim 1. A high-frequency circuit comprising the capacitor according to claim 1.

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