JP2004039208A - Static random access memory cell of two transistor and its driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a SRAM cell of two transistors in which the magnitude of a cell is small, a manufacturing cost is low, charge voltage is low, and a standby current is low. <P>SOLUTION: This memory is a SRAM of two transistors and its driving method, the SRAM cell has a first transistor, a second transistor, a first capacitor, and a second capacitor. The first transistor has a first terminal, a second terminal, and a gate terminal. The first terminal of the first transistor is connected to a first bit line, the gate terminal of the first transistor is connected to a word line. The first capacitor has a first electrode terminal and a second electrode terminal. The second electrode terminal of the first capacitor is connected to a cell substrate voltage. The second transistor has a first terminal, a second terminal, and a gate terminal. <P>COPYRIGHT: (C)2004,JPO

Description

TECHNICAL FIELD OF THE INVENTION
[0001] This application seeks priority of Taiwan Application No. 91108949 filed on April 30, 2002.
The present invention relates to a static random access memory (SRAM) cell and a driving method thereof, and more particularly, to a two-transistor SRAM cell and a driving method thereof.
[Prior art and its problems]
[0002] A random access memory (RAM) is a memory that disappears when the power is turned off. There are two types of RAM memory. One is a static random access memory (SRAM), which stores data depending on the dielectric state of a transistor in a memory cell. Another type is a dynamic random access memory (DRAM), which stores digital signals according to the state of charge of a capacitor in a memory cell. The present invention relates to a static random access memory (SRAM).
A conventional SRAM cell usually has six transistors. Reading and writing of data by "0" and "1" are performed as follows. In the write state, the ON or OFF state of the dielectric state for the six transistors determines “0” or “1” of the write data. The two bit lines to which the two write transistors are individually connected have a potential difference between each other due to the two write transistor dielectric states. Therefore, at the time of reading, "0" and "1" are distinguished by using this potential difference. Further, in the conventional method of driving the SRAM cell to read or write "0" and "1", the transistor is insulated using one capacitor and one transistor (1-T) of the DRAM. In some cases, it is checked whether or not the amount of charge stored in the capacitor is determined. As a result, data "0" or "1" is written to and read from the DRAM cell by the amount of charge of the capacitor determined by the dielectric state of the transistor.
[0004] However, both conventional SRAMs have disadvantages. In the case of a memory cell having six transistors, the degree of integration of the memory cell itself is obviously low. With current production technology, the size of this six-transistor SRAM cell is ten to sixteen times that of a DRAM cell, resulting in a large occupation area and high manufacturing costs. In addition, production techniques are constantly being improved, increasing the number of devices per unit area. This may cause a can-not-turn-off problem in the six-transistor SRAM due to the total leakage current I _off (similar to the standby current). In contrast, when using a one-transistor SRAM cell, the size of the cell can be much smaller. However, a drawback of the conventional one-transistor SRAM cell is that when the capacitor can be charged more, the capacitor has a high ability to prevent the problem of leakage of the stored charge from occurring, so that the data can be held safely. For this reason, a higher charge voltage (voltage obtained by adding the threshold voltage of the transistor to the power supply voltage) must be used.
[Means to solve the problem]
The present invention provides a two transistor SRAM cell. Compared to a conventional SRAM cell or an SRAM cell using a DRAM, the two-transistor SRAM cell has advantages in that the cell size is small, the production cost is low, the charge voltage is low, and the standby current is low. Therefore, the two-transistor SRAM cell according to the present invention can be replaced with the SRAM cell currently used in the industry.
A two-transistor SRAM cell provided by the present invention has a first transistor, a second transistor, a first capacitor, and a second capacitor. The first transistor has a first terminal, a second terminal, and a gate terminal. The first terminal is connected to a first bit line, and the gate terminal is connected to a word line. The first capacitor has a first electrode terminal and a second electrode terminal, the first electrode terminal is connected to the second terminal of the first transistor, and the second electrode terminal is connected to the substrate voltage of the SRAM cell. . The second transistor also has a first terminal, a second terminal, and a gate terminal, and the gate terminal is connected to a word line. Similarly, the second capacitor also has a first electrode terminal and a second electrode terminal, the first electrode terminal being connected to the second terminal of the second transistor, and the second electrode terminal being connected to the substrate voltage.
The present invention also provides a method for driving a two transistor SRAM cell. In this case, the SRAM cell includes a first DRAM cell and a second DRAM cell, and the first DRAM cell and the second DRAM cell have a common word line and a common cell substrate voltage. Each of the two DRAM cells has a first bit line and a second bit line. The driving method includes reading and writing of data. When writing bit data to a cell, the word line voltage changes from the cell substrate voltage to the power supply voltage. Based on the value of the data, a cell substrate voltage is applied to the first bit line and a power supply voltage is applied to the second bit line. Thereafter, the voltage of the bit line changes from the power supply voltage to the cell substrate voltage, and the write operation is completed. When reading data, the first bit line and the second bit line are precharged to the power supply voltage state, and the word line voltage changes from the cell substrate voltage to the power supply voltage. The data stored in the SRAM cell is determined based on whether the voltages of the first bit line and the second bit line have dropped. After detecting the data stored in the SRAM, the bit line whose voltage has dropped falls to the cell substrate voltage. Finally, the word line voltage changes from the power supply voltage to the cell substrate voltage, returning the SRAM cell to the state before reading.
In summary, with the present invention, using two DRAMs, the "write" value is based on the charge voltage difference between the two capacitors of the two DRAM cells, and the "read" value is after the bit line has been precharged. The determination is made based on whether one of the pair of bit lines is pulled down by the charge voltage of the capacitor. Therefore, the present invention provides an SRAM cell with small size, low charge voltage, low standby current, low production cost, and other advantages. The two-transistor SRAM cell can be replaced with a conventionally used SRAM cell.
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a simplified circuit diagram of an SRAM cell according to a preferred embodiment of the present invention. The SRAM cell 100 includes NMOS transistors 101 and 105 and capacitors 103 and 107. The gate terminals of the NMOS transistors 101 and 105 are both connected to the word line WL. The first terminals of the NMOS transistors 101 and 105 are connected to the first bit line BL and the second bit line BLB, respectively. The second terminals of the NMOS transistors 101 and 105 are both connected to the SRAM cell substrate. Further, one end of the first bit line BL and one end of the second bit line BLB are connected to a sense amplifier.
In this preferred embodiment, the method of writing and reading cell 100 is described below. When the cell 100 is in the write mode, the word line voltage changes from the ground voltage GND to VDD which is the power supply of the SRAM (if the DRAM is designed based on the word line, the word line must be changed to VDD + threshold voltage of the DRAM transistor). ). Then, the voltages of the first bit line BL and the second bit line BLB are supplied at VDD or GND based on the data of “0” or “1” to be written. For example, referring simultaneously to FIGS. 1 and 2, FIG. 2 shows a timing diagram in a write mode based on an SRAM cell according to the present invention. When the data to be written is “1”, the WL voltage is raised from GND to VDD, the BL voltage is raised from GND to VDD, and the BLB voltage is lowered from VDD to GND. In this state, it is obvious to those skilled in the art that the NMOS transistor 101 is in the dielectric state (ON) and the capacitor 103 starts charging. Based on the voltage change of the first bit line BL, the charging voltage of the capacitor 103 (the voltage of the first storage node SN1) increases from the ground voltage to the power supply voltage VDD minus the initial voltage VTN of the NMOS 101 (VDD-VTN). The NMOS transistor 105 is also switched, and the charging voltage of the capacitor 107 (the voltage of the second storage node SN2) is reduced from VDD-VTN to the ground voltage based on the voltage change of the second bit line BLB. As for the word line, after the WL voltage is raised to the power supply voltage VDD for a while, the voltage is again lowered from VDD to the ground voltage GND, and the NMOS transistors 101 and 105 are cut off. Protect. At this point, the above-described write operation of the cell 100 is completed. Similarly, the reading operation for the cell 100 can be understood.
When the cell 100 is in the read mode, the voltages of the first bit line BL and the second bit line BLB are precharged so that both become equal to the power supply voltage. The voltage of the word line WL is switched from the ground voltage GND to the power supply voltage VDD. Referring to FIGS. 1 and 2, FIG. 3 shows a timing diagram when the SRAM according to the present invention is reading "1". When the data to be read is "1", the voltages of the first bit line BL and the second bit line BLB are controlled by the sense amplifier. When the sense amplifier is operating (the detectable voltage is the ground voltage GND), both of the voltages BL and BLB are precharged and balanced with the power supply voltage VDD. Subsequently, the voltage of the word line WL is switched from the ground voltage GND to the power supply voltage VDD. At this point, the NMOS transistors 101 and 105 are all "ON" and the voltage of the first bit line BL is still the power supply voltage VDD because the voltage of the first storage node SN1 is VDD-VTN. On the other hand, since the voltage of the second storage node SN2 is the ground voltage GND and the second bit line BLB has a uniformly distributed charge, the capacitor 107 starts receiving charge from the second bit line BLB during the charging process. Then, the voltage of the second bit line BLB is pulled down slightly lower than VDD. Finally, the final voltage stored on the second storage node SN2 remains slightly below VDD-VTN because the second storage node SN2 is not sufficiently precharged.
While the voltage of the first storage node SN1 is VDD-VTN and the voltage of the second storage node SN2 is slightly lower than VDD-VTN, the sense amplifier changes the voltages of the first bit line BL and the second bit line BLB. Can be detected. By reading the difference between the voltage of the first bit line BL (power supply voltage) and the voltage of the second bit line BLB (slightly lower than the power supply voltage), the sense amplifier determines whether the data stored in the cell 100 is "1". to decide. After the sense amplifier determines that the data stored in the cell 100 is "1", the sense amplifier stops operating. The detectable voltage changes from the ground voltage GND to the power supply voltage VDD. At the same time, the voltage of the first bit line is maintained at the power supply voltage VDD, and the voltage of the second bit line is reduced to the ground voltage GND. Therefore, the charge voltage stored in the capacitor 103 is maintained at VDD-VTN, and the charge voltage stored in the capacitor 107 is reduced to the ground voltage GND. That is, the voltages of the first storage node SN1 and the second storage node SN2 are returned to the original voltages before reading. Finally, the voltage of the word line WL is switched from the power supply voltage VDD to the ground voltage GND. Then, the NMOS transistors 101 and 105 are shut off, the charge stored in the capacitors 103 and 107 is maintained, and the voltages of the first storage node SN1 and the second storage node SN2 are maintained as before reading. As described above, the operation of reading “1” in the cell 100 is completed. The operation of reading "0" of the cell 100 is similarly understood. In addition, when the voltage of the word line WL is switched to the ground voltage GND, the sense amplifier operates. Subsequently, the voltages of the first bit line BL and the second bit line BLB are pre-charged and balanced by the power supply voltage VDD, and the data stored in the cell 100 at the next time is read.
In conclusion, the present invention provides an SRAM cell using two DRAMs and a driving method thereof. In the present invention, the difference between the charge voltages stored in the capacitors of the cells is used as a reference during writing and reading data. Therefore, a two-transistor SRAM cell different from the conventional SRAM device and a driving method thereof are provided. This has the advantage that the cell size is small and the charge voltage is low, and the number of devices in the cell is small, the overall leakage current is small, the standby current is small, and the production cost is low. Thus, the SRAM according to the present invention can replace the one currently used in the industry.
It will be apparent to those skilled in the art that various modifications and variations can be made in the structure of the present invention without departing from the scope or spirit of the invention. Accordingly, it is intended that the present invention cover the modifications and variations of the present invention when they cover the claims and equivalents.
By reading the detailed description of the above embodiments, the present invention can be fully understood. The accompanying drawings are numbered and are as follows:
[Brief description of the drawings]
FIG. 1 is a simplified circuit diagram of an SRAM cell according to a preferred embodiment of the present invention.
FIG. 2 is a timing diagram when writing “1” based on the SRAM cell of the preferred embodiment according to the present invention;
FIG. 3 is a timing diagram when “1” is read based on the SRAM cell of the preferred embodiment according to the present invention;
[Explanation of symbols]
100 SRAM cell 101 NMOS transistor 103 Capacitor 105 NMOS transistor 107 Capacitor BL First bit line BLB Second bit line I _off leak current SN1 First storage node SN2 Second storage node VDD Power supply voltage VTN Initial voltage WL Word line

Claims (13)

A first transistor having a first terminal, a second terminal, and a gate terminal, wherein the first terminal is connected to the first bit line, and the gate terminal is connected to the word line;
A first capacitor having a first terminal and a second terminal, the first terminal connected to the second terminal of the first transistor, and the second terminal connected to the cell substrate voltage of the SRAM cell;
A second transistor having a first terminal, a second terminal, and a gate terminal, wherein the first terminal is connected to the second bit line, and the gate terminal is connected to the word line;
A second capacitor having a first terminal and a second terminal, wherein the first terminal is connected to the second terminal of the second transistor, and the second terminal is connected to the cell substrate voltage,
A two-transistor static random access memory (SRAM) cell having: 2. The two-transistor SRAM cell according to claim 1, wherein the first transistor is an NMOS transistor. The two-transistor SRAM cell according to claim 1, wherein the second transistor is an NMOS transistor. The first and second DRAM cells include a common word line and a common cell substrate voltage, and each of the first and second DRAM cells has a first bit line and a second DRAM cell. A method for driving a two transistor SRAM cell having a second bit line, comprising:
When writing data to the SRAM cell, the word line voltage is switched from the cell substrate voltage to the power supply voltage,
Based on the value of the data, respectively, supply the cell substrate voltage to the first bit line, supply the power supply voltage to the second bit line,
A method of driving a two-transistor static random access memory (SRAM) cell having a method of switching a word line voltage from a power supply voltage to a cell substrate voltage. 5. The method of driving a two-transistor SRAM cell according to claim 4, wherein the cell substrate voltage is a ground voltage. 5. The method according to claim 4, wherein when the data to be written is 1, the voltage of the first bit line is raised from the cell substrate voltage to the power supply voltage, and the voltage of the second bit line is lowered from the power supply voltage to the cell substrate voltage. A method for driving an SRAM cell having a single transistor. 5. The method according to claim 4, wherein when data to be written is 0, the voltage of the first bit line is reduced from the cell power supply voltage to the cell substrate voltage, and the voltage of the second bit line is raised from the cell substrate voltage to the power supply voltage. A method for driving a two-transistor SRAM cell. 7. The driving of a two-transistor SRAM cell according to claim 6, wherein the voltage stored in the first capacitor of the first DRAM cell is a power supply voltage minus a threshold voltage of the first transistor of the first DRAM cell. Method. 7. The method of driving a two-transistor SRAM cell according to claim 6, wherein the voltage stored in the second capacitor of the second DRAM cell is a cell substrate voltage. 10. The method of driving a two-transistor SRAM cell according to claim 9, wherein the cell substrate voltage is a ground voltage. A first dynamic random access memory (DRAM) cell and a second DRAM cell, wherein the first and second DRAM cells have a common word line and a common cell substrate voltage, and the first DRAM cell has a first bit. In a method for driving a two-transistor static random access memory (SRAM), wherein the line has a second bit line in the second DRAM cell,
When reading the value of the data stored in the SRAM cell, the voltage of the first bit line and the voltage of the second bit line are precharged to the power supply voltage,
Switching the word line voltage from the cell substrate voltage to the power supply voltage,
The value of the data in the SRAM is determined based on whether any of the voltage of the first bit line and the voltage of the second bit line has been reduced to the set level,
After the step of determining the value of the data, the voltage of the first bit line and the voltage of the second bit line are reduced to the cell substrate voltage,
A method for driving a two-transistor SRAM cell, comprising a step of switching a word line voltage from a power supply voltage to a cell substrate voltage. 12. The method of driving a two-transistor SRAM cell according to claim 11, wherein the cell substrate voltage is a ground voltage. There are a first dynamic random access memory (DRAM) cell and a second DRAM, the first DRAM cell and the second DRAM cell have a common word line and a common cell substrate voltage, and the first DRAM cell has a first DRAM cell. A method for driving a two transistor static random access memory (SRAM) cell having a bit line and a second DRAM having a second bit line,
When data is written to the SRAM cell,
Switching the word line voltage from the cell substrate voltage to the power supply voltage,
According to the value of the data, the cell substrate voltage is supplied to the first bit line and the power supply voltage is supplied to the second bit line,
Switch the word line voltage from the power supply voltage to the cell substrate voltage,
When the SRAM cell reads the write data,
Pre-charging the voltage of the first bit line and the voltage of the second bit line so as to be balanced with the power supply voltage level,
Switching the word line voltage from the cell substrate voltage to the power supply voltage,
Determining the value of the data stored in the SRAM cell by determining whether one of the first bit line voltage and the second bit line voltage is reduced to a set level;
After the step of determining data, the voltage of the first bit line and the voltage of the second bit line are reduced to the cell substrate voltage,
A method for driving a two-transistor SRAM cell, comprising a step of switching a word line voltage from a power supply voltage to a cell substrate voltage.

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