JP2004014711A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A semiconductor element and a method for manufacturing the semiconductor element, which can reduce a writing time without shortening a memory retention time.
The semiconductor element has a structure in which a first tunnel insulating film, a second tunnel insulating film, a charge storage layer, a blocking insulating film, and a gate electrode are stacked on a semiconductor substrate on which a source and a drain are formed. , the first tunnel insulating layer is SiO _x, by the second tunnel insulating layer and SiO _2, performs prolonged shortened and memory maintaining time of write time by using a diode effect.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device that operates as a nonvolatile memory device and a method for manufacturing the semiconductor device.
[0002]
[Prior art]
Conventionally, as a semiconductor nonvolatile memory element, a MOSFET (metal-oxide semiconductor field effect transistor) having a floating gate layer has been used. In order to reduce the bit cost, high integration of these elements is required. However, since this type of element has a floating gate layer, it is becoming difficult to miniaturize the element. Therefore, recently, a MONOS (metal oxide nitride oxide semiconductor) type nonvolatile memory element has begun to be put into practical use.
[0003]
FIG. 10 shows the structure of this MONOS type nonvolatile memory element. The structure of the MONOS type nonvolatile memory element is such that a tunnel insulating film 55 (SiO ₂ ) is formed on a semiconductor substrate 51 (Si) on which a source region 52 and a drain region 53 are formed, and charge is stored on the tunnel insulating film 55. It has a structure in which a layer 56 (SiN _x ) is formed, a blocking insulating film 57 (SiO ₂ ) is formed on the charge storage layer 56, and a gate electrode 58 is formed on the blocking insulating film 57. Since the charge accumulation in the MONOS type structure is carried out in the trap of thin SiN _x, it is possible to perform miniaturization of elements, like the conventional MOSFET.
[0004]
Important characteristics of the nonvolatile memory element include a write time and a retention time. The MONOS element is suitable for miniaturization, but generally has a feature that the writing time is long. Therefore, if the tunnel insulating film (SiO ₂ ) is made thinner in order to shorten the writing time, electrons can easily escape from the SiN _x layer, which is the charge storage layer, by the reverse tunnel from the SiN _x layer to the Si substrate after the writing applied voltage is removed. The maintenance time is shortened. In general terms, there is a trade-off between the writing time and the storage maintaining time, and this is an obstacle to widespread practical use of the MONOS type nonvolatile memory element.
[0005]
[Problems to be solved by the invention]
The present invention has been made in view of such a problem, and an object of the present invention is to provide a semiconductor element and a method of manufacturing the semiconductor element, which can shorten a writing time without shortening a memory retention time.
[0006]
[Means for Solving the Problems]
In order to solve the above problem, a semiconductor device of the present invention has a charge storage layer for storing data by storing carriers on a semiconductor substrate, and the semiconductor device is provided between the semiconductor substrate and the charge storage layer. It is characterized by having an anisotropic tunnel layer in which injection of electrons from the substrate side to the charge storage layer side is easier than injection of electrons from the charge storage layer side to the semiconductor substrate side.
[0007]
The injection of electrons from the semiconductor substrate side to the charge storage layer side has an anisotropic tunnel layer that is easier than the injection of electrons from the charge storage layer side to the semiconductor substrate side. At the time of writing with a voltage applied, electrons flow easily, so that the writing time can be shortened. When the memory is maintained, electrons are hardly transported, so that the memory holding time can be lengthened. In the SiO _x / SiO ₂ structure, which is a stacked structure of a silicon-rich silicon oxide (SiO _x ) layer and a silicon oxide (SiO ₂ ) layer, electrons easily flow from SiO _{x in the} direction of SiO ₂ , but in the opposite direction. Since it has anisotropy in the ease of electron injection, in which electrons hardly flow, it can be used as an anisotropic tunnel layer.
[0008]
In the semiconductor device according to the present invention, an ultrathin oxide film is further formed between the anisotropic tunnel layer and the semiconductor substrate.
[0009]
An ultra-thin oxide film exists between the semiconductor substrate and the first tunnel insulating film, and the interface between the two layers is adjusted so that the first tunnel insulating film (SiO _x ) directly contacts the channel region of the FET. when, receiving the influence of the interface between the SiO _x and Si that depend on the characteristics of SiO _x, it is possible to prevent the operating characteristics of the FET operation is deteriorated.
[0010]
In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention includes a step of forming an anisotropic tunnel layer on a semiconductor substrate, and a step of forming a charge storage layer on the anisotropic tunnel layer. , Is characterized by having. The method may further include forming an ultra-thin oxide film on the semiconductor substrate before forming the anisotropic tunnel layer.
[0011]
As a result, a tunnel insulating film having a diode effect is formed on the semiconductor substrate, and it is possible to manufacture a semiconductor device in which the writing time is shortened and the storage time is lengthened. Further, since an extremely thin oxide film can be formed between the semiconductor substrate and the anisotropic tunnel layer, it becomes possible to manufacture a semiconductor element capable of preventing the operating characteristics from being deteriorated.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
[First Embodiment]
Hereinafter, a semiconductor device and a method for manufacturing the semiconductor device according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and can be appropriately modified without departing from the gist of the present invention. In the description, only one semiconductor element will be described, but it is assumed that a plurality of the illustrated semiconductor elements are formed on a semiconductor substrate.
[0013]
FIG. 1 is a cross-sectional view schematically showing the structure of a semiconductor device of the present invention, which is a MISFET (metal insulator field effect transistor) type device in which a floating gate layer is composed of a multilayer film. As shown in FIG. 1, a source region 2 and a drain region 3 are formed on a semiconductor substrate 1, a first tunnel insulating film 4 is stacked on the semiconductor substrate 1 by 3 to 5 nm, and a first tunnel insulating film 4 is formed. A second tunnel insulating film 5 is stacked thereon with a thickness of 1 to 5 nm, a charge storage layer 6 is stacked on the second tunnel insulating film 5 with a thickness of 3 to 20 nm, and a blocking insulating film 7 is formed on the charge storage layer 6 with a thickness of 5 to 10 nm. The gate electrode 8 is formed on the blocking insulating film 7 by stacking.
[0014]
The semiconductor substrate 1 is a substrate made of a semiconductor material such as p-type silicon. The source region 2 and the drain region 3 are formed in a self-aligned manner with the gate electrode by a method such as ion implantation of an n-type dopant such as phosphorus or arsenic. The surface portion of the semiconductor substrate 1 between the source region 2 and the drain region 3 becomes a channel region. Although not shown, an opening is formed in the source region 2 and the drain region 3 to extract an electrode.
[0015]
The first tunnel insulating film 4 is silicon-rich silicon oxide (SiO _x ), and the range of x of SiO _x is 0.2 <x <1.8. In the first tunnel insulating film 4, Si clusters 9, which are fine lump of Si, are deposited.
[0016]
The second tunnel insulating film 5 is typically SiO ₂ , and when writing, that is, when a positive voltage is applied to the gate electrode 8, the first tunnel insulating film 4 is a silicon-rich silicon oxide film SiO 2. _{It functions} as a tunnel insulating film that introduces electrons by a tunnel effect into the charge storage layer 6 that is a layer that stores electrons from the _x side. When a negative voltage is applied to the gate electrode 8, the gate electrode 8 functions as a tunnel insulating film for reducing electrons from the charge storage layer 6 by a tunnel effect in a reverse direction. When the voltage is not applied to the gate electrode 8 and the charge storage layer 6 is in the storage maintaining state, the charge storage layer 6 serves as an insulating film for preventing electrons from leaking from the charge storage layer 6 to the semiconductor substrate 1 through the first tunnel insulating film 4. work.
[0017]
The charge storage layer 6 is typically a SiN _x layer including traps, and is a material that functions as a layer for storing charges. The blocking insulating film 7 prevents charge from leaking from the charge storage layer 6 to the gate electrode 8 when a voltage is applied to the gate electrode 8. Typical materials are SiO _2. The gate electrode 8 is made of metal or doped polysilicon (doped poly-Si).
[0018]
The combination of the first tunnel insulating film 4 (SiO _x ) and the second tunnel insulating film 5 (SiO ₂ ) is such that when a voltage is applied to both ends of the first tunnel insulating film 4 (SiO _x ), the first tunnel insulating film 5 Electrons have anisotropy in ease of electron injection, such that electrons hardly flow in the direction of the insulating film 4 and conversely, electrons easily flow from the first tunnel insulating film 4 to the second tunnel insulating film 5. . The combination of the first tunnel insulating film 4 and the second tunnel insulating film 5 is used as an anisotropic tunnel layer.
[0019]
When the first tunnel insulating film 4 is made of SiO _x and the second tunnel insulating film 5 is made of SiO _2, that is, in the case of a SiO _x / SiO ₂ structure, electrons are emitted in the direction from SiO ₂ to SiO _x. Are difficult to flow, and conversely, electrons easily flow from SiO _x to SiO ₂ . J. J. DiMaria et al. Appl. Phys. 51 (59), 2722 (1980), Appl. Pys. Lett. 37 (1), 61 (1980). It is revealed in.
[0020]
D. J. The anisotropy of the ease of electron injection in the SiO _x / SiO ₂ structure will be described with reference to FIGS. 2 to 6 based on a paper by DiMaria et al. FIG. 2 shows the SiO _x / SiO ₂ structure used in the experiment. An insulating film 25 of SiO ₂ and an insulating film 24 of SiO _x are formed on a semiconductor substrate 21 of Si. A gate electrode 28 made of aluminum (Al) is formed on the insulating film 24. In order to generate a potential difference between the semiconductor substrate 21 and the gate electrode 28, terminals are connected to the semiconductor substrate 21 and the gate electrode 28, and a voltage is applied to both terminals to form an SiO _x / SiO ₂ structure. A current was applied and current-voltage characteristics (IV characteristics) were measured. The insulating film 24 is made of Si-rich silicon oxide, and has a structure in which Si clusters 29 on the order of 100 ° are deposited in SiO ₂ .
[0021]
FIG. 3 shows a current-voltage characteristic (IV characteristic) when the SiO _x / SiO ₂ structure is provided on the semiconductor substrate 21 side, and FIG. 4 shows an IV characteristic when the SiO _x / SiO ₂ structure is provided on the gate electrode 28 side. FIG. 5 shows the IV characteristics in the case of providing both on the 21 side and the gate electrode 28 side. In each of the figures, the horizontal axis indicates the magnitude of the voltage applied to the gate electrode 28, and the vertical axis indicates the current value.
[0022]
The IV characteristic indicated by a broken line (Vg ⁺ ) in the graph indicates a case where a positive potential is applied to the gate electrode 28 and electrons flow from the semiconductor substrate 21 to the gate electrode 28, and a solid line (Vg ⁺ ) ^The IV characteristic indicated by-) indicates a case where a negative potential is applied to the gate electrode 28 and electrons flow from the gate electrode 28 to the semiconductor substrate 21. The insets in the graph schematically show the arrangement of each layer. The gray portion is the insulating film 24 (SiO _x ) having a thickness of 100 mm, the hatched portion is the semiconductor substrate 21 (Si), the black portion is the gate electrode 28 formed of Al, and the colorless portion is the insulating film having a thickness of 300 mm. 25 (SiO ₂ ).
[0023]
From the IV characteristics shown in FIG. 3, Vg ⁺ <Vg ⁻ is known when the current value is the same, and from the IV characteristics shown in FIG. 4, Vg ⁺ > Vg when the current value is the same. ^- and it can be seen. Comparing the electron injection from the same Si substrate side, it can be seen that, for the same current value of the IV characteristic of FIG. 3Vg ⁺ and FIG. 4Vg ⁺ , FIG. 3Vg ⁺ <FIG. 4Vg ⁺ . Therefore, it can be seen that the SiO _x / SiO ₂ structure allows electrons to flow easily from SiO _{x in the} direction of SiO ₂ but does not easily flow electrons in the opposite direction.
[0024]
As a reason why the SiO _x / SiO ₂ structure shows anisotropy of ease of electron injection, a model that is considered will be described with reference to a potential diagram of FIG. Si clusters 29 are precipitated in the SiO _x layer of the insulating film 24, and electrons move between the Si clusters by a direct tunnel. Therefore, the resistance of the SiO _x layer is considerably lower than that of the SiO ₂ layer. The ease of flow of electrons as a whole in the SiO _x / SiO ₂ structure is mainly determined near the interface between the two layers, and the injection of electrons from the Si cluster near the interface into SiO ₂ is considered to be a FN (Fowler Nordheim) tunnel. Can be The outer shape of the Si cluster 29 (or dot) has a curved surface, in other words, because it is sharp, there is a region where the electric field is more concentrated than Si exists as a flat surface. Therefore, the electric field intensity of SiO ₂ near the surface of the Si cluster 29 is higher than the average electric field intensity. It is considered that the efficiency of electron injection from the Si cluster 29 to the insulating film 25 (SiO ₂ ) increases for the reasons described above.
[0025]
The SiO _x / SiO ₂ structure has anisotropy in the ease of electron injection, in which electrons flow easily from SiO _{x in the} direction of SiO ₂ but electrons do not easily flow in the reverse direction. This makes it easier for electrons to flow during writing when a positive voltage is applied to the gate electrode, so that the writing time can be shortened.In the memory maintaining state, electrons are difficult to be transported in the reverse direction. It can be longer.
[0026]
Next, a method of manufacturing the semiconductor device having the above-described structure will be described with reference to FIG. First, as shown in FIG. 7A, a p-type silicon single crystal semiconductor substrate 1 is subjected to element isolation by LOCOS (local oxidation of silicon) or the like, and non-isolated by PECVD (plasma enhanced chemical vapor or deposition) method. A first tunnel insulating film 4 is formed by depositing SiO _x having a stoichiometric composition on the main surface of the semiconductor substrate 1 to a thickness of about 3 to 5 nm. Next, SiO ₂ is deposited on the first tunnel insulating film 4 to a thickness of about 1 to 5 nm by a CVD method to form a second tunnel insulating film 5.
[0027]
Subsequently, as shown in FIG. 7B, SiN _x (Si ₃ N ₄ ) is deposited on the second tunnel insulating film 5 by LPCVD (low pressure chemical deposition) to a thickness of about ₃ to 20 nm to form a charge storage layer. 6 is formed. Further, a blocking insulating film 7 is formed by depositing SiO ₂ on the charge storage layer 6 by about 5 to 10 nm by a CVD method. Next, Al or doped polysilicon (doped poly-silicon) is deposited on the blocking insulating film 7 to form the gate electrode 8.
[0028]
Next, as shown in FIG. 7C, a heat treatment is applied in a nitrogen atmosphere at, for example, 300 ° C. to 1100 ° C. for about one hour. By this heat treatment, in the first tunnel insulating film 4, the SiO _x film is phase-separated and a Si cluster 9 of about several nanometers is precipitated as schematically shown in FIG.
[0029]
FIG. 7D shows patterning of the gate multilayer film. The first tunnel insulating film 4 and the second tunnel insulating film 5 containing the Si cluster 9 are formed by a method such as RIE (Reactive Ion Etching). The charge storage layer 6, the blocking insulating film 7, and the gate electrode 8 are cut to the same size.
[0030]
In FIG. 7E, an n-type dopant such as phosphorus or arsenic is introduced into the surface of the semiconductor substrate 1 by ion implantation or the like, so that the source region 2 and the drain region 3 are formed in a self-aligned manner with the gate electrode 8. You. Next, an insulating film is formed on the entire surface by a CVD method, and the insulating film is etched by RIE or the like to form a sidewall on a side wall (not shown). Finally, the source region 2 and the drain region 3 are opened and electrodes (not shown) are attached in a required pattern to complete a memory cell.
[0031]
[Second embodiment]
[0032]
Next, another embodiment of a semiconductor device and a method of manufacturing the semiconductor device according to the present invention will be described in detail with reference to the drawings. Note that this embodiment is different from the above-described first embodiment only in that an extremely thin oxide film is formed between the semiconductor substrate and the first tunnel insulating film. Further, the present invention is not limited to the following description, and can be appropriately modified without departing from the gist of the present invention. In the description, only one semiconductor element will be described, but it is assumed that a plurality of the illustrated semiconductor elements are formed on a semiconductor substrate.
[0033]
FIG. 8 is a cross-sectional view schematically showing the structure of the semiconductor element of the present invention, which is a MISFET (metal insulator field effect transistor) type element in which a floating gate layer is formed of a multilayer film. As shown in FIG. 8, a source region 32 and a drain region 33 are formed on a semiconductor substrate 31, an ultra-thin oxide film 40 is formed on the semiconductor substrate 31 to a thickness of about 2 nm, and a first A tunnel insulating film 34 is laminated with a thickness of 3 to 5 nm, a second tunnel insulating film 35 is laminated with a thickness of 1 to 5 nm on the first tunnel insulating film 34, and a charge storage layer 36 with a thickness of 3 to 5 nm is formed on the second tunnel insulating film 35. The blocking insulating film 37 is stacked on the charge storage layer 36 to a thickness of 5 to 10 nm, and the gate electrode 38 is formed on the blocking insulating film 37.
[0034]
The semiconductor substrate 31 is a substrate made of a semiconductor material such as p-type silicon. The source region 32 and the drain region 33 are formed in a self-aligned manner with the gate electrode by a method such as ion implantation of an n-type dopant such as phosphorus or arsenic. The surface portion of the semiconductor substrate 31 between the source region 32 and the drain region 33 becomes a channel region. Although not shown, openings are formed in the source region 32 and the drain region 33 to take out electrodes.
[0035]
The ultra-thin oxide film 40 is typically SiO ₂ . The ultra-thin oxide film 40 adjusts the interface state between the channel region of the FET and the first tunnel insulating film 34. The ultra-thin oxide film 40 is used for a different purpose from the conventional tunnel insulating film of the dot memory, and the semiconductor substrate 31 (Si) From the first tunnel insulating film 34 (SiO _x ) to a sufficiently thin film (for example, 2 nm or less) so as not to hinder the transport of carriers. In other words, the film is thin enough to transport carriers without excessive resistance by the direct tunnel.
[0036]
The first tunnel insulating film 34 is silicon-rich silicon oxide (SiO _x ), and the composition of SiO _x is such that the range of x is 0.2 <x <1.8. In the first tunnel insulating film 34, a Si cluster 39, which is a fine lump of Si, is deposited.
[0037]
The second tunnel insulating film 35 is typically SiO _{2. In} the case of writing, that is, when a positive voltage is applied to the gate electrode 38, a layer that accumulates electrons from the SiO _x side of the first tunnel insulating film 34. And acts as a tunnel insulating film for introducing electrons into the charge storage layer 36 by the tunnel effect. When a negative voltage is applied to the gate electrode 38, the gate electrode 38 functions as a tunnel insulating film that reduces electrons from the charge storage layer 36 by a tunnel effect in the reverse direction. When the voltage is not applied to the gate electrode 38 and the charge storage layer 36 is in the memory maintaining state, the charge storage layer 36 serves as an insulating film for preventing electrons from leaking from the charge storage layer 36 to the semiconductor substrate 31 through the first tunnel insulating film 34. work.
[0038]
The charge storage layer 36 is typically a SiN _x layer including traps, and is a material that functions as a layer for storing charges. The blocking insulating film 37 prevents the charge from leaking from the charge storage layer 36 to the gate electrode 38 when a voltage is applied to the gate electrode 38. Typical materials are SiO _2. The gate electrode 38 is made of metal or doped polysilicon (doped poly-Si).
[0039]
The combination of the first tunnel insulating film 34 (SiO _x ) and the second tunnel insulating film 35 (SiO ₂ ) is such that when a voltage is applied to both ends thereof, the first tunnel insulating film 35 Electrons have anisotropy in the ease of electron injection, such that electrons hardly flow in the direction of the insulating film 34 and conversely, electrons easily flow from the first tunnel insulating film 34 to the second tunnel insulating film 35. . The combination of the first tunnel insulating film 44 and the second tunnel insulating film 44 is used as an anisotropic tunnel layer.
[0040]
The SiO _x / SiO ₂ structure has anisotropy in the ease of electron injection, in which electrons flow easily from SiO _{x in the} direction of SiO ₂ but electrons do not easily flow in the reverse direction. This makes it easier for electrons to flow during writing with a voltage applied to the gate electrode, so that the writing time can be shortened.In the memory maintaining state, it is difficult to transport electrons, so that the memory maintaining time can be lengthened. It becomes possible.
[0041]
In addition, the ultra-thin oxide film 40 exists between the semiconductor substrate 31 and the first tunnel insulating film 34, and the first tunnel insulating film 34 (SiO _x ) is directly formed by adjusting the interface between the two layers. when in contact with the channel region of the FET, receiving the influence of the interface between the SiO _x and Si that depend on the characteristics of SiO _x, it is possible to prevent the operating characteristics of the FET operation is deteriorated.
[0042]
Next, a method of manufacturing the semiconductor device having the above-described structure will be described with reference to FIG. First, as shown in FIG. 9A, a p-type silicon single crystal semiconductor substrate 31 is subjected to element isolation by LOCOS (local oxidation of silicon) or the like, and a SiO ₂ film is formed on the semiconductor substrate 31 by a thermal oxidation method. An extremely thin oxide film 40 is formed to a thickness of about 2 nm. Then by PECVD (plasma enhanced chemical vap or deposition ) method, a non-stoichiometric deposited about 3~5nm on ultrathin oxide film 40 a SiO _x composition to the first tunnel insulating film 34 formed. Next, SiO ₂ is deposited on the first tunnel insulating film 34 to a thickness of about 1 to 5 nm by a CVD method to form a second tunnel insulating film 35.
[0043]
Then, as shown in FIG. 9 (b), to form a LPCVD (low pressure chemical vapor deposition) method by the second tunnel insulating film 35 charge storage layer 36 is deposited about 3~20nm the SiN _x on. Further, a blocking insulating film 37 is formed by depositing SiO ₂ on the charge storage layer 36 by about 5 to 10 nm by the CVD method. Next, Al or doped polysilicon (doped poly-silicon) is deposited on the blocking insulating film 37 to form a gate electrode 38.
[0044]
Next, as shown in FIG. 9C, a heat treatment is applied in a nitrogen atmosphere at, for example, 300 ° C. to 1100 ° C. for about one hour. By this heat treatment, in the first tunnel insulating film 34, the SiO _x film is phase-separated and a Si cluster 39 of about several nanometers is precipitated as schematically shown in FIG.
[0045]
FIG. 9D shows the patterning of the gate multilayer film. The ultra-thin oxide film 40, the first tunnel insulating film 34 containing the Si cluster 39, and the second tunneling film are formed by a method such as RIE (Reactive Ion Etching). The tunnel insulating film 35, the charge storage layer 36, the blocking insulating film 37, and the gate electrode 38 are cut to the same size.
[0046]
In FIG. 9E, an n-type dopant such as phosphorus or arsenic is introduced into the surface of the semiconductor substrate 31 by ion implantation or the like, so that the source region 32 and the drain region 33 are formed in a self-aligned manner with the gate electrode 38. You. Next, an insulating film is formed on the entire surface by a CVD method, and the insulating film is etched by RIE or the like to form a sidewall on a side wall (not shown). Finally, the source region 32 and the drain region 33 are opened and electrodes (not shown) are attached in a required pattern to complete a memory cell.
[0047]
【The invention's effect】
The SiO _x / SiO ₂ structure has anisotropy in the ease of electron injection, in which electrons flow easily from SiO _{x in the} direction of SiO ₂ but electrons do not easily flow in the reverse direction. This makes it easier for electrons to flow during writing when a voltage is applied to the gate electrode, so that the writing time can be shortened.In the memory maintaining state, it is difficult to transport electrons, so that the memory maintaining time can be lengthened. It becomes possible.
[0048]
An ultra-thin oxide film exists between the semiconductor substrate and the first tunnel insulating film, and the interface between the two layers is adjusted so that the first tunnel insulating film (SiO _x ) directly contacts the channel region of the FET. when, receiving the influence of the interface between the SiO _x and Si that depend on the characteristics of SiO _x, it is possible to prevent the operating characteristics of the FET operation is deteriorated.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing a structure of a MISFET type semiconductor device according to a first embodiment.
FIG. J. It is a diagram schematically showing an experiment to measure the I-V characteristic of the _SiO x / SiO ₂ multilayer structure by such DiMaria.
FIG. 3 is a graph showing IV characteristics when an SiO _x / SiO ₂ stacked structure is provided on the semiconductor substrate side.
FIG. 4 is a graph showing IV characteristics when a SiO _x / SiO ₂ stacked structure is provided on the gate electrode side.
FIG. 5 is a graph showing IV characteristics when a SiO _x / SiO ₂ stacked structure is provided on both the semiconductor substrate side and the gate electrode side.
FIG. 6 is a model diagram showing the reason why the SiO _x / SiO ₂ stacked structure shows anisotropy in ease of electron injection.
FIG. 7 is a process chart showing a method for manufacturing a MISFET type semiconductor device according to the first embodiment.
FIG. 8 is a schematic sectional view showing a structure of a MISFET type semiconductor device according to a second embodiment.
FIG. 9 is a process chart showing a method for manufacturing a MISFET type semiconductor device according to the second embodiment.
FIG. 10 is a schematic cross-sectional view showing the structure of a conventional MONOS nonvolatile memory element.
[Explanation of symbols]
1, 21, 31, 51 Semiconductor substrate 2, 32, 52 Source region 3, 33, 53 Drain region 4, 34 First tunnel insulating film 5, 35 Second tunnel insulating film 24, 25 Insulating film 55 Tunnel insulating film 6, 36, 56 Charge storage layer 7, 37, 57 Blocking insulating film 8, 28, 38, 58 Gate electrode 9, 29, 39 Silicon cluster 40 Ultra-thin oxide film

Claims (25)

On a semiconductor substrate, having a charge storage layer for storing data by storing carriers,
Between the semiconductor substrate and the charge storage layer, injection of carriers from the semiconductor substrate side to the charge storage layer side is easier than injection of carriers from the charge storage layer side to the semiconductor substrate side. A semiconductor device having an anisotropic tunnel layer. 2. The semiconductor device according to claim 1, wherein an ultra-thin oxide film is further formed between said anisotropic tunnel layer and said semiconductor substrate. 2. The semiconductor device according to claim 1, wherein the anisotropic tunnel layer is formed by a combination of a first tunnel insulating film and a second tunnel insulating film. 4. The semiconductor device according to claim 3, wherein said first tunnel insulating film is made of silicon-rich silicon oxide. The composition of the silicon-rich silicon _oxide, the semiconductor device according to claim 4, characterized by being represented by SiO x (0.2 <x <1.8 ). 5. The semiconductor device according to claim 4, wherein fine silicon clusters are deposited in the first tunnel insulating film. 4. The semiconductor device according to claim 3, wherein said second tunnel insulating film is made of silicon oxide. 2. The semiconductor device according to claim 1, wherein said charge storage layer is made of silicon nitride. 3. The semiconductor device according to claim 2, wherein said ultra-thin oxide film is made of silicon oxide. Forming a first tunnel insulating film on the semiconductor substrate on which the source region and the drain region are formed;
A second tunnel insulating film is formed on the first tunnel insulating film;
Forming a charge storage layer on the second tunnel insulating film;
A blocking insulating film is formed on the charge storage layer,
A semiconductor device, wherein a gate electrode is formed on the blocking insulating film. The first tunnel insulating film is made of silicon-rich silicon oxide, the second tunnel insulating film is made of silicon oxide, the charge storage layer is made of silicon nitride, and the blocking insulating film is made of silicon oxide. The semiconductor device according to claim 10, wherein the semiconductor device is configured. The semiconductor device according to claim 11, wherein the composition of the silicon-rich silicon oxide is represented by SiO _x (0.2 <x <1.8). 12. The semiconductor device according to claim 11, wherein fine silicon clusters are deposited in the first tunnel insulating film. On the semiconductor substrate on which the source region and the drain region are formed, an extremely thin insulating film made of silicon oxide is formed,
Forming a first tunnel insulating film on the ultra-thin insulating film;
A second tunnel insulating film is formed on the first tunnel insulating film;
Forming a charge storage layer on the second tunnel insulating film;
A blocking insulating film is formed on the charge storage layer,
A semiconductor device, wherein a gate electrode is formed on the blocking insulating film. The ultra-thin insulating film is made of silicon oxide, the first tunnel insulating film is made of silicon-rich silicon oxide, the second tunnel insulating film is made of silicon oxide, and the charge storage layer is made of silicon nitride. The semiconductor device according to claim 14, wherein the blocking insulating film is made of silicon oxide. The composition of the silicon-rich silicon _oxide, the semiconductor device according to claim 15, wherein the represented by SiO x (0.2 <x <1.8 ). 16. The semiconductor device according to claim 15, wherein fine silicon clusters are deposited in the first tunnel insulating film. Forming an anisotropic tunnel layer on a semiconductor substrate;
Forming a charge storage layer on the anisotropic tunnel layer;
A method for manufacturing a semiconductor device, comprising: 19. The method according to claim 18, further comprising forming an ultra-thin oxide film on the semiconductor substrate before forming the anisotropic tunnel layer. 19. The semiconductor device according to claim 18, wherein the step of forming the anisotropic tunnel layer further includes a step of forming a first tunnel insulating film and a step of forming a second tunnel insulating film. Manufacturing method. 21. The method according to claim 20, further comprising a step of performing a heat treatment in an inert gas atmosphere after forming the first tunnel insulating film. 21. The semiconductor device according to claim 20, wherein the step of forming the first tunnel insulating film comprises stacking silicon-rich silicon oxide by a CVD method. 21. The method according to claim 20, wherein the step of forming the second tunnel insulating film comprises stacking silicon oxide by a CVD method. 19. The method according to claim 18, wherein the step of forming the charge storage layer comprises stacking silicon nitride by a CVD method. 20. The method according to claim 19, wherein the step of forming the ultra-thin oxide film comprises forming silicon oxide on the surface of the semiconductor substrate by a thermal oxidation method.

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