JP2004096039A - Method for manufacturing semiconductor device - Google Patents

Abstract

An object of the present invention is to suppress an increase in leakage current due to a punch-through or body floating effect of a MOS transistor.
An element isolation region, a gate insulating film, and a dummy gate are formed in a single crystal Si film on an oxide film (FIG. A), and an S / D extension region is formed by ion implantation using the gate as a mask. 11 and 12 are formed (FIG. B), sidewalls 13 are formed, and S / Ds 15 and 16 are formed by ion implantation 14 of N-type impurities using the gate 6 and the sidewalls 13 as masks (FIG. C), and an insulating film is formed. 19 is deposited and polished until the upper surface of the gate 6 appears, and then the gate 6 is removed (FIG. 4D). A high-concentration P-type impurity layer is formed between the S / Ds 15 and 16 (not shown). A regular gate is provided after the gate 6. The high-concentration impurity injection layer functions as a punch-through stopper.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device capable of suppressing a leakage current due to a body floating (Body Floating) effect of an SOI type MOS transistor.
[0002]
[Prior art]
A method of manufacturing an N-channel MOS transistor for manufacturing an SOI MOS transistor on a single crystal Si film on an insulating film according to a conventional example will be described with reference to FIG.
[0003]
First, as shown in FIG. 5A, an SOI substrate in which a BOX (Buried Oxide) 2 and an SOI (Silicon on Insulator) 3 are sequentially stacked on a Si substrate 1 is used, and the SOI (single crystal Si) is used. 3, an element isolation region (SiO ₂ ) 4 and a gate oxide film (SiO ₂ ) 5 are formed, a polycrystalline Si film 6 is deposited thereon, a photoresist mask 8 is formed, and polycrystalline Si is formed by anisotropic etching. The gate electrode 7 is formed.
[0004]
Next, as shown in FIG. 5B, source / drain diffusion layers (S / D diffusion layers) 11 and 12 are formed by ion implantation 10 using the gate electrode 7 as a mask, and then an insulating film is deposited. The entire surface is etched back to form a gate electrode sidewall 13 leaving an insulating film on the side of the gate electrode, and using this as a mask, ion implantation 14 is performed to form source / drain (S / D) 15 and 16 (FIG. 5). (C)). Then, a heat treatment for activating the impurities implanted into the S / Ds 15 and 16 by ion implantation is performed to form a silicide layer on the S / D diffusion layers 11 and 12 and the gate electrode 7 and then deposit an interlayer film 17 ( As shown in FIG. 5D, a MOS transistor is manufactured by making a contact hole in the interlayer film 17 to make contact with the silicide layer and forming a contact and a wiring.
[0005]
[Problems to be solved by the invention]
When a short-channel MOS transistor is manufactured by the above-described conventional technique, the junction shape between the S / D and the single-crystal Si film is constricted as shown in FIG. Therefore, punch through occurs due to impact ionization and DIBL (Drain induced Barrier Lowering), and the leakage current between the S / D increases. For this reason, suppression of the short channel effect is indispensable, but in the case of SOI MOS transistors in particular, holes generated by impact ionization accumulate in the body, so that the body floating effect is added, and the situation is more serious. Therefore, relaxation of the electric field near the drain for suppressing impact ionization is a major technical problem.
[0006]
The present invention has been made to solve such a problem, and a method of manufacturing a semiconductor device in which an electric field near a drain is alleviated and an increase in leak current due to punch-through and body floating effects can be suppressed. The purpose is to provide.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes: (1) a method of manufacturing a MOS transistor in which a MOS transistor is formed on a single crystal Si film; A first insulating film and a first polycrystalline Si film are sequentially deposited on the surface of the film, a resist pattern is formed, and the first polycrystalline Si film is removed by anisotropic etching using the resist pattern as a mask. (2) a step of leaving the polycrystalline Si only in a desired region; (2) a step of implanting impurities into the single-crystal Si film using the first polycrystalline Si as a mask; and (3) a step of leaving the first polycrystalline Si. Depositing a second insulating film so as to cover the crystalline Si film, flattening irregularities on the surface of the second insulating film by polishing, and exposing the surface of the first polycrystalline Si film; (4) exposing Only the removed first polycrystalline Si film is selectively removed. A step of (5) implanting impurities into the single crystal Si film using the second insulating film as a mask, and (6) removing the first insulating film to form a third insulating film and a second polysilicon film. (7) a step of sequentially depositing a crystalline Si film, and (7) removing the second polycrystalline Si film on the second insulating film by polishing, and removing the second polycrystalline Si film in a groove where the second insulating film does not exist. And leaving the surface flat.
[0008]
In the method of manufacturing a semiconductor device according to the second aspect of the present invention, the impurity implantation using the second insulating film as a mask in the first aspect of the invention is performed by heat treatment of the impurity implantation using the first polycrystalline Si film as a mask. Thereafter, the step is performed after removing the polycrystalline Si film. According to a third aspect of the present invention, in the method of manufacturing a semiconductor device, the impurity implantation using the second insulating film as a mask in the first aspect of the present invention is performed at a concentration of 1 × 10 ¹⁸ / cm ³ to 1 × 10 ¹⁹ /. cm ³ . According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device, the impurity implantation using the second insulating film as a mask in the first aspect of the present invention is performed by using a third group element for an NMOS or a fifth group element for a PMOS. Is injected. According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device, the impurity implantation using the second insulating film as a mask in the first aspect of the invention is an ion implantation method.
[0009]
According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which a MOS transistor is formed on a single-crystal Si film. Forming an insulating film and a polycrystalline Si film in this order, forming an etching mask, removing the polycrystalline Si film by anisotropic etching, and leaving the polycrystalline Si only in a desired region to form a gate electrode (2) After forming the gate electrode, a second insulating film and a third insulating film are sequentially deposited, and the entire surface is etched back to leave the third insulating film on the side of the gate electrode to form the first sidewall. And (3) after forming the first sidewall, depositing a fourth insulating film, etching back the entire surface, and forming a second sidewall with the fourth insulating film outside the first sidewall. And (4) forming a gate electrode. And anisotropically etching the single crystal Si film using the first and second sidewalls as a mask; (5) removing the second sidewalls by etching; and (6) removing the etched single-crystal Si film. The method is characterized by including a step of implanting impurities into the crystalline Si film and performing heat treatment to form a source / drain, and (7) a step of depositing a single crystal Si film in the source / drain region by epitaxial growth.
[0010]
According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixth aspect, the source / drain impurities are implanted by removing the second sidewall after the anisotropic etching of the single crystal Si film. It is characterized by performing after. In a method of manufacturing a semiconductor device according to an eighth aspect of the present invention, the third and fourth insulating films of the sixth aspect of the present invention are deposited using films having different components, and the first and second sidewalls are formed of different films. It is characterized by being formed by. In the method of manufacturing a semiconductor device according to the ninth aspect, in the anisotropic etching of the single-crystal Si film according to the sixth aspect, the tip of the lateral etching is located below the second sidewall, preferably, the first sidewall. And a boundary between the second side wall and the second side wall.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described with reference to the drawings.
(1) Embodiment 1
A method for manufacturing an N-channel MOS transistor on a single crystal Si film (SOI) formed on an oxide film according to the first embodiment will be described with reference to FIGS. Since the P-channel MOS transistor only needs to be changed from the N-type to the P-type and the P-type to the N-type, if the N-type and the P-type are replaced in the following description, a method of manufacturing the P-channel MOS transistor is obtained. .
[0012]
As shown in FIG. 1A, an SOI substrate in which a Si oxide film (BOX) 2 and a single crystal Si film (SOI) 3 are stacked on a Si substrate 1 is formed by an element isolation region 4 by a known trench element isolation method. Is formed, a thermal oxide film called a pad oxide film is formed on the surface of the single crystal Si film 3 by thermal oxidation, ion implantation for well formation and ion implantation for threshold adjustment are performed, and the pad oxide film is wet-etched with an HF aqueous solution. After that, a Si oxide film (first insulating film) 5 serving as a gate insulating film and a polycrystalline Si film for the gate electrode 6 are sequentially deposited. Table 1 exemplifies the respective film thicknesses when fabricating a 0.18 μm fully depleted SOI MOS transistor.
[0013]
[Table 1]
Example of deposited film thickness Single crystal Si 2 film (SOI) of SOI substrate: 30 nm
Oxide film (BOX) of SOI substrate: 100 nm
Pad oxide film: 8 nm
Oxide film for gate insulating film: 3.5 nm
Polycrystalline Si film for gate electrode: 150 nm
Subsequently, a resist pattern 8 is formed on the polycrystalline Si film using a lithography technique, and the polycrystalline Si film is anisotropically dry-etched by RIE (reactive ion etching) using the resist pattern 8 as an etching mask. A gate electrode (first polycrystalline Si film) 6 is formed. After the etching, the resist pattern 8 used as an etching mask is peeled off by a known method.
[0014]
Next, a resist pattern for forming source / drain diffusion layers (S / D diffusion layers) 11 and 12 is formed by lithography, and ion implantation 10 of N-type impurities is performed (see FIG. 1B). In this ion implantation, the impurity is not implanted into the SOI 3 below the gate electrode using the polycrystalline Si film 6 as a mask. Subsequently, an insulating film is deposited, a sidewall (second insulating film) 13 is formed on the gate electrode 6 by a known method, and then a resist pattern for forming source / drain (S / D) 15 and 16 is formed. It is formed using a lithography technique, and ion implantation 14 of an N-type impurity is performed (see FIG. 1C). In this ion implantation, the gate electrode 6 and the side wall 13 are used as a mask, and no impurity is implanted into SOI below the gate electrode 6 and the side wall 13. Table 2 exemplifies each ion implantation condition. The resist mask after the ion implantation is peeled off by a known method after each ion implantation.
[0015]
[Table 2]
Example of ion implantation conditions Ion implantation energy for the S / D diffusion layer As: 2.52 keV
S / D
P ion implantation implantation energy: 15 keV
Dose amount: 1.2 × 10 ¹⁵ / cm ²
After the impurity ions are implanted in the S / Ds 15 and 16, RTA (short annealing) at 900 to 1000 ° C. is performed. Thereafter, the gate electrode 6 is covered with an oxide film, Co salicide is formed on the S / Ds 15 and 16 by a known method, and a Si oxide film for the interlayer film 19 is deposited. Next, the Si oxide film is subjected to CMP (chemical / mechanical polishing) to flatten the upper surface of the gate electrode 6 and expose the surface of the gate electrode 6 from the interlayer film (third insulating film) 19. Then, the entire surface is anisotropically dry-etched by RIE (reactive ion etching) to remove the gate electrode 6 and form a groove 18 inside the sidewall 13 (see FIG. 1D). Table 3 shows examples of the gate electrode dry etching conditions.
[0016]
[Table 3]
Example of gate electrode dry etching conditions Gas used: HBr / O2 = 100/8 sccm
Pressure: 0.5Pa
RF power: 20W
Next, a resist pattern for forming a high-concentration P-type region having a concentration of about 1 × 10 ¹⁸ / cm ³ to 1 × 10 ¹⁹ / cm ³ is formed at the center of the SOI by using a lithography technique. Ion implantation 20 is performed to form a high-concentration impurity implantation layer (punch-through stopper) 21 (see FIG. 2E). In this ion implantation 20, the interlayer film 19 serves as a mask, and no impurities are implanted into the S / Ds 15 and 16. Table 4 exemplifies ion implantation conditions. The resist mask after the ion implantation is stripped by a known method.
[0017]
[Table 4]
Example of ion implantation conditions: ion implantation energy of BF2: 30 keV
Dose amount: 3 × 10 ¹² / cm ²
Thereafter, RTA treatment is performed at 900 to 1000 ° C. for 10 seconds to activate the high-concentration impurities implanted by the ion implantation 20. Subsequently, after the gate oxide film 5 below the trench 18 is wet-etched with an HF aqueous solution, a thermal oxide film 5a is deposited again by thermal oxidation, for example, to a thickness of about 3.5 nm. The deposited film 5a below the groove 18 may be made of a material having a high dielectric constant such as Ta ₂ O ₅ , for example. Then, a second polycrystalline Si 22 for the gate electrode 23 is deposited, for example, to a thickness of about 500 nm in the groove 18 formed by etching the gate electrode 6 (see FIG. 2F).
[0018]
Next, the polycrystalline Si film 22 on the interlayer film 19 is removed by CMP to form a polycrystalline Si gate electrode 23 (see FIG. 2G). This CMP is performed, for example, with an aqueous solution of ethylenediamine (Ethylenediamine) having a high selectivity with respect to the interlayer film (oxide film) 19. Thereafter, Co salicide is formed on the gate electrode 23 by a known method by a known method. Next, a Si oxide film (interlayer film) 24 is deposited by a known method (see FIG. 2H), contacts and wiring are formed (not shown), and an SOI N-channel MOS transistor is manufactured. Instead of the polycrystalline Si film 22, a metal such as Al or W may be embedded. In that case, about 10 nm of TiN is deposited before embedding as a barrier metal.
[0019]
In the first embodiment, in the manufacture of a MOS transistor, a dummy gate electrode 6 for forming source / drain regions in a self-aligned manner is formed, an interlayer insulating film is deposited after a silicide layer is formed, and a dummy gate electrode is formed by CMP. After the surface is exposed and the dummy gate electrode is removed by etching, impurities are implanted to suppress punch-through, and a high-concentration P-type region is formed in the center of the SOI. Since the cross-sectional shape of the source / drain can be controlled by the high-concentration P-type region in the central portion of the SOI, the electric field near the drain is reduced, impact ionization is suppressed, and the leakage current due to the body floating effect is reduced.
[0020]
In the first embodiment, a method of manufacturing an SOI N-channel MOS transistor in which a MOS transistor is manufactured on a single crystal Si film (SOI) formed on a Si oxide film (BOX) has been described. The present invention is also applicable to the case of manufacturing a MOS transistor on a single crystal Si film.
(2) Embodiment 2
A method for manufacturing an N-channel MOS transistor on a single crystal Si film (SOI) formed on an oxide film according to the second embodiment will be described with reference to FIGS. As in the case of the first embodiment, a method of manufacturing a P-channel MOS transistor can be obtained by replacing the N-type and the P-type in the following description.
[0021]
First, an element isolation region 4 is formed on a SOI substrate in which a Si oxide film (BOX) 2 and a single crystal Si film (SOI) 3 are stacked on a Si substrate 1 by a known trench element isolation method, and then a single crystal Si is formed. A thermal oxide film called a pad oxide film is formed on the surface of the film 3 by thermal oxidation, ion implantation for forming a well and ion implantation for adjusting the threshold value of a transistor are performed, and the pad oxide film is wet-etched with an HF solution. A Si oxide film (first insulating film) 5 serving as a gate insulating film and a polycrystalline Si film serving as a gate electrode 7 are sequentially deposited. Table 5 shows examples of the thickness of the deposited films.
[0022]
[Table 5]
Example of deposited film thickness Single crystal Si film (SOI) of SOI substrate: 100 nm
Si oxide film (BOX) of SOI substrate: 100 nm
Pad oxide film: 8 nm
Si oxide film for gate insulating film: 3.5 nm
Polycrystalline Si film for gate electrode: 150 nm
Subsequently, an etching mask 8 is formed on the polycrystalline Si film using a lithography technique, and the polycrystalline Si film is etched by an RIE method to form a gate electrode 7. After this etching, the resist pattern used as the etching mask 8 is peeled off by a known method.
[0023]
Next, a 5 nm thick Si oxide film (second insulating film) 31 and a 20 nm thick Si nitride film (third insulating film) 32 are sequentially deposited by CVD (chemical vapor deposition) (FIG. 3A )reference). The Si oxide film 31 serves as an etching stopper in the next step of forming a sidewall, and is deposited in a reaction system using TEOS (tetraethyl orthosilicate: Si (OC ₂ H ₅ ) ₄ ) having good step coverage. After the deposition of the Si nitride film 32, the entire surface is etched back to form a first sidewall 33 made of the Si nitride film (see FIG. 3B). Table 6 shows an example of the etch-back conditions for the Si nitride film 32.
[0024]
[Table 6]
Example of nitride film etch-back conditions Gas used: CF ₄ / Ar = 50/950 sccm
Pressure: 105Pa
RF power: 200W
Subsequently, a Si oxide film (fourth insulating film) 34 is deposited, for example, to a thickness of 20 nm (see FIG. 3C), and a second sidewall 35 of an oxide film is formed by etch back (see FIG. 3D). ). At this time, as in the case where the first sidewall 33 is formed, for example, a Si nitride film may be deposited as an etch-back stopper before depositing the Si oxide film 34 to be the second sidewall 35. . Table 7 shows an example of the etch-back condition of the Si oxide film.
[0025]
[Table 7]
Si oxide film etch-back condition Use gas: C ₄ F ₈ / CO / Ar / O ₂ = 9/50/200/5 sccm
Pressure: 4.8 Pa
RF power: 1760W
Next, the oxide film on the surface of the active layer (single-crystal Si film) 3 where the gate electrode 7 and the sidewalls 33 and 35 are not formed is removed by wet etching of the HF solution. Subsequently, the single-crystal Si film 3 is anisotropically etched with, for example, a 15% (weight percent concentration) TMAH (tetramethyl ammonium hydroxide: 4-methylammonium hydroxide) solution to remove the single-crystal Si film 3 by about 30 nm. Then, the portion of the single crystal Si film 3 overlapping with the second sidewall 35 has an oblique shape as shown in FIG. The inner angle θ of this oblique angle is 54.7 ° when the single crystal film 3 has the (100) plane.
[0026]
Next, after removing the second sidewall 35 by wet etching of an HF solution, impurity implantation for forming the S / Ds 37 and 38 is performed by ion implantation 36 using the first sidewall 33 as a mask (FIG. 4 ( e)). In this case, oblique ion implantation and ion implantation for forming the S / D extension region are not performed. In the ion implantation 36, after forming an ion implantation mask with a photoresist by using a lithography technique, N-type impurities are performed under the conditions shown in Table 8, for example. Then, RTA, which is a heat treatment for activating the implanted impurities, is performed, for example, under the conditions shown in Table 9. After the ion implantation, the resist pattern used as a mask is peeled off by a known method.
[0027]
[Table 8]
Example of S / D ion implantation conditions Ion implantation energy for P (phosphorus): 15 keV
Dose amount: 1.2 × 10 ¹⁵ / cm ²
[0028]
[Table 9]
Example of S / D heat treatment (RTA) conditions Temperature: 1000 ° C
Time: 10 seconds FIG. 4E also shows the joint shape between the S / Ds 37 and 38 and the single crystal Si film 3 after RTA, but this joint shape is different from that of the prior art (see FIG. 5C). , Become more smooth. Also, by changing the thickness of the second sidewall 35 and the depth of anisotropic etching of the active layer, the position of the bottom corner b of the S / Ds 37 and 38 can be changed in the left-right direction. The shape inclination can be controlled. In the present invention, the impurities implanted into the S / Ds 37 and 38 by RTA are diffused below the first sidewall 33. This lowers the impurity concentration in the portion a of the S / Ds 37 and 38 near the first sidewall 33 and functions as a diffusion region.
[0029]
Next, a single-crystal Si film 39 of, eg, 30 nm is selectively deposited in the S / D 37 and 38 regions by a known CVD epitaxial growth method (see FIG. 4F).
[0030]
Thereafter, Co silicides 40, 41, and 42 are formed on the S / Ds 37 and 38 on the gate electrode 7 by a known method (see FIG. 4G), and an interlayer film 43 is deposited (see FIG. 4H). A contact hole is formed in the interlayer film 43 so as to communicate with the Co silicides 40, 41, and 42, and a contact and a wiring are formed to manufacture an SOI N-channel MOS transistor.
[0031]
The inventor forms the double sidewalls 33 and 35 as described above, removes the single-crystal Si film 3 by about 30 nm by anisotropic etching, and overlaps the single-crystal Si film 3 with the second sidewall 35. It has been found that punch-through can be suppressed by forming a source / drain by ion-implanting a portion with an inner angle θ.
[0032]
In the second embodiment, in manufacturing a MOS transistor, after forming a double sidewall with a Si nitride film and a Si oxide film, the Si film is subjected to anisotropic etching depending on the plane orientation to form a junction with the second sidewall. Is made oblique, and impurities are implanted into the source / drain. For this reason, the junction shape between the source / drain and the single crystal Si layer can be controlled, so that the electric field near the drain is reduced, impact ionization is suppressed, and the leak current flowing between the source / drain is reduced.
[0033]
In the second embodiment, a method for manufacturing an SOI MOS transistor in which a MOS transistor is formed on a single crystal Si film formed on a Si oxide film has been described. However, a MOS transistor is formed on a normal single crystal Si film. The case is also applicable.
[0034]
【The invention's effect】
According to the first to fifth aspects of the present invention, since the cross-sectional shape of the diffusion layer can be controlled by injecting impurities between the source and the drain, the electric field near the drain is reduced, and impact ionization can be suppressed. Therefore, an increase in leakage current due to the body floating effect of the SOI type MOS transistor can be suppressed, so that low power consumption of the semiconductor device is realized.
[0035]
Further, according to the inventions described in claims 6 to 9, since the junction shape between the source / drain and the single-crystal Si layer can be controlled, the electric field near the drain is alleviated and impact ionization can be suppressed. Therefore, an increase in leakage current due to the body floating effect, which is a problem of the SOI type MOS transistor, can be suppressed, so that the power consumption of the semiconductor device can be reduced.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view (part 1) showing an essential part of an element in each step of a method for manufacturing a semiconductor device according to a first embodiment.
FIG. 2 (Part 2).
FIG. 3 is a schematic cross-sectional view (part 1) showing an essential part of an element in each step of the method for manufacturing a semiconductor device according to the second embodiment.
FIG. 4 (No. 2).
FIG. 5 is a schematic cross-sectional view showing a main part of an element in each step of a method for manufacturing a semiconductor device according to a conventional example.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Si substrate 2 ... Insulating film (BOX) 3 ... Single crystal film (SOI)
DESCRIPTION OF SYMBOLS 4 ... Element isolation region 5 ... Gate oxide film 6 ... Gate electrode (first polycrystalline film) 7 ... Gate electrode 8 ... Resist pattern 10 ... Ion implantation 11, 12 ... Source / drain (S / D) diffusion layer 13 ... Side wall (second insulating film) 14 ... Ion implantation 15, 16 ... Source / drain (S / D) diffusion layer 17 ... Interlayer film 19 ... Third insulating film 21 ... High-concentration impurity implantation layer (punch through stopper)
23 gate electrode (second polycrystalline film)
31 second insulating film 32 third insulating film 33 first side wall 34 fourth insulating film 35 second side wall 37, 38 source / drain 39 single crystal Si 41, 42 , 43… Co Salicide

Claims (9)

In a method of manufacturing a MOS transistor for forming a MOS transistor on a single crystal Si film,
(1) After forming the element isolation, a first insulating film and a first polycrystalline Si film are sequentially deposited on the surface of the single crystal Si film, a resist pattern is formed, and then anisotropic using the resist pattern as a mask. Removing the first polycrystalline Si film by etching and leaving the polycrystalline Si only in a desired region;
(2) implanting impurities into the single-crystal Si film using the first polycrystalline Si as a mask;
(3) After depositing a second insulating film so as to cover the remaining first polycrystalline Si film, the surface of the second insulating film is flattened by polishing, and the surface of the first polycrystalline Si film is removed. Exposing,
(4) selectively removing only the exposed first polycrystalline Si film;
(5) a step of injecting impurities into the single-crystal Si film using the second insulating film as a mask; and (6) removing the first insulating film to form a third insulating film and a second polycrystalline Si film. Sequentially depositing
(7) removing the second polycrystalline Si film on the second insulating film by polishing and leaving the second polycrystalline Si film in a groove where the second insulating film does not exist, and flattening the surface; A method for manufacturing a MOS transistor, comprising: 2. The method according to claim 1, wherein the impurity implantation using the second insulating film as a mask is performed after removing the polycrystalline Si film after the heat treatment of the impurity implantation using the first polycrystalline Si film as a mask. 2. The method for manufacturing a semiconductor device according to claim 1, wherein The impurity implantation using the second insulating film according to claim 1 as a mask is performed so that the concentration becomes 1 × 10 ¹⁸ / cm ³ to 1 × 10 ¹⁹ / cm ^3. The manufacturing method of the semiconductor device described in the above. 2. The semiconductor device according to claim 1, wherein the impurity implantation using the second insulating film according to claim 1 as a mask is performed by implanting a group 3 element for an NMOS or a group 5 element for a PMOS. Manufacturing method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity implantation using the second insulating film as a mask according to claim 1 is an ion implantation method. In a method of manufacturing a semiconductor device in which a MOS transistor is formed on a single crystal Si film,
(1) After forming element isolation, a first insulating film and a polycrystalline Si film are sequentially deposited on the surface of the single crystal Si film, and after forming an etching mask, the polycrystalline Si film is removed by anisotropic etching. Forming a gate electrode while leaving the polycrystalline Si only in a desired region;
(2) After forming the gate electrode, a second insulating film and a third insulating film are sequentially deposited, and the entire surface is etched back to form a first sidewall while leaving the third insulating film on the side of the gate electrode. Process and
(3) after forming the first sidewall, depositing a fourth insulating film, etching back the entire surface, and forming a second sidewall with the fourth insulating film outside the first sidewall; ,
(4) anisotropically etching the single crystal Si film using the gate electrode and the first and second sidewalls as a mask;
(5) removing the second sidewall by etching;
(6) implanting impurities into the etched single-crystal Si film and performing heat treatment to form a source / drain;
And (7) a step of depositing a single-crystal Si film in the source / drain region by epitaxial growth. 7. The semiconductor according to claim 6, wherein the source / drain impurity implantation according to claim 6 is performed after removing the second sidewall after the anisotropic etching of the single crystal Si film. Device manufacturing method. 7. The semiconductor device according to claim 6, wherein the third and fourth insulating films according to claim 6 are deposited using films having different components, and the first and second sidewalls are formed using different films. Manufacturing method. 7. The anisotropic etching of the single crystal Si film according to claim 6, wherein a tip of the lateral etching is a lower part of the second sidewall, preferably a boundary between the first sidewall and the second sidewall. The method for manufacturing a semiconductor device according to claim 6, wherein:

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