JP2004088660A - Photoelectric conversion circuit, parallel-serial conversion device, and optical signal processing device - Google Patents

Abstract

The present invention relates to a photoelectric conversion circuit and an optical signal processing device using the same, and realizes a high-speed photoelectric conversion circuit, a parallel-serial conversion device, and an optical signal processing device that are not limited by the response speed of a photoelectric conversion element or a photoconductive switch.
A photoelectric conversion circuit includes a resistor connected in series between a bias voltage application terminal of a photoelectric conversion element and a bias power supply, and a capacitor connected to the bias voltage application terminal. The time constant of the charge determined by the product _C h · _{R in} the capacitance _{C h} of the capacitor and the resistance value _{R in} the resistance, capacitance _{C h} of the capacitor, the load resistor 14 resistance _{R d,} and the photoelectric conversion element compared to the time constant of the discharge expressed as the light receiving time of the resistance _R with _{on C h · (R on +} R d), is set to be sufficiently larger than 10 times. The capacitance value _{C h} of the capacitor 13 is set to the following sufficiently small value 1 pF.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a photoelectric conversion circuit, a parallel-serial conversion device, and an optical signal processing device, and more particularly, to a photoelectric conversion circuit that converts an optical signal into an electric signal, and converts a parallel electric signal into a high-speed serial electric signal. The present invention relates to an electrical signal parallel-serial converter, an electrical-optical parallel-serial converter for converting a parallel electrical signal into a serial optical signal, and an optical signal processing device used for optical label processing of high-speed optical packets.
[0002]
[Prior art]
As a high-speed response photoelectric conversion device for converting a high-speed optical signal of 10 Gbit / s or more into an electric signal, various semiconductor light receiving elements have been proposed and realized so far.
[0003]
As a specific example, in a pin photodiode, a device has been devised to overcome the limitation of the moving speed of holes in the light absorption layer, which is a main factor that limits the response speed of the semiconductor light receiving element. For example, in a waveguide type photodiode, the light absorption layer is made thinner to reduce the moving distance of holes (for example, see Non-Patent Document 1). An excellent high-speed performance is realized by using only electrons as a carrier to travel by devising (for example, see Non-Patent Document 2).
[0004]
However, these conventional light receiving elements have a problem to be solved in that the manufacturing process is complicated and a special layer structure is required. Furthermore, in these pin-type light receiving elements, even if a bias voltage applied to the light receiving element from the outside is 0 V, an electric signal is output in response to an optical signal incident due to a built-in potential generated inside. . Therefore, a pin-type light receiving element is not suitable for applications in which an input electric signal is used as a bias voltage for a light receiving element to output an electric signal corresponding to the sign of the input electric signal during light irradiation.
[0005]
On the other hand, MSM-PD (Metal-semiconductor-metal Photodiode) does not respond to an optical signal at all when no bias voltage is applied, so that it can be applied to the above-mentioned applications and is extremely easy to manufacture. Having.
[0006]
However, MSM-PD has a long fall time of an optical response output waveform due to low hole mobility, and it is difficult to perform high-speed response. To solve this difficulty, high-speed processing has been realized by introducing a low-temperature growth technique (see, for example, Non-patent Document 3) and a narrow band cap structure. However, these techniques reduce the light receiving sensitivity and complicate the manufacturing process. Cause it.
[0007]
Further, when looking at the entire optical communication system, the demand for faster optical signals is increasing with the rapid increase in data communication, and the transmission rate of the optical signals used in the communication system is 40 Gbit / s in the most advanced region. I'm trying to reach more. However, even when the speed of the transmitted optical signal is increased, the signal processing functions such as the routing and the memory are currently implemented by a silicon-based LSI, so that the high-speed optical signal and the operation speed are 1 Gbit / s. An optical-to-electrical serial-to-parallel converter, an electrical-to-optical parallel-to-serial converter, and a clock generator which are interfaces with a silicon-based LSI (large-scale integrated circuit) of s or less are essential. The electro-optical parallel-serial conversion for converting a low-speed electric signal into a high-speed optical signal is roughly classified into an optical parallel-serial conversion after an E / O conversion (electric-optical conversion) of a low-speed electric signal. Conversion to generate a high-speed optical signal (see FIG. 7A) or parallel-to-serial conversion of an electric signal into a high-speed electric signal, and then perform E / O conversion to generate a high-speed optical signal. (See FIG. 7B).
[0008]
The former method shown in FIG. 7A has the advantage that high-speed performance is not required for the electronic circuit, but requires a number of optical modulators 73 equal to the number of bits, which increases the size of the device. In addition, there is a problem to be solved in that the loss of an optical signal due to optical demultiplexing and optical multiplexing is large.
[0009]
In the latter method shown in FIG. 7B, the speed of the serial optical signal is limited by the operation speed of the electronic circuits 78 and 79, and therefore, it is considered that the limit is about 40 Gbit / s. Further, when performing parallel-serial conversion from an electric signal of several tens to several hundreds of Mbit / s to an electric signal of a 40 Gbit / s class by using an InP or GaAs high-speed electronic circuit technology, it is divided into several stages to sequentially increase the speed. It is expected that the overall power consumption will be considerably increased. Moreover, in the conventional clock extraction using an electronic circuit, it is necessary to apply feedback by a PLL (Phase Locked Loop) and lock the oscillation frequency of a VCO (Voltage-Controlled Oscillator). It is not possible for burst signals.
[0010]
In packet communication, which is an example of a high-speed optical communication system, label processing of high-speed optical packets is performed, and as a method of controlling a packet transmission destination, optical serial-parallel conversion is performed on an optical label, and after photoelectric conversion, A method in which an electronic circuit performs label recognition on a bit-by-bit basis and performs processing (for example, see Non-Patent Document 4); a method in which a local optical address signal is generated in a node; There is a method of performing processing by judging only using an optical logic gate (comparison type: see Non-Patent Document 5, for example).
[0011]
The latter comparison type is not suitable for complicated label processing as compared with the former, but the simple label processing such as the case of controlling only packet bypass / drop at the node is called simplification of the device configuration. There are advantages. However, the comparison-type label processing method reported so far uses an optical logic gate, so that high-speed operation is possible, but there are restrictions on polarization, signal strength, etc., and the apparatus is not necessarily simple. Not really. Further, considering the dynamic change of the local optical address, there is a disadvantage that the same number of optical modulators as the number of address bits are required.
[0012]
[Non-patent document 1]
J. E. FIG. Bowers et al. , "High-speed zero-bias waveguide photodetectors," Electron. Lett. , Vol. 22, p. 905 (1986)
[0013]
[Non-patent document 2]
T. Ishibashi et al. , "InP / InGaAs Uni-Traveling-Carrier Photodiodes,"
IEICE Trans. Electron. , Vol. E83-C, no. 6, p. 938 (2000)
[0014]
[Non-Patent Document 3]
R. Takahashi et al. , "Ultrafast 1.55-um photoresponse in
low-temperature-grown InGaAs / InAlAs quantum wells, "
Appl. Phys. Lett. , Vol. 65, No. 14, p. 1790 (1994)
[0015]
[Non-patent document 4]
T. Nakahara et al. , "100-Gbit / s optical-packet self-routing by self
serial-to-parallel conversion, "
Proc. OFC 2002, WE5, p. 266 (2002)
[0016]
[Non-Patent Document 5]
D. Cotter et al. , "Self-routing of 100 Gb / s packets using 6 bits
keyword address recognition, "
Electron. Lett. , Vol. 31, p. 1475 (1995)
[0017]
[Problems to be solved by the invention]
Accordingly, a first object of the present invention is to achieve a photoelectric conversion circuit capable of high-speed response with a simple configuration that does not require a special layer structure or a complicated manufacturing process in order to solve the above-described problems of the conventional technology. Is to do.
[0018]
Further, a second object of the present invention is to provide an electric signal parallel-serial conversion device capable of responding to a burst signal with high speed, low power consumption and a simple circuit configuration in order to solve the above-mentioned problems of the prior art. Is to make it happen.
[0019]
Further, a third object of the present invention is to solve the above-mentioned problems of the prior art by using an electro-optical parallel type which has a simple device configuration but can flexibly cope with high speed and multi-bit. -To realize a serial conversion device.
[0020]
Further, a fourth object of the present invention is to solve the above-mentioned problems of the prior art, so that a special condition is not required for an optical packet signal, and a simple device configuration can cope with a dynamic change of a local address. Another object of the present invention is to realize an optical signal processing device suitable for a comparative label processing device.
[0021]
Further, a fifth object of the present invention is to solve the above-mentioned problems of the prior art, while achieving a high-speed, multi-bit, and dynamic change of a local address while having a simple device configuration. An object of the present invention is to realize an optical signal processing device suitable for a comparative label processing device.
[0022]
[Means for Solving the Problems]
The configuration of the present invention that achieves the above object has the following features.
[0023]
The photoelectric conversion circuit for achieving the first object has a resistor connected in series between a bias voltage application terminal of the photoelectric conversion element and a bias power supply, and a capacitor connected to the bias voltage application terminal. .
[0024]
Here, preferably, the capacitance value C of the capacitor _h And the resistance value R of the resistor _in With product C _h ・ R _in Is compared with the charging time constant determined by _h , A resistance value R of a load resistor connected in parallel with the output terminal to the photoelectric conversion element. _d And the resistance R of the photoelectric conversion element at the time of receiving light. _on Using C _h ・ (R _on + R _d ) So that the time constant of the discharge, which can be expressed as _in To the above (R _on + R _d ) Is set to a sufficiently large value that is at least 10 times as large as that in the case of ()).
[0025]
Further, preferably, the C _h Is set to a sufficiently small value of 1 pF or less, the time constant C _h ・ (R _on + R _d ) Is set smaller.
[0026]
Preferably, the bias power supply may be replaced with an input signal source, and the photoelectric conversion element may be replaced with a photoconductive switch that performs a switching operation in response to light pulse irradiation.
[0027]
As an electric signal parallel-serial converter for achieving the second object, k capacitors for accumulating k parallel electric signals as electric charges, and k resistors connected in series to respective signal input terminals are provided. An optical demultiplexer including: k photoconductive switches for discharging electric charges stored in the capacitor; and an optical delay device for delaying a light trigger pulse by one bit and sequentially demultiplexing the phototrigger pulses to the k photoconductive switches. And a container.
[0028]
Here, preferably, the capacitance value C of the capacitor _h And the resistance value R of the resistor _in With product C _h ・ R _in Is compared with the charging time constant determined by _h , A resistance value R of a load resistor connected to the output side of the photoconductive switch. _d And the resistance R of the photoconductive switch when receiving light. _on Using C _h ・ (R _on + R _d ) So that the time constant of the discharge, which can be expressed as _in To the above (R _on + R _d ) Is set to a sufficiently large value that is at least 10 times as large as that in the case of ()).
[0029]
Further, preferably, the C _h Is set to a sufficiently small value of 1 pF or less, the time constant C _h ・ (R _on + R _d ) Is set smaller.
[0030]
As an electro-optical parallel-serial converter for achieving the third object, m (m = k / n) sets of electric signal parallels for converting k parallel electric signals into serial electric signals in units of n. A serial converter, an optical pulse light source, an optical demultiplexer that branches an optical signal output from the optical pulse light source into m signals, and the m parallel optical signals demultiplexed by the optical demultiplexer. m optical modulators that modulate with m sets of parallel electrical signals output from the m sets of electrical signal parallel-serial converters, and m parallel optical signals on the input side or output side of the m optical modulators An optical delay unit that delays the parallel optical signal by one bit, and a multiplexer that combines the m parallel optical signals that have passed through the optical modulator and the optical delay unit into one optical pulse train to form a serial optical signal. And said m sets of electrical signal parallel-to-serial converters Each includes n capacitors for storing n parallel electric signals as electric charges, n resistors connected in series to respective signal input terminals, and n capacitors for discharging the electric charges stored in the capacitors. A photoconductive switch; and an optical duplexer including an optical delay device that delays the optical trigger pulse by one bit and sequentially splits the light into the n photoconductive switches.
[0031]
Here, preferably, the capacitance value C of the capacitor _h And the resistance value R of the resistor _in With product C _h ・ R _in Is compared with the charging time constant determined by _h , A resistance value R of a load resistor connected to the output side of the photoconductive switch. _d And the resistance R of the photoconductive switch when receiving light. _on Using C _h ・ (R _on + R _d ) So that the time constant of the discharge, which can be expressed as _in To the above (R _on + R _d ) Is set to a sufficiently large value that is at least 10 times as large as that in the case of ()).
[0032]
Further, preferably, the C _h Is set to a sufficiently small value of 1 pF or less, the time constant C _h ・ (R _on + R _d ) Is set smaller.
[0033]
As the optical signal processing device for achieving the fourth object, the electric signal parallel-serial conversion device for converting a parallel electric signal into a serial electric signal, an optical splitter for splitting an optical signal, and the optical splitter An optical modulator that modulates one of the optical signals demultiplexed by the optical modulator with an output signal of the electric signal parallel-serial conversion device, and outputs a control signal depending on the presence or absence of an optical output from the optical modulator. A control circuit; and an optical switch to which the other optical signal demultiplexed by the optical demultiplexer is input and an output port is controlled by the control signal.
[0034]
As the optical signal processing device for achieving the fifth object, the electro-optical parallel-serial conversion device for converting a parallel electric signal into a serial optical signal, an optical splitter for splitting an optical signal, An optical logic gate that gates one of the optical signals demultiplexed by the optical demultiplexer with an output signal of the electro-optical parallel-serial converter, and control depending on the presence or absence of optical output from the optical logic gate A control circuit that outputs a signal; and an optical switch to which the other optical signal demultiplexed by the optical demultiplexer is input and an output port is controlled by the control signal.
[0035]
Here, the optical signal processing apparatus may be used as an optical packet router.
[0036]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0037]
(1st Embodiment)
FIG. 1 shows a configuration of a photoelectric conversion circuit according to a first embodiment of the present invention. In FIG. 1, reference numeral 11 denotes a photoelectric conversion element, and 12 denotes a resistance value R. _in , 13 is the capacitance C _h , The capacitor 14 has a resistance value R _d , A bias power supply, 16 a bias voltage application terminal, and 17 an output terminal. Each terminal of the input-side capacitor 13 and the output-side load resistor 14 is grounded or connected to an external circuit (not shown).
[0038]
The resistor 12 is connected in series between the bias voltage application terminal 16 and the bias power supply 15. Further, a capacitor 13 is also connected to the terminal 16. At this time, the capacitor 13 is charged by the voltage applied from the bias power supply 15, but the charging time constant is C _h ・ R _in It is. On the other hand, when the photoelectric conversion element 11 is irradiated with a light pulse, the resistance of the photoelectric conversion element 11 decreases due to the photoconductive effect, and the charge stored in the capacitor 13 flows through the load resistor 14 and is discharged. Is the capacitance C of the capacitor 13 _h , The resistance value R of the resistor 14 _d , And the resistance R of the photoelectric conversion element 11 when receiving light _on Using C _h ・ (R _on + R _d ).
[0039]
Where R _in To (R _on + R _d If the value is set to a sufficiently large value which is 10 times or more as compared with the value of), the time constant of charging becomes sufficiently large as compared with the time constant of discharging. Therefore, it is considered that charging is not performed from the start of discharging to the end of discharging. I can do it. That is, the response speed of the electric pulse generated by the incidence of the light pulse is the discharge time constant C _h ・ (R _in + R _d ). Capacitance C of capacitor 13 _h Is set to a sufficiently small value of 1 pF (picofarad) or less, so that the time constant C _h ・ (R _on + R _d If the value of () is reduced, a photoelectric conversion circuit capable of high-speed response without being limited by the response speed of the photoelectric conversion element 11 can be realized.
[0040]
As described above, in the present embodiment, the resistor 12 and the capacitor 13 are connected to the bias voltage application terminal 16 of the photoelectric conversion element 11 as a photoelectric conversion circuit, and the time constant of charging determined by the resistor 12 and the capacitor 13 Since the time constant is set to be sufficiently larger than the time constant by 10 times or more, a high-speed photoelectric conversion circuit that is not limited by the photoelectric conversion element 11 can be realized.
[0041]
(Second embodiment)
FIG. 2 shows a configuration of a photoelectric conversion circuit according to a second embodiment of the present invention. In FIG. 2, 11A is a photoconductive switch, and 12A is a resistance value R. _in , 13A is the capacitance C _h , The capacitor 14A has a resistance value R _d , 15A is an input signal source, 16A is a bias voltage application terminal, and 17A is an output terminal. Each terminal of the input-side capacitor 13A and the output-side load resistor 14A is grounded or connected to an external circuit (not shown). In the present embodiment, the bias power supply 15 in the first embodiment is replaced with an input signal source 15A.
[0042]
As in the first embodiment, R _in To (R _on + R _d ) Is set to a sufficiently large value that is at least 10 times as large as the capacitance value of the capacitor 13A. _h And the resistance R of the resistor 12A _in With product C _h ・ R _in The capacitance value C of the capacitor 13A is compared with the charging time constant determined by _h , The resistance value R of the resistor 14A _d And the resistance R of the photoconductive switch 11A when receiving light. _on Using C _h ・ (R _on + R _d ) Is set so that the time constant of the discharge which can be expressed as) is sufficiently small. Here, from the input signal source 15A, the “0” level is the voltage 0V and the “1” level is the voltage V _b A signal of Y bit / s, which is V, is input, and a light pulse having a repetition frequency of YHz is irradiated to the photoconductive switch 11A.
[0043]
1 / Y is C _h ・ R _in When the input signal is "1", the photoconductive switch 11A is irradiated with a light pulse while the input signal is "1", so that an electric pulse is output from the output terminal 17A. When the input signal is "0", the capacitor 13A is not charged, and the light pulse is emitted in a state where no bias voltage is applied to the photoconductive switch 11A. Therefore, no electric pulse is output to the output terminal 17A. That is, an electrical pulse corresponding to the input electrical signal is output from the output terminal 17A.
[0044]
Also in this embodiment, as in the first embodiment described above, a resistor 12A and a capacitor 13A are connected to a bias voltage application terminal 16A of a photoconductive switch 11A as a photoelectric conversion circuit, and charging is determined by the resistor 12A and the capacitor 13A. Since the constant is set to be sufficiently larger than the discharge time constant by a factor of 10 or more, it is possible to realize a circuit in which a high-speed electric pulse that is not limited by the photoconductive switch 11A is output in response to an input signal.
[0045]
(Third embodiment)
FIG. 3 shows a configuration of an electric signal parallel-serial converter according to a third embodiment of the present invention. In FIG. 3, 31 is a k (k is an integer of 2 or more) photoconductive switches, 32 is a k resistor, 33 is a k capacitor, 34 is a load resistor, and 35 is an optical component including an optical delay unit. It is a wave device. This device is a device that generates k-bit Ybit / s serial electric signals by bundling k parallel electric signals. Each terminal of the input-side capacitor 33 and the output-side load resistor 34 is grounded or connected to an external circuit (not shown). The circuit portions 31 to 33 in FIG. 3 have a configuration in which the corresponding circuit portions in FIG. 2 are connected in parallel, and similar effects can be obtained as described later.
[0046]
The k capacitors 33 are charged by the k parallel electric signals. Further, the optical trigger pulse is split into k light splitters by the optical splitter 35, a delay of 1 / Y second is given, and these are sequentially irradiated on the k photoconductive switches 31. The accumulated charges are sequentially discharged, and are converted by the load resistor 34 into a Y-bit / s electric pulse train signal in which k pulses are continuous.
[0047]
In this embodiment, similarly to the above-described second embodiment, the resistor 32 and the capacitor 33 are connected to the bias voltage application terminals of the respective photoconductive switches 32, and the charging time constant determined by the resistor 32 and the capacitor 33 is: The electric signal parallel-to-serial converter is capable of converting a parallel electric signal of several hundred Mbit / s from DC (direct current) to 40 Gbit / s or more, since the electric signal parallel-serial converter is designed to be sufficiently larger than 10 times the discharge time constant. Not only can it be directly converted into a high-speed serial electric signal, but it does not require a power supply to the device other than the input parallel electric signal, and consumes extremely low power. Further, it can be operated for irradiation of a burst-like light trigger pulse.
[0048]
(Fourth embodiment)
FIG. 4 shows a configuration of an optical packet address processing apparatus according to a fourth embodiment of the present invention. 4, reference numeral 41 denotes an electric signal parallel-serial converter having the same configuration as in FIG. 3, reference numeral 42 denotes an optical modulator, reference numeral 43 denotes a control device, and reference numeral 44 denotes an optical switch. The optical packet has a signal speed of Ybit / s and is composed of a k-bit optical label followed by a payload. This device is a device that determines whether the optical label and the local address match or not, and controls the output port of the optical packet.
[0049]
The k-bit local address is input to the electric signal parallel-serial converter 41 as k parallel (parallel) electric signals, and is converted into a k-bit serial electric signal having a signal speed of Ybit / s. Is input to
[0050]
On the other hand, the optical packet is divided into two paths by an optical demultiplexer (not shown). One is input to the optical modulator 42 and the other is input to the optical switch 44. Here, the optical modulator 42 is set to be opened when the input electric signal is “0” and closed when the input electric signal is “1”. Further, the number of “1” included in the optical label and the number of “1” included in the local address are the same. Under this condition, when the optical label and the local address match, no optical signal is output from the optical modulator 42, and only when the two do not match, an optical signal of 1 bit or more is output from the optical modulator 42. Is output.
[0051]
The output optical signal from the optical modulator 42 is input to the control device 43. When the optical signal is input, the control device 43 sends a control signal for setting the output port of the optical switch 44 to the port A to the optical switch 44, When no signal is input, a control signal for setting the output port of the optical switch 44 to port B is sent to the optical switch 44.
[0052]
An optical packet is input to the optical switch 44 via the other path branched by the optical demultiplexer (not shown), and the optical packet is output to a port corresponding to the control signal. That is, when the optical label and the local address do not match, the optical packet is output to port A, and when the optical label and the local address match, the optical packet is output to port B.
[0053]
Here, by using the electric signal parallel-serial conversion device described in the third embodiment as the electric signal parallel-serial conversion device 41, a very simple configuration, low power consumption, and dynamic Thus, it is possible to realize a comparative label processing apparatus which can easily cope with various changes.
[0054]
(Fifth embodiment)
FIG. 5 shows the configuration of an electro-optical parallel-serial converter according to a fifth embodiment of the present invention. As described in the section of the prior art, a conventional electro-optical parallel-serial of a type that generates a high-speed optical signal by performing E / O conversion after converting an electric signal from parallel to serial to a high-speed electric signal. In the conversion device, the number of optical modulators equal to the number k of parallel signals is required. Therefore, there is a problem that the size of the device is increased and loss due to multiplexing and demultiplexing of the optical signal is caused. Therefore, in the present embodiment, when k is large, k parallel electric signals are bundled in units of n to generate m parallel electric signals (k = n × m), and m optical modulators are generated. Thus, a k-bit optical serial signal is generated. As a result, the number of required optical modulators can be significantly reduced (1 / n).
[0055]
In FIG. 5, 50 is an optical demultiplexer including an optical delay device, 51 is n photoconductive switches, 52 is n resistors, 53 is n capacitors, and 54 is a load resistor. Thus, an electric signal parallel-serial converter that generates an n-bit Ybit / s serial electric signal by bundling n parallel electric signals is configured. This electric signal parallel-serial converter has the same circuit configuration as that of FIG. 3 described in the third embodiment of the present invention, and charges n capacitors 53 with n parallel electric signals. Furthermore, the light trigger pulse is split into n light splitters by the light splitter 50, and the light accumulated in each capacitor 53 is sequentially turned on by giving a delay of 1 bit to the n photoconductive switches 51 sequentially. After the discharge, the load resistor 54 converts the n pulses into a continuous electric pulse train signal.
[0056]
In this way, m electric pulse train signals in which n pulses are obtained are prepared in parallel, and the m electric pulse trains are input to the optical modulator 57. After being output from the optical pulse light source 55, the optical modulator 57 receives an n-bit optical pulse train branched into m lines by the optical demultiplexer 56. Modulated by a pulse train. The output optical signals from the m optical modulators 57 are delayed by an optical delay unit 58 and further bundled into one optical pulse train by an optical multiplexer 59 to generate a k-bit optical serial signal.
[0057]
Here, the circuit portion including the optical pulse light source 55, the optical demultiplexer 56, the optical modulator 57, the optical delay device 58, and the optical multiplexer 56 according to the present embodiment is the same as that shown in FIG. Although the configuration is the same as that of the conventional circuit shown in FIG. 7, k parallel electric signals are directly input to the optical modulator 73 of FIG. As described above, since m electric pulse trains each including m electric pulse train signals in which n pulses are continuous are input to the modulator 57, the number of optical modulators 57 is reduced to 1 / n. For example, when k = 64, n = 8, and m = 8, the number of optical modulators 57 can be drastically reduced from 64 in the related art to eight.
[0058]
Here, the light trigger pulse and the light pulse light source 55 used in the electric signal parallel-serial conversion unit are separately described, but a part of the output of the light pulse light source 55 branched by the light splitter 56 is used as the light trigger pulse. It is also possible to use.
[0059]
(Sixth embodiment)
FIG. 6 shows a configuration of an optical packet address processing apparatus according to a sixth embodiment of the present invention. In FIG. 6, reference numeral 61 denotes an electro-optical parallel-serial converter having a configuration similar to that of FIG. 5 described in the fifth embodiment, and 62 denotes an optical logic gate (for example, one using four-wave mixing). And 63 using a cross phase modulation type wavelength conversion), 63 is a control device, and 64 is an optical switch. An optical packet is composed of a k-bit optical label followed by a payload at a signal rate of Ybit / s. This device is a device that determines whether the optical label and the local address match or not, and controls the output port of the optical packet.
[0060]
The k-bit local address is input to the electro-optical parallel-serial converter 61 as k parallel electric signals, and is converted into a k-bit serial optical signal having a signal speed of Ybit / s. Will be entered. On the other hand, the optical packet is divided into two paths by an optical demultiplexer (not shown). One is input to the optical logic gate 62 and the other is input to the optical switch 64.
[0061]
Here, the optical logic gate 62 does not output the optical signal when the input optical signals to the two input ports match (both "0" or both "1"), and the input to the two input ports If the optical signals are different (only one is "1"), the optical signal is output. Further, the number of “1” included in the optical label of the optical packet is the same as the number of “1” included in the local addresses of the k parallel electric signals. Under this condition, when the optical label and the local address match, no optical signal is output from the optical logic gate 62, and only when the two do not match, an optical signal of 1 bit or more is output from the optical logic gate 62. Is output.
[0062]
The output optical signal from the optical logic gate 62 is input to the control device 63. When the optical signal is input, the control device 63 sends a control signal to the optical switch 64 with the output port of the optical switch 64 as the port A, When no signal is input, a control signal for setting the output port of the optical switch 64 to port B is sent to the optical switch 64. An optical packet is input to the optical switch 64 through the other path branched by the optical demultiplexer (not shown), and the optical packet is output to a port corresponding to the control signal. That is, when the optical label and the local address do not match, the optical packet is output to port A, and when the optical label and the local address match, the optical packet is output to port B.
[0063]
Here, by using the electro-optical parallel-serial converter of FIG. 5 described in the fifth embodiment of the present invention as the electro-optical parallel-serial converter 61, a high-speed multi-bit optical label can be obtained. A comparison-type label processing apparatus that can perform processing and can easily cope with dynamic changes in local addresses can be realized.
[0064]
(Other embodiments)
The present invention is not limited to the above-described embodiment of the present invention, and replacement with a substitute having a similar function, a change within the scope of the claims, a combination, and the like are also included in the embodiment of the present invention. Of course.
[0065]
【The invention's effect】
As described in detail with the above embodiments, according to the present invention, a high-speed response that is not limited by the moving speed of holes in a photoelectric conversion element can be achieved by simply adding a simple circuit to a photoelectric conversion element having a conventional structure. A photoelectric conversion circuit is realized.
[0066]
Further, according to the present invention, it is possible to configure an electric signal parallel-serial converter and an electric-optical parallel-serial converter that are low power consumption, simple and compact, and can also handle burst signals. It becomes.
[0067]
Further, according to the present invention, it is possible to realize a comparison type label processing apparatus which can easily cope with high speed, multi-bit, and dynamic change of a local address with a simple configuration.
[Brief description of the drawings]
FIG. 1 is a circuit diagram illustrating a configuration of a photoelectric conversion circuit according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating a configuration of a photoelectric conversion circuit according to a second embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating a configuration of an electronic signal parallel-serial conversion device that performs parallel-serial conversion of an electric signal according to a third embodiment of the present invention.
FIG. 4 is a block diagram illustrating a configuration of an optical signal processing device that performs label processing of an optical packet according to a fourth embodiment of the present invention.
FIG. 5 is a circuit diagram showing a configuration of an electro-optical parallel-serial converter according to a fifth embodiment of the present invention.
FIG. 6 is a block diagram illustrating a configuration of an optical signal processing device (address processing device) that performs label processing of an optical packet according to a sixth embodiment of the present invention.
7A and 7B are a configuration diagram (a) and a block diagram (b) showing a configuration example of a conventional electro-optical parallel-serial converter.
[Explanation of symbols]
11 photoelectric conversion element
11A Photoconductive switch
12,12A resistance
13,13A Capacitor (capacitance)
14,14A Load resistance
15 Bias power supply
15A signal source
16, 16A Bias voltage application terminal
17, 17A output terminal
31 Photoconductive switch
32 resistance
33 Capacitor
34 Load resistance
35 Optical demultiplexer including optical delay unit
41 Electric signal parallel-serial converter
42 optical modulator
43 Control device
44 Optical switch
50 Optical demultiplexer including optical delay device
51 Photoconductive switch
52 resistance
53 capacitor
54 Load resistance
55 light pulse light source
56 Optical splitter
57 optical modulator
58 Optical delay unit
59 Optical multiplexer
61 Electric-optical parallel-serial converter
62 Optical Logic Gate
63 control unit
64 optical switch
71 Optical pulse light source
72 Optical splitter
73 optical modulator
74 Optical delay unit
75 Optical multiplexer
76 light source
77 optical modulator
78 Electric signal parallel-serial converter
79 Electric clock signal generator

Claims (13)

In a photoelectric conversion circuit that converts an optical signal into an electric signal,
A resistor connected in series between a bias voltage application terminal of the photoelectric conversion element and a bias power supply,
A photoelectric conversion circuit comprising: a capacitor connected to the bias voltage application terminal. Compared to the time constant of the charging determined by the product C _h · R _in the resistance R _in of the capacitive value C _h of the capacitor resistor, and an output terminal capacitance C _h of the _capacitor, to said photoelectric conversion element resistance R _d of the connected load resistor in _parallel, and as _{C h · (R on + R} d) and expressed the time constant of the discharge is sufficiently small by the resistance R _on during reception of said photoelectric conversion elements, 2. The photoelectric conversion circuit according to claim 1, wherein the R _in is set to a value that is at least ten times as large as the value of (R _on + R _d ). 3. Wherein C _h a by setting the following sufficiently small value 1 pF, the time constant C _h · photoelectric conversion circuit according to claim 2, characterized in that the smaller the value of _(R on ₊ R _d). 4. The device according to claim 1, wherein the bias power supply is replaced with an input signal source, and the photoelectric conversion element is replaced with a photoconductive switch that performs a switching operation in response to irradiation of a light pulse. Photoelectric conversion circuit. In an electric signal parallel-serial converter for converting a parallel electric signal into a serial electric signal,
k capacitors for storing k parallel electric signals as electric charges;
K resistors connected in series to each signal input terminal;
K photoconductive switches for discharging the electric charge stored in the capacitor,
An optical demultiplexer including an optical delay device that delays an optical trigger pulse by one bit and sequentially demultiplexes the light trigger pulse to the k photoconductive switches. Compared to the time constant of the charging determined by the product C _h · R _in the resistance R _in of the capacitive value C _h of the capacitor resistance, capacitance C _h of the _capacitor, to the output side of the photoconductive switch as _{C h · (R on + R} d) and expressed the time constant of the discharge with the connected load resistance of the resistance value R _d, and resistance R _on during reception of the photoconductive switch is sufficiently small, the R It said _{in (R on +} R _d) electrical signals according to claim 5, characterized in that set to 10 times or more of a sufficiently large value compared to the parallel - serial converter. Wherein C _h a by setting the following sufficiently small value 1 pF, electrical signals according to claim 6, characterized in that the smaller the value of the time constant _{C h · (R on + R} d) Parallel - Serial Conversion device. m (m = k / n) sets of electric signal parallel-serial converters for converting k parallel electric signals into serial electric signals in units of n;
An optical pulse light source,
An optical demultiplexer that branches an optical signal output from the optical pulse light source into m signals,
M optical modulators for modulating m parallel optical signals demultiplexed by the optical demultiplexer with m sets of parallel electric signals output from the m sets of electric signal parallel-serial converters,
An optical delay unit that delays the m parallel optical signals by one bit at an input side or an output side of the m optical modulators;
A multiplexer that multiplexes the m parallel optical signals that have passed through the optical modulator and the optical delay into a single optical pulse train to form a serial optical signal; Each of the serial converters
n capacitors for storing the n parallel electric signals as electric charges;
N resistors connected in series to each signal input terminal;
N photoconductive switches for discharging the charge stored in the capacitor;
An electro-optical parallel-serial conversion device, comprising: an optical demultiplexer including an optical delay device that delays an optical trigger pulse by one bit and sequentially demultiplexes the light trigger pulse to the n photoconductive switches. Compared to the time constant of the charging determined by the product C _h · R _in the resistance R _in of the capacitive value C _h of the capacitor resistance, capacitance C _h of the _capacitor, to the output side of the photoconductive switch as _{C h · (R on + R} d) and expressed the time constant of the discharge with the connected load resistance of the resistance value R _d, and resistance R _on during reception of the photoconductive switch is sufficiently small, the R It said _in electrical of claim 8, wherein the set to a sufficiently large value of more than 10 times that of _{(R on +} R _d) - light-type parallel - serial converter. Wherein C _h a by setting the following sufficiently small value 1 pF, electrically according to claim 9, characterized in that smaller values of the time constant _{C h · (R on + R} d) - Light-type parallel A serial converter. An electric signal parallel-serial conversion device according to any one of claims 5 to 7, which converts the parallel electric signal into a serial electric signal.
An optical splitter for splitting an optical signal,
An optical modulator that modulates one of the optical signals split by the optical splitter with an output signal of the electric signal parallel-serial converter,
A control circuit that outputs a control signal depending on the presence or absence of an optical output from the optical modulator,
An optical switch, to which the other optical signal demultiplexed by the optical demultiplexer is input and an output port is controlled by the control signal. An electro-optical parallel-serial converter according to any one of claims 8 to 10, which converts a parallel electric signal into a serial optical signal.
An optical splitter for splitting an optical signal,
An optical logic gate that gates one of the optical signals split by the optical splitter with an output signal of the electro-optical parallel-serial converter;
A control circuit that outputs a control signal depending on the presence or absence of optical output from the optical logic gate,
An optical switch, to which the other optical signal demultiplexed by the optical demultiplexer is input and an output port is controlled by the control signal. 13. The optical signal processing device according to claim 11, wherein the optical signal processing device is used for an optical packet router.

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