JP2004085693A - Method of driving plasma display panel and plasma display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of driving a plasma display panel and a plasma display for stabilizing display by reducing deviation of an electric charge. <P>SOLUTION: When interlace type display is performed with a PDP having an electrode array where two adjacent lines share one display electrode, a reset discharge is generated as a reset or part of the reset which serves as preparation of addressing only in the line used for display in the most recent sustaining. Two steps of wall electric charge control causing a reset discharge only in the other line thereafter are included in a driving sequence. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a driving method of a plasma display panel (PDP) and a plasma display device for displaying an image using the plasma display panel.
[0002]
Plasma display devices are becoming widespread as large-screen television receivers. In order to promote the spread, improvements in display performance and overall operation performance are being promoted.
[0003]
[Prior art]
In an AC PDP, a display electrode for generating a display discharge that determines the amount of light emitted from a cell is covered with a dielectric, and a wall voltage (wall charge) generated by charging the dielectric is used for the display discharge. At the time of display, addressing for controlling the wall voltage of each cell is performed in accordance with the image data, and then sustaining is performed to generate display discharges the number of times corresponding to the brightness to be displayed. The discharge in the cell is generated by an electric field applied to the cell due to a voltage applied to each electrode and wall charges.
[0004]
A typical AC PDP for color display has a surface discharge structure. The surface discharge structure referred to here is a structure in which display electrodes are arranged in parallel on a front substrate or a rear substrate. There are Form A and Form B in the surface discharge structure. In the form A, a pair of display electrodes is arranged for each row of the matrix display. The total number of display electrodes is twice the number n of rows. Mode B is a mode in which display electrodes of the number obtained by adding 1 to the number n of rows are arranged at equal intervals (intervals at which discharge can occur between adjacent electrodes) at a rate of 3 in 2 rows. It is suitable for high definition (reduction of line pitch) and high resolution (increase of the number of lines). In the form B, the display electrodes except for both ends of the array are common to two adjacent rows.
[0005]
With the PDP adopting the mode B, an interlaced display in which one frame is divided into an odd field and an even field is performed. The PDP uses only odd lines on the screen to display odd fields, and uses only even lines to display even fields. Since the cell of the PDP is a binary light emitting element, each of the odd field and the even field is displayed by being replaced with a plurality of subfields in order to reproduce the gradation. Reset, addressing, and sustain are performed for each subfield. The reset is a driving process for equalizing wall voltages of all the cells constituting the display surface in preparation for addressing. In recent years, instead of erasing the wall charge and setting the wall voltage to zero, it is becoming common to perform charge adjustment (also referred to as charge rearrangement) to generate a wall voltage suitable for addressing.
[0006]
In the reset of the conventional driving method, voltage is applied to each electrode so that the same electric field is applied to all cells at once without distinguishing between odd-numbered rows and even-numbered rows so that reset discharge occurs in all cells. Was applied.
[0007]
[Problems to be solved by the invention]
By causing the reset discharge to occur in all the cells at once as described above, the operation conditions of all the cells are normally made and the subsequent operation is usually stabilized. However, in the conventional reset, although the amount of charge in each cell can be changed, the imbalance between the positive charge and the negative charge in the cell caused by the charge transfer between the cells cannot be eliminated. In driving an AC type PDP, although it is desirable that the positive charge and the negative charge in each cell be the same amount or both zero, the positive charge is generated due to the charge transfer between adjacent cells in addressing and sustain. There may be more than negative charges, or conversely, more negative charges than positive charges. Such bias of electric charge may be eliminated by accident as the display is continued, or may gradually increase. Which one depends on the contents of the display.
[0008]
Conventionally, there has been a problem that the operation becomes abnormal in a cell in which the bias of the charge has excessively advanced. Excessive discharge occurred during resetting, and background light emission, which reduced display contrast, became strong. Discharge for addressing did not occur, or unnecessary display discharge occurred. An object of the present invention is to stabilize display by reducing bias of electric charges.
[0009]
[Means for Solving the Problems]
In the present invention, when performing interlaced display by a PDP having an electrode array in which two adjacent rows share one display electrode, the immediately preceding sustain as a reset or a part of the reset in preparation for addressing. In the driving sequence, a two-stage wall charge control in which a reset discharge is generated only in the row used for display and a reset discharge is generated only in the other rows thereafter (this is called a special reset) is incorporated. The first stage reset discharge reduces wall charges. If there is a bias in the charge at the start of the discharge, a certain amount of bias in the charge remains after the end of the discharge. When the cell in which the discharge occurs is a cell between the positively-charged cell and the negatively-charged cell, the excessive charge is neutralized by the second-stage reset discharge, and the bias of the charge is reduced.
[0010]
The special reset is not necessarily performed for each field, and may be performed once for two or more set fields. Appropriate settings can be made for the implementation time.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a configuration diagram of a display device according to the present invention. The display device 100 includes a surface-discharge type PDP 1 having a display surface capable of color display of m × n cells and a drive unit 70 for controlling light emission of the cells. It is used as a monitor for computer and computer system.
[0012]
In the PDP 1, display electrodes X and Y forming an electrode pair for causing a display discharge are arranged in parallel, and address electrodes A are arranged so as to intersect the display electrodes X and Y. The display electrodes X and Y extend in the horizontal direction, and the address electrodes A extend in the column direction (vertical direction). The total number of display electrodes X and Y is (n + 1) obtained by adding 1 to the number n of rows, and the total number of address electrodes A is the same as the number m of columns. In the figure, the suffixes of the reference numerals of the display electrodes X and Y and the address electrodes A indicate the arrangement order. In this embodiment, the number n of rows is an even number.
[0013]
The drive unit 70 includes a control circuit 71 for driving control, a power supply circuit 73 for outputting drive power, an X driver 74 for controlling the potential of the display electrode X, a Y driver 77 for controlling the potential of the display electrode Y, and An A driver 80 for controlling the potential of the address electrode A is provided. Frame data Df indicating luminance levels of three colors of R, G, and B are input to the drive unit 70 from external devices such as a TV tuner and a computer together with various synchronization signals. The frame data Df is temporarily stored in a frame memory 711 in the control circuit 71. The control circuit 71 converts the frame data Df into subfield data Dsf for gradation display and serially transfers the data to the A driver 80. The subfield data Dsf is 1-bit display data per cell, and the value of each bit indicates whether or not light emission of a cell in the corresponding one subfield is necessary, or strictly, whether or not address discharge is required.
[0014]
FIG. 2 is a diagram showing a cell structure of a PDP. In FIG. 2, a portion corresponding to three columns of two rows in the PDP 1 is illustrated by separating the pair of substrate structures 10 and 20 so that the internal structure can be clearly understood.
[0015]
The PDP 1 includes a pair of substrate structures 10 and 20. The substrate structure means a structure including a glass substrate having a size equal to or larger than the screen size and at least one other panel component. The substrate structure 10 on the front side includes a glass substrate 11, display electrodes X and Y, a dielectric layer 17, and a protective film 18. The display electrodes X and Y include a thick band-shaped transparent conductive film (transparent electrode) 41 for forming a surface discharge gap and a thin band-shaped metal film (metal electrode) 42 as a bus conductor for lowering electric resistance. The dielectric layer 17 covering the display electrodes X and Y is formed by firing a low-melting glass paste, and the protective film 18 is made of magnesia. The rear substrate structure 20 includes a glass substrate 21, an address electrode A, an insulating layer 24, a partition wall 29, and phosphor layers 28R, 28G, and 28B. The partition wall 29 is a band-shaped structure having a straight planar shape, and is provided one for each electrode gap of the address electrode array. The partition wall 29 divides the discharge gas space for each column of the matrix display, and forms a column space 31 corresponding to each column. The column space 31 is continuous over all rows. The phosphor layers 28R, 28G, 28B are arranged so as to cover the region between the partitions in the insulating layer 24 and the side surfaces of the partitions, and emit light when excited by ultraviolet rays emitted by the discharge gas. Italic alphabets R, G, and B in the figure indicate the emission colors of the phosphor.
[0016]
FIG. 3 is a plan view showing the arrangement of the display electrodes. The display electrodes X and the display electrodes Y are arranged so as to be alternately arranged one by one in the order of XYXY... XYX, and the adjacent display electrodes X and Y constitute an electrode pair. The total number of electrode pairs is the same as the number n of rows. Of the (n + 1) display electrodes X and Y, the display electrode X at one end of the array is used for displaying the first row together with the adjacent display electrode Y, and the display electrode X at the other end of the array is the adjacent display electrode Y Used to display the last line. The remaining (n-1) display electrodes X and Y are used in two adjacent rows (an odd row L _odd and an even row L _even ). A row (odd row L _odd or even row L _even ) is a set of cells 50 of the number of columns (m) having the same arrangement order in the column direction, and the column R _j (j = 1, 2, 3,... It is a set of cells 50 for the number of rows (n).
[0017]
Hereinafter, a method of driving the PDP 1 in the display device 100 will be described.
[0018]
FIG. 4 is an explanatory diagram of field division. A time-series frame F which is an input image includes an odd field F1 and an even field F2. Generally, the frame rate is 30, and the allocation time for one field is 1/60 seconds ≒ 16.7 milliseconds. In the display according to PDP 1, for reproducing colors by selecting the combination of on / OFF subfields _SF 1 of a predetermined number q of each of the odd field F1 and even fields _{F2, SF 2, SF 3,} ..., the SFq To divide. That is, each of the fields F1 and F2 is replaced with _q subfields SF _{1 to} SF _q weighted with luminance. The luminance weight defines the number of display discharges. Typical weighting sets shown ^{{2 0, 2 1, 2} 2, ..., 2 q-2, 2 q-1} is. However, other weights may be used. In the figure, the subfield arrays are in the order of weight, but may be in another order. Odd lines L ₁ , L ₃ , L ₅ are displayed in the display of _q subfields SF _{1 to} SF _q constituting the odd field F ₁ .  Are used, and the display of the q number of sub-fields SF _{1 to} SF _q constituting the even-numbered field F2 is performed even-numbered row L _2. , L ₄ , L ₆ ... Are used.
[0019]
FIG. 5 is a diagram showing the breakdown of the subfield period. The subfield period Tsf allocated to one subfield is divided into a reset period TR, an address period TA, and a sustain period TS. The length of the address period TA is constant regardless of the luminance weight. The length of the sustain period TS is longer as the weight is larger. The length of the reset period TR differs depending on the contents of the reset performed during this period. The reset period TR of the subfield in which only the standard reset is performed as in the related art is short, and the reset period TR of the subfield in which the standard reset is performed after the special reset unique to the present invention is performed is long. That is, the length of the subfield period Tsf depends on the content of the reset and the weight of the luminance. The order of the reset period TR, the address period TA, and the sustain period TS is common to the q subfields SF1 to SFq. When the reset is regarded as the preprocessing of the addressing, the reset period TR is the first period of the subfield. When the reset is regarded as the postprocessing of the sustain, the reset period TR is the last period of the subfield. There is no difference in display operation between the two.
[0020]
Prior to the description of the drive control in the reset period TR according to the present invention, the drive control in the address period TA and the sustain period TS will be described.
[0021]
FIG. 6 is a drive voltage waveform diagram during the address period and the sustain period. FIG. 6A shows a waveform of an odd field, and FIG. 6B shows a waveform of an even field.
[0022]
In the case of the odd-numbered field in FIG. 6A, in the first half TA1 of the address period TA, the odd-numbered display electrode X _odd of the (n / 2 + 1) display electrodes X is collectively biased and activated. In this state, the scan pulses Py are applied to the odd-numbered display electrodes Y _odd among the n / 2 display electrodes Y one by one in an arbitrary order. The polarity of the scan pulse Py is opposite to the bias potential of the display electrode X _odd . By the application of the scan pulse Py, scanning of each row having the order of 1, 5, 9,... (1 + 4k) is performed. k is an integer including 0. In the cell to which the bias and the pulse have been applied, the cell voltage becomes higher than that of the other cells, and the address discharge between the display electrode Y and the address electrode A is triggered to generate the address discharge between the display electrodes. In the latter half TA2, the scan pulse Py is applied to the even-numbered display electrodes Y _even among the display electrodes Y one by one in an arbitrary order while the even-numbered display electrodes X _even are biased at once. As a result, scanning is performed on each row having the order of 3, 7, 11,... (3 + 4k). By scanning the first half TA1 and the second half TA2, predetermined wall charges are formed in the selected cells in the odd rows. Thus, in the addressing in which the scan pulse Py is applied while distinguishing the display electrode Y _odd from the display electrode Y _even , it is not necessary to switch the bias of the display electrode X every time the scan pulse Py is applied, and the boundary between the first half TA1 and the second half TA2 is not required. , It is possible to reduce wasteful power consumed for charging the capacitance between the display electrodes. In the sustain period TS, a sustain pulse Ps having a different polarity is applied to a pair of display electrodes (a pair of X _odd and Y _{odd and} a pair of X _even and Y _even ) related to odd rows, and a display discharge occurs in odd rows. Let it. A display discharge occurs each time a pulse is applied. A sustain pulse Ps having the same polarity is applied to a set of display electrodes (a set of Y _odd and X _even ) related to the even-numbered rows. Since the voltage between the electrodes does not change when a pulse of the same polarity is applied, no display discharge occurs in even-numbered rows. It should be noted that the voltage of the drive circuit can be reduced by applying the positive and negative sustain pulses Ps as in this example. However, even if the amplitude of the sustain pulse Ps is doubled and a positive or negative single-polarity sustain pulse is applied, a display discharge can be similarly generated.
[0023]
In the case of the even-numbered field in FIG. 6B, in the first half TA1 of the address period TA, the odd-numbered display electrode Y _odd is activated while the _even- numbered display electrodes _Xeven are collectively biased and activated. The scan pulses Py are applied one by one in an arbitrary order. By the application of the scan pulse Py, scanning of each row having the order of 2, 6, 10,... (2 + 4k) is performed (k is an integer including 0). In the latter half TA2, the scan pulse Py is applied to the _even- numbered display electrodes Y _even one by one in an arbitrary order while the odd-numbered display electrodes X _odd are collectively biased. As a result, scanning of each row having the order of 4, 8, 12,... (4 + 4k) is performed. By scanning the first half TA1 and the second half TA2, predetermined wall charges are formed in the selected cells in the even-numbered rows. In the sustain period TS, a sustain pulse Ps having a different polarity is applied to a set of display electrodes (a set of _Yodd and X _even ) related to an even-numbered row to generate a display discharge in the even-numbered row. A display discharge occurs each time a pulse is applied. A sustain pulse Ps having the same polarity is applied to a set of display electrodes (a set of X _odd and Y _{odd and} a set of X _even and Y _even ) related to odd-numbered rows. No display discharge occurs in odd rows.
[0024]
FIG. 7 is an explanatory diagram of a special reset according to the present invention. "+" And "-" in the figure indicate the polarity of the bias of the charge in the cell at the start of the discharge. The special reset is a charge control process in which the first reset discharge 61 is generated only in the cell belonging to the row used for display in the immediately preceding sustain, and the second reset discharge 62 is generated only in the cell belonging to another row. . In the example of FIG. 7, the row used for display in the sustain period TS immediately before the reset period TR for performing the special reset is an odd row, and the display discharge 60 is generated in the odd row. At the start of the display discharge 60, the cell corresponding to the display electrodes X ₁ and Y ₁ has a bias of the charge having a large amount of positive charge, and the cell corresponding to the display electrodes X ₂ and Y ₂ has a bias of the charge having a large amount of the negative charge. There is bias. As described above with reference to FIG. 6, a phenomenon in which biases having different polarities occur between nearby cells may be caused by applying the scan pulse Py in groups of _odd- numbered display electrodes Y _odd and even-numbered display electrodes Y _even. This is likely to occur when addressing is performed.
[0025]
Although the positive and negative wall charges are replaced by the display discharge 60, the bias of the charges remains without being eliminated. The first reset discharge 61 eliminates wall charges formed by the sustain and reduces the wall voltage. Since the excess charge remains without being neutralized, the bias of the charge is not eliminated. However, when the second reset discharge 62 is generated, excess positive charges and negative charges remaining in nearby cells attract and neutralize. Thereby, the bias of the electric charge in the cell causing the second reset discharge 62 and the cell adjacent thereto becomes small. The bias can be almost completely eliminated. The second reset discharge 62 may be one that makes the wall voltage zero when there is no bias in the electric charge, or one that generates an appropriate wall voltage. Such a special reset is particularly effective in a structure in which discharge spaces are continuous along the direction in which display electrodes are arranged, that is, a structure in which charge transfer between cells is possible. In addition, if the order of the reset discharge 61 and the reset discharge 62 is reversed, the bias of the charges may increase.
[0026]
Performing the standard reset following the special reset is preferable from the viewpoint of display stability. The standard reset is a process in which the reset discharge 63 is generated in all the rows at the same time as the conventional reset. The standard reset is excellent for equalizing the charges for all cells.
[0027]
FIG. 8 is a diagram showing an example of the execution time of the special reset. Since the purpose of performing the special reset is to correct the bias of the electric charges, it is not necessary to perform the special reset frequently. It is sufficient to carry out once for one field. The frequency may be set to be low, such as every other field or every ten fields. However, it is preferable to make the number of executions equal for the odd field and the even field. Further, it is possible to arbitrarily set which subfield of the q subfields constituting the field is to be implemented.
[0028]
When the special reset is performed once for one field, the special reset is preferably performed between the last sustain of a certain field and the first addressing of the next field, that is, at the time when a line used for display is switched. . Here, if reset is regarded as preprocessing of addressing, it is preferable to perform special reset in the first subfield of the field. For example, as in pattern 1 of FIG. 8, the first subfield SF ₁ Performs a special reset and a standard reset, and performs only the standard reset in the remaining subfields SF ₂ and SF ₃ . Pattern 2 is a modification of pattern 1 and includes first subfield SF ₁ The standard reset is omitted. The reset period TR can be shortened by the omission. As another example, all subfields SF ₁ , SF ₂ , SF ₃ , there is a pattern in which only the special reset is performed and the standard reset is not performed. This is a pattern that can be employed when the purpose of the reset is to eliminate the wall voltage and make the wall voltage zero.
[0029]
FIG. 9 is a diagram illustrating an example of an applied voltage waveform during a reset period and a discharge aspect corresponding to the waveform. The illustrated reset comprises a special reset and a standard reset, both of which use a ramp waveform. In the immediately preceding sustain period TS, the display electrode X _odd is generated so that the display discharge 60 occurs in the _odd- numbered row L _odd. , Y _odd , X _even , Y _even Are applied to the pulse. Therefore, in the reset period TR, first, the first reset discharge 61 is generated in the _odd- numbered row L _odd , then the second reset discharge 62 is generated in the _even- numbered row L _even , and finally, the odd-numbered row L _odd and the even-numbered row in L _{the even} cause third reset discharge 63. When a discharge is caused, the waveform differs between the display electrodes forming the electrode pair in the corresponding row. When no discharge occurs, the waveform is equal between the display electrodes forming the electrode pair in the corresponding row. Since a ramp waveform is used, unlike a one-shot discharge that occurs in the case of a rectangular waveform, a minute discharge occurs continuously from the time when the voltage between the electrodes exceeds the discharge starting voltage to the time when the ramp waveform ends. Each of the first, second, and third reset discharges 61, 62, and 63 is a series of minute discharges caused by two lamp voltage applications. By using the ramp waveform, the wall voltage can be adjusted to any value including zero. The principle is described in JP-A-11-352924.
[0030]
Note that the waveform of FIG. 9 can be applied to the reset following the sustain using the _even- numbered row _Leven for display. However, it is necessary to shift the relationship between the waveform and the display electrode. That is, the display electrode X _odd in FIG.  Of the display electrode Y _odd And the display electrode Y _odd Waveform display electrodes _{X the even} of the display electrodes _{Y the even} the waveform of the display electrodes _{X the even,} the display electrodes _{Y the even} display waveforms electrodes _{X odd} Respectively.
[0031]
【The invention's effect】
According to the first to fifth aspects of the present invention, it is possible to reduce the occurrence of operation abnormalities due to the bias of electric charges and to stabilize the display.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a display device according to the present invention.
FIG. 2 is a diagram showing a cell structure of a PDP.
FIG. 3 is a plan view showing an arrangement of display electrodes.
FIG. 4 is an explanatory diagram of field division.
FIG. 5 is a diagram showing a breakdown of a subfield period.
FIG. 6 is a drive voltage waveform diagram during an address period and a sustain period.
FIG. 7 is an explanatory diagram of a special reset according to the present invention.
FIG. 8 is a diagram showing a setting example of a special reset execution timing.
FIG. 9 is a diagram illustrating an example of an applied voltage waveform during a reset period and a discharge aspect corresponding to the waveform.
[Explanation of symbols]
1 PDP (AC type plasma display panel)
Df Frame data (image information)
F frame F1 odd field F2 even field _{L odd} odd rows _{L the even} an even row _SF 1 - SF _q subfield 50 cells 61 first reset discharge 62 second reset discharge 63 third reset discharge 100 plasma display device 70 drive unit ( Drive circuit)

Claims (5)

An object to be driven is that (n + 1) display electrodes are arranged on a display surface having n rows, an electrode pair for surface discharge is configured for each row by these display electrodes, and one row is adjacent to another. An AC plasma display panel having an electrode configuration sharing a display electrode,
The display target is interlaced image information in which one frame is composed of two fields.
One of the two fields constituting one frame is displayed using only odd-numbered rows of the display surface, and the other display is displayed using only even-numbered rows of the display surface.
Replace a field with multiple subfields,
Reset for equalizing wall voltages of all cells constituting the display surface in preparation for addressing for each subfield, addressing for forming a wall voltage difference between a cell to be lit and another cell, and A method for driving a plasma display panel that performs sustaining to cause display discharge only in cells to be lit using a difference in wall voltage,
In at least one subfield of a field corresponding to all or a display order of at least one set number of a plurality of fields to be sequentially displayed at a fixed period, the reset or a part of the reset is performed by the immediately preceding sustain. The first reset discharge for reducing the wall voltage is caused only by the cells belonging to the used row, and the second reset discharge is thereafter caused only for the cells belonging to the other rows to bring the wall voltage close to the set value. A method for driving a plasma display panel, comprising resetting. 2. The method according to claim 1, wherein the subfield in which the special reset is performed is a first subfield to be displayed in a corresponding field. In the subfield for performing the special reset, following the special reset, perform a standard reset in which a third reset discharge for bringing the wall voltage closer to a set value is performed in all cells at once,
2. The method according to claim 1, wherein in the subfield in which the special reset is not performed, the standard reset is performed as the reset. In the subfield for performing the special reset, only the special reset is performed as the reset,
2. The plasma display panel driving method according to claim 1, wherein in the subfield in which the special reset is not performed, a standard reset is performed in which all the cells simultaneously perform a third reset discharge for bringing the wall voltage closer to a set value as the reset. . A plasma display device comprising: an AC type plasma display panel; and a driving circuit for driving the plasma display panel, wherein the plasma display device displays interlaced image information in which one frame includes two fields,
In the plasma display panel, (n + 1) display electrodes are arranged on a display surface having n rows, an electrode pair for surface discharge is formed for each row by these display electrodes, and one adjacent row is formed. Has an electrode configuration that shares the display electrode of
The driving circuit includes:
One of the two fields constituting one frame is displayed using only odd-numbered rows of the display surface, and the other display is displayed using only even-numbered rows of the display surface.
Replace a field with multiple subfields,
Reset for equalizing wall voltages of all cells constituting the display surface in preparation for addressing for each subfield, addressing for forming a wall voltage difference between a cell to be lit and another cell, and Using the difference in wall voltage, perform sustain to generate display discharge only in cells to be lit,
In at least one subfield of a field corresponding to all or a display order of at least one set number of a plurality of fields to be sequentially displayed at a fixed period, the reset or a part of the reset is performed by the immediately preceding sustain. The first reset discharge for reducing the wall voltage is caused only by the cells belonging to the used row, and the second reset discharge is thereafter caused only for the cells belonging to the other rows to bring the wall voltage close to the set value. A plasma display device, wherein reset is performed.

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