JP2002202750A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a gradation display of high luminance by using a PDP in the structure wherein two adjacent lines share a display electrode. SOLUTION: To reproduce gradations of fields F1 and F2 by setting whether cells need to illuminate by subfields, the fields F1 and F2 are composed of subfields SF1 to SFq-1, for which one of two adjacent lines is used for the display and a subfield SFq, for which the two adjacent lines are used for the display and brought under the same illumination control. The luminance of the subfields when the two lines are used for the display becomes twice as high as when only one line is used.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a display device having a plasma display panel (PDP). PDP
Is a digital display device composed of binary light emitting cells and is suitable for displaying digital data, and is therefore expected as a multimedia monitor. In the market, there is a demand for a device having a resolution corresponding to a high-quality digital image and capable of displaying a bright image.

[0002]

2. Description of the Related Art A surface discharge type is used in an AC type PDP for color display. The surface discharge type here is
In this type, first and second display electrodes serving as an anode and a cathode in a display discharge for ensuring luminance are arranged in parallel on a front substrate or a rear substrate. Surface discharge type PDP
In such a case, it is necessary to provide a partition for partitioning a discharge space for each column of the matrix display along the length direction of the display electrode (this is referred to as a row direction). A so-called stripe pattern in which straight band-shaped partition walls are arranged at the boundaries between columns in plan view is known as the simplest partition pattern with excellent productivity.

There are two arrangements of display electrodes in the surface discharge type.
There are two forms. One is to arrange a pair of display electrodes for each row. The total number of display electrodes is twice the number n of rows. In this embodiment, the driving sequence can be simplified because each row is controlled independently. However, in the case of a stripe pattern structure, in order to prevent interference of discharge between rows, an electrode gap between adjacent rows (referred to as a reverse slit) is compared with an arrangement interval (surface discharge gap length) in each row. ) Must be a sufficiently large value (about several times). The other is a mode in which display electrodes of the number obtained by adding 1 to the number n of rows are arranged at substantially equal intervals at a rate of 3 in 2 rows. In this mode, adjacent display electrodes constitute an electrode pair for surface discharge, and display electrodes except for both ends of the arrangement are related to display of odd-numbered rows and even-numbered rows. From the viewpoints of high definition (reduction of the line pitch), effective use of the display surface, and high resolution (increase of the number of lines), it is advantageous to arrange them at equal intervals.

[0004] A driving sequence suitable for a PDP having a structure in which display electrodes are arranged at equal intervals is an interlaced type in which display of odd rows and display of even rows are performed in a time-division manner. Conventionally, in a display device equipped with this type of PDP, drive control has been performed so as not to emit light in even-numbered rows in odd-numbered fields and not to emit light in odd-numbered rows in even-numbered fields.

[0005]

Conventionally, half of the entire screen is not used for display in each of the odd and even fields, so that the frame brightness is lower than in the progressive format in which all the lines are always used for display. There was a problem of becoming. In particular, if a grid pattern that can reliably prevent discharge interference as a partition pattern is adopted,
The light emitting area of each cell becomes narrower than in the case of the stripe pattern, resulting in a darker display. When the number of times of display discharge is increased to increase the luminance, the time that can be allocated to addressing becomes shorter, and the number of gray scales that can be expressed decreases.

An object of the present invention is to realize a high-brightness multi-tone display using a PDP having a structure in which two adjacent rows share a display electrode.

[0007]

According to the present invention, a field is replaced with q (q.gtoreq.2) subfields weighted with luminance, and the necessity of light emission of the cells of the plasma display panel is set for each subfield. When gradation display is performed, k (1 ≦ k <q) subfields, in which only one of two adjacent rows is used for display, and two adjacent rows are used for display, and the same light emission control is performed for these subfields And (q−k) subfields that constitute a field. “Use for display” means that lighting control of each cell is performed according to display data. All cells belonging to a row not used for display are turned off. By using two lines for display, the brightness of the subfield is twice as high as when only one line is used. By providing a subfield that uses only one row for display, it is possible to prevent a decrease in resolution in the row arrangement direction (column direction).

It is useful to make the ratio of the number k to the number of subfields q of one field variable to realize a display suitable for the application. For example, for monitor applications that mainly display still images, a resolution priority setting with a large number k is set, and for television applications that mainly display moving images, a luminance priority setting with a small number k is set. If a setting change switch is provided, the user can select a desired setting. In that case, k = p or k = 0 as the switching options
It is also possible to add settings.

The ratio of the number k to the number q of subfields can be changed according to the display ratio. The display ratio is a numerical value representing a driving load. Strictly speaking, a ratio Gi where the gradation value displayed by the cell is Gi (0 ≦ Gi ≦ Gmax)
/ Gmax is defined as the average over all cells. When the display ratio is small, the number k is reduced to increase the luminance of the lighting cell. Conversely, when the display rate is large, the number k is increased to suppress power consumption.

The increase / decrease of the number of subfields q is effective for correcting the gradation. For example, when the display ratio is low, two adjacent rows are turned on in a subfield having a large weight, and the subfield having a small weight is omitted instead. That is, the number of subfields q is reduced.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] FIG. 1 is a diagram showing the configuration of a display device according to the present invention. The display device 100 is mx
It is composed of a surface discharge type PDP 1 having a display surface capable of color display consisting of n cells, and a drive unit 70 for controlling light emission of the cells, such as a wall-mounted television receiver and a monitor of a computer system. Used as

In the PDP 1, display electrodes X and Y forming an electrode pair for causing a display discharge are arranged in parallel, and address electrodes A are arranged so as to intersect the display electrodes X and Y. The display electrodes X and Y extend in the row direction (horizontal direction) of the matrix display, and the address electrodes extend in the column direction (vertical direction). The total number of display electrodes X and Y is (n + 1) obtained by adding 1 to the number n of rows, and the total number of address electrodes A is the same as the number m of columns. In the figure, the display electrodes X and Y
The subscripts of the reference numerals of the address electrodes A indicate the arrangement order. In this embodiment, the number n of rows is an even number.

The drive unit 70 includes a control circuit 71 for controlling driving, a power supply circuit 73 for outputting driving power, an X driver 74 for controlling the potential of the display electrode X, a Y driver 77 for controlling the potential of the display electrode Y, and an address. Electrode A
A driver 80 for controlling the potential of the A. Frame data Df indicating the luminance levels of the three colors R, G, and B are input to the drive unit 70 from external devices such as a TV tuner and a computer together with various synchronization signals. The frame data Df is temporarily stored in a frame memory 711 in the control circuit 71. The control circuit 71
The frame data Df is converted into sub-field data Dsf for gradation display and serially transferred to the A driver 80. The subfield data Dsf is a set of display data of one bit per cell, and the value of each bit indicates whether or not light emission of a cell in the corresponding one subfield is necessary, or strictly, whether or not address discharge is required. Control circuit 71
In the field configuration (2)
A control signal for specifying the type of the subfield is input. The control circuit 71 controls the sub-field data Dsf
Is generated, and driver control is performed at a timing according to the subfield data Dsf. The field configuration options include a configuration that does not display all lines described later.

FIG. 2 is a diagram showing a cell structure of a PDP according to the present invention. The PDP 1 includes a pair of substrate structures (structures in which cell components are provided on a substrate) 10 and 20. Display electrodes X and Y arranged on the inner surface of the glass substrate 11 on the front side
Are transparent conductive films 4 forming a surface discharge gap.
Metal film (bus electrode) 42 extending over the entire length of row 1
Consists of A dielectric layer 17 is provided so as to cover the display electrode pairs X and Y, and a protective film 18 is provided on the surface of the dielectric layer 17.
Magnesia (MgO). The address electrodes A are arranged in one row on the inner surface of the glass substrate 21 on the rear side.
The partition walls 29 are arranged one by one, and on the dielectric layer 24 covering these address electrodes A, partition walls 29 each having a band shape in plan view are provided between the address electrodes. These partition walls 29 divide the discharge space into columns in the row direction (horizontal direction of the display surface ES). Then, phosphor layers 28R, 28G, 28B of three colors of R, G, B for color display are provided so as to cover the side surfaces of the address electrodes A and the partition walls 29. Italic alphabet R, G, B in the figure
Indicates the emission color of the phosphor. Phosphor layers 28R, 28G, 2
8B is locally excited by ultraviolet rays emitted from the discharge gas to emit light.

FIG. 3 is a plan view showing an arrangement of display electrodes. The display electrode X and the display electrode Y are XYXY.
X are alternately arranged one by one in the order of X, and the adjacent display electrodes X
And the display electrode Y form an electrode pair. The total number of electrode pairs is the same as the number n of rows. Of the (n + 1) display electrodes X and Y, the display electrode X at one end of the array is used for displaying the first row together with the adjacent display electrodes Y, and the display electrode X at the other end of the array is the adjacent display electrode Y Used to display the last line. The remaining (n-1) display electrodes X and Y are used for two adjacent rows (odd row L _odd and even row L _even ). A row (odd-numbered row L _odd or even-numbered row L _even ) is a set of cells C of the number of columns (m) having the same arrangement order in the column direction, and the column R _j (j = 1, 2, 3,... For the number of rows (n
Cells C).

Hereinafter, the PDP 1 in the display device 100 will be described.
The driving method will be described. FIG. 4 is a conceptual diagram of a display mode.
A time-series frame F which is an input image has an odd field F
1 and an even field F2. Table by PDP1
In the figure, the color reproduction is performed by selecting the lighting / non-lighting combination.
To perform the present, the odd field F1 and the even field
Field F2 is replaced by a predetermined number q of subfields S
F₁, SF _Two, SF_Three, ..., SF_qIt is divided into. Toes
And the respective fields F1 and F2 are weighted by q
Subfields SF₁~ SF_qReplace with Luminance
Weight defines the number of display discharges. Typical weight set
Is shown in ｛2⁰, 2¹, 2^Two, ..., 2^q-2, 2^q-1｝
It is. However, other weights may be used. In the figure
The subfield array is in order of weight, but in other order.
You may. The features of the field configuration unique to the present invention are as follows.
"All lines display style" subfield that uses all lines for display
Display mode that uses only half of the field and half the number of rows n for display
(“Odd line display mode” or “even line display mode”)
Is mixed with subfields. In all line display format
Means that the subfield data for one line is applied to two lines.

In the example shown, q subfields SF
_{1 to} SF _q, the subfield S having the largest weight
Only _Fq is in the full line display mode. In the subfields SF ₁ ~SF _q-1 in the odd field F1, the lighting control of the odd row corresponding in accordance with the sub-field data of each odd row is performed, all the even rows are non-illuminated.
That is, odd-numbered row display is performed. Odd field F1
In the subfield _SFq , lighting control of the corresponding odd-numbered row and the even-numbered row adjacent thereto is performed in accordance with the subfield data of each odd-numbered row. That is, all lines are displayed. In the subfields SF ₁ ~SF _q-1 in the even field F2, the lighting control of the even rows for the following subfield data of each even row is performed, all the odd rows are non-illuminated. That is, even-numbered row display is performed. In the subfield SF _q in the even field F1, lighting control of the even rows and odd rows adjacent to it are true in accordance with the sub-field data of each even row is performed. That is, all lines are displayed.

FIG. 5 is a drive voltage waveform diagram schematically showing a drive sequence. For the waveform, the amplitude, polarity,
The timing can be variously changed. Instead of the illustrated write address format, an erase address format may be adopted.

The subfield period Tsf assigned to one subfield is divided into a reset period TR for initialization, an address period TA for addressing, and a display period TS for maintaining lighting. While the lengths of the reset period TR and the address period TA are constant regardless of the weight, the length of the display period TS increases as the weight increases. Therefore, the subfield period Ts
The length of f also increases as the weight of the corresponding subfield SF increases. The order of the reset period TR, the address period TA, and the display period TS is q subfields SF _{1 to} SF.
_The driving sequence is common in _q , and is repeated for each subfield.

In the reset period TR, a negative ramp pulse and a positive ramp pulse are sequentially applied to all display electrodes X, and a positive ramp pulse and a negative ramp pulse are applied to all display electrodes Y. Are sequentially applied. The voltage change rate of the lamp pulse is a sufficiently small value selected so as to cause a minute discharge. The ramp pulse applied first is applied to generate an appropriate wall voltage of the same polarity in all cells regardless of lighting / non-lighting in the previous subfield. By applying a ramp pulse to a cell having an appropriate wall charge, the wall voltage can be adjusted to a value corresponding to the difference between the discharge starting voltage and the pulse amplitude. The initialization (equalization of charges) in this example is to eliminate the wall charges of all the cells and make the wall voltage almost zero. The application of the pulse means that the electrode is temporarily biased. Initialization can be performed by applying a pulse to only one of the display electrodes X and Y, but by applying pulses of opposite polarities to both the display electrodes X and Y as shown in the figure, the low withstand voltage of the driver circuit element can be reduced. Can be achieved. The applied voltage to the cell is
This is a composite voltage obtained by adding the amplitudes of the pulses applied to the display electrodes X and Y.

In the address period TA, wall charges necessary for maintaining lighting are formed only in cells to be lit. In a state where all the display electrodes X and all the display electrodes Y are biased to a predetermined potential, a scan pulse Py of a negative polarity is applied to one display electrode Y corresponding to the selected row in each row selection period (scanning cycle).
Is applied. At the same time as the row selection, the address pulse Pa is applied only to the address electrode A corresponding to the selected cell in which the address discharge is to be caused. In the selected cell, the display electrode Y
A discharge occurs between the display electrode and the address electrode A, which triggers a surface discharge between the display electrodes. These series of discharges are address discharges. Wall discharge is formed on the dielectric layer 17 by the address discharge, and a wall voltage required for maintaining lighting is generated between the display electrodes.

In the display period TS, basically, a positive sustain pulse Ps is alternately applied to the display electrode Y and the display electrode X. By the first application to the display electrode Y, the cell voltage in the selected cell exceeds the discharge starting voltage, and a surface discharge occurs between the display electrodes. Since wall charges having the opposite polarity to the previous state are formed by the surface discharge, the surface discharge occurs again in the selected cell by applying the sustain pulse Ps to the display electrode X. Similarly, thereafter, a surface discharge occurs in the selected cell every time the sustain pulse Ps is applied. In the display period TS, the address electrode A is biased to a potential having the same polarity as the sustain pulse Ps in order to prevent unnecessary discharge.

[0023] In such a drive sequence, the driving waveform of the reset period TR is common to all the subfields, the driving waveform of the address period TA and the display period TS subfields SF ₁ ~SF _q-1 subfield Different from SF _q .

FIG. 6 is a diagram showing a drive voltage waveform of a subfield for displaying an odd-numbered row. Subfields SF ₁ ~SF _q-1 of the address period in the odd field F1 TA is divided into the second half of the first half TA1 TA2. In the first half TA1, the odd-numbered display electrodes X _odd of the (n / 2 + 1) display electrodes X are collectively biased and activated, and the odd-numbered display electrodes Y of the n / 2 display electrodes Y are activated. A scan pulse Py is applied to the display electrodes Y ₁ , Y ₃ , Y ₅ ..., Y _{n / 2-1} one by one in an arbitrary order. The polarity of the scan pulse Py is opposite to the bias potential of the display electrode X _odd . By the application of the scan pulse Py, scanning of each row having the order of 1, 5, 9,... (1 + 4k) is performed.
k is an integer including 0. In the cell where the bias and pulse were applied, the cell voltage was higher than the other cells,
An address discharge between the display electrodes is triggered by an address discharge between the display electrode Y and the address electrode A. In the second half TA2, while biasing the even-numbered display electrodes X _{the even} collectively, even-numbered display electrodes _{Y 2, Y 4, Y 6} ... of the display electrode Y, 1 present relative to Y n _{/ 2} The scan pulse Py is applied in any order. Thus, scanning of each row having the order of 3, 7, 11,... (3 + 4k) is performed. By scanning the first half TA1 and the second half TA2, predetermined wall charges are formed in the selected cells in the odd rows.

In the display period TS, the sustain electrodes Ps are alternately applied to the display electrodes Y and X in the odd rows.
And a sustain pulse Ps is simultaneously applied to the display electrodes Y and the display electrodes X in the even-numbered rows.

FIG. 7 shows a subfield for displaying even-numbered rows.
FIG. 4 is a diagram illustrating a drive voltage waveform. Even field F2
Buffield SF₁~ SF_q-1Before the address period TA
It is divided into half TA1 and second half TA2. First half TA1 smell
And the even-numbered display electrode X_evenBias all at once
In the active state, the odd-numbered display electrodes Y ₁,
Y_Three, Y_Five…, Y_{n / 2-1}One by one in any order
A can pulse Py is applied. Mark of scan pulse Py
In addition, each row of rank 2, 6, 10, ... (2 + 4k)
(K is an integer including 0). Second half T
In A2, the odd-numbered display electrodes X_oddAll at once
In the state of being biased, the even-numbered display electrodes Y_Two, Y_Four, Y
₆…, Y_{n / 2}Scanners one by one in an arbitrary order
Loose Py is applied. As a result, the ranking is 4, 8, 1
Scanning of each row of 2,... (4 + 4k) is performed. First half TA
Selection in even-numbered row by scanning 1 and 2nd half TA2
A predetermined wall charge is formed in the cell.

In the display period TS, the sustain pulse Ps is alternately applied to the display electrodes Y and X of the even rows.
And simultaneously apply the sustain pulse Ps to the display electrodes Y and X on the odd rows.

FIG. 8 is a diagram showing drive voltage waveforms of a subfield for displaying all rows in an odd field and an even field. Address subfield SF _q odd fields F1 and even fields F2 period TA
Is divided into the first half TA1 and the second half TA2. In the first half TA1, in a state where both the _odd- numbered display electrode X _odd and the even-numbered display electrode X _even are biased and activated at once, the odd-numbered display electrodes Y ₁ , Y ₃ ,.
A scan pulse Py is applied to Y _5, ..., Y _{n / 2-1} one by one in an arbitrary order. Late in the TA2, it is biased both odd-numbered display electrodes X _odd and even-numbered display electrodes X _{the even} collectively, even-numbered display electrodes _{Y 2, Y 4, Y 6} ..., to the Y n _{/ 2} On the other hand, scan pulses Py are applied one by one in an arbitrary order. According to the present example, the application timing of the scan pulse Py is the same for odd-row display, even-row display, and all-row display, so that the Y driver 77 can be configured using conventional drive circuit components as they are.

In the display period TS, the application of the sustain pulse Ps to all the display electrodes Y and the application of the sustain pulse Ps to all the display electrodes X are performed alternately without distinguishing between the odd-numbered and the even-numbered. This allows
The cells in which the wall charges are formed emit light during the address period TA regardless of whether the row is an odd number or an even number.

In the above embodiment, each field
Corresponding q subfields SF ₁~ SF_qOf which
Any number of subfields within the range of 2 to (q-1)
It can be a subfield in a line display format. All lines
There is no limitation on the luminance weight of the subfield to be displayed. [Second Embodiment] FIG. 9 shows the structure of another display device according to the present invention.
FIG. The display device 100b has m × n cells.
The field configuration according to the PDP1 and the display rate
Drive unit 70b having a control circuit 72
It is composed of Except for the control circuit 72, the display device 100
The configuration of b is the same as the display device 100 of the first embodiment.
You.

The control circuit 72 includes a frame memory 721,
It has a data control unit 722, a display ratio detection unit 723, a mode setting unit 724, and a driver control unit 725. The frame memory 721 temporarily stores the frame data Df input via the data control unit 722. The data control unit 722 converts the frame data Df into subfield data Dsf and transfers the subfield data Dsf to the A driver 80 in accordance with the progress of the display. The display ratio detection unit 723 detects a display ratio of a frame based on the frame data Df. The display ratio may be detected for each of the odd field and the even field. The mode setting unit 724 sets the number of subfields q and the field configuration according to the display ratio. For example, when a window having a display rate of about 10% is displayed, white peak luminance is increased by displaying all lines in a subfield having a large weight. When the display rate is high, a field configuration in which there are few or no subfields for displaying all lines is set. Generally, when the display ratio is large, power adjustment for reducing the number of sustain pulses in the display period TS is performed. Therefore, when all rows are displayed, the effect of the power adjustment is reduced. The setting contents of the field configuration are sent to the data control unit 722 and the driver control unit 725, and are applied to the generation of the subfield data Dsf and the driver control. Also in this example, a function of changing the field configuration in accordance with the mode specified by the user through the switch operation can be provided.

[0032]

According to the first or fifth aspect of the present invention, high-intensity multi-tone display can be realized by using a PDP having a structure in which two adjacent rows share a display electrode.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a display device according to the present invention.

FIG. 2 is a diagram showing a cell structure of a PDP according to the present invention.

FIG. 3 is a plan view showing an arrangement of display electrodes.

FIG. 4 is a conceptual diagram of a display mode.

FIG. 5 is a drive voltage waveform diagram schematically showing a drive sequence.

FIG. 6 is a diagram showing a drive voltage waveform of a subfield for displaying an odd-numbered row.

FIG. 7 is a diagram showing a drive voltage waveform of a subfield for displaying even-numbered rows.

FIG. 8 is a diagram showing drive voltage waveforms in a subfield for displaying all rows in an odd field and an even field.

FIG. 9 is a configuration diagram of another display device according to the present invention.

[Explanation of symbols]

X display electrode (first display electrode) Y display electrode (second display electrode) L _{odd /} odd row L _even even row 1 PDP (plasma display panel) F1 odd field (first field) F2 even field (second field) ) SF _{1 to} SF _q subfield 100, 100b Display device 71, 72 Control circuit 723 Display ratio detection unit 724 Mode setting unit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/28 K (72) Inventor Fumihiro Namiki 3-2-1 Sakado, Takatsu-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Hitachi Plasma Display Stock Company In-house (72) Inventor Shoji Ishigaki 3-2-1, Sakado, Takatsu-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Hitachi Plasma Display Co., Ltd. In-house F-term (reference) EE29 HH02 HH04 JJ02 JJ04 JJ06

Claims (5)

[Claims] 1. A plurality of first display electrodes and a plurality of second display electrodes form an electrode pair for surface discharge for each row and share one electrode for display of two adjacent rows. A display device having an arrayed plasma display panel, replacing a field with a plurality of sub-fields weighted with luminance, and setting a necessity of light emission of the cells of the plasma display panel in sub-field units to perform gradation display A field is composed of a subfield that uses only one of two adjacent rows for display, and a subfield that uses two adjacent rows for display and performs the same light emission control on these two rows. Display device. 2. A first field comprising a subfield using only odd rows for display, a subfield using both odd rows and even rows for display, and a subfield using only even rows for display. And a second field composed of subfields that use both odd and even rows for display.
The display device according to the above. 3. The display device according to claim 1, wherein the ratio of a subfield in which only one of two adjacent lines in one field is used for display and a subfield in which two adjacent lines are used for display is variable. 4. The display device according to claim 3, further comprising: a circuit for detecting a display ratio of the input image; and a circuit for changing the ratio in accordance with the display ratio. 5. The display device according to claim 1, further comprising a circuit for detecting a display rate of the field, and a circuit for changing the number of subfields constituting one field according to the display rate.