JP2004078660A - Semiconductor device and system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which of automatically corrects AC timing chip by chip after substrate packaging, and materializes the AC timing suitable for a packaging environment by enabling freely changing the AC timing after actual chip completion, and enables automatically correcting variable delay amount, and also to provide a system packaged with the semiconductor device. <P>SOLUTION: An LSI1 comprises a clock regenerating circuit 17 regenerating an inner clock signal by inputting a clock signal from the outside, an inputting/outputting circuit 12 inputting/outputting a data signal to the outside, and a phase adjusting circuit 18 adjusting a relative phase between the inner clock signal regenerated by the clock regenerating circuit 17 and the data signal inputted/outputted by the inputting/outputting circuit 12. A CPU 2 is connected to the outside of the LSI1, and the AC timing is freely changed even after actual chip completion between the LSI1 and the CPU2. In addition, variable delay amount is automatically corrected. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a system mounted with the semiconductor device, and more particularly to a technique effective when applied to AC timing adjustment for automatically correcting the phase of a clock signal for an interface.
[0002]
[Prior art]
According to studies made by the present inventors, the following techniques are considered as AC timing adjustment techniques for semiconductor devices.
[0003]
For example, in a semiconductor device such as a CPU and a memory, AC timing such as a propagation delay time between an input / output terminal, a setup time, and a hold time is defined. For this reason, a timing design is performed so as to satisfy a specified AC timing under conditions that consider device manufacturing variations, temperature conditions, voltage conditions, and the like.
[0004]
As a technique relating to the AC timing adjustment of such a semiconductor device, for example, a technique described in Japanese Patent Application Laid-Open No. H11-289322 can be cited. This publication discloses a technique for easily adjusting a timing of a signal by arbitrarily changing an AC characteristic by using a JTAG circuit and easily designing a substrate in a short period of time.
[0005]
[Problems to be solved by the invention]
By the way, as a result of the present inventor's study on the AC timing adjustment technology for a semiconductor device as described above, the following has become clear.
[0006]
For example, in the technique disclosed in Japanese Patent Application Laid-Open No. H11-289322, timing adjustment cannot be performed automatically, and timing adjustment optimized for each actual use condition and each chip cannot be performed. Further, the AC timing can be delayed but not advanced.
[0007]
Further, in the semiconductor device as described above, timing design is performed to satisfy the AC timing specification. However, the specified AC timing must be satisfied under conditions in which all of device manufacturing variations, temperature conditions, voltage conditions, and the like are considered. However, it is becoming more difficult, especially for interfaces that operate at high speed.
[0008]
Furthermore, in the mass production process of semiconductor devices, it is difficult to select based on the strict AC timing conditions and manufacturing variations in terms of test accuracy, which may cause a reduction in yield. In addition, timing problems may become apparent for the first time on the mounting machine, and there is a limit to this as well with the evaluation by the tester alone.
[0009]
Therefore, an object of the present invention is to make it possible to arbitrarily change the AC timing even after the actual chip is completed, and to automatically correct the variable delay amount after the actual chip is completed. Another object of the present invention is to provide a semiconductor device capable of realizing an optimum AC timing according to a mounting environment, and a system mounting the same.
[0010]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0011]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0012]
(1) A semiconductor device according to the present invention reproduces an internal clock signal by inputting a clock signal from outside, a clock reproducing circuit, an input / output circuit for inputting / outputting a data signal to / from the outside, and a clock reproducing circuit. A phase adjusting circuit for adjusting a relative phase between the internal clock signal and a data signal input / output by the input / output circuit. In this configuration, a CPU having means for generating a clock signal and means for inputting and outputting a data signal is connected to the outside (upper). Alternatively, a first semiconductor device including a circuit for generating a clock signal and a circuit for inputting and outputting a data signal is connected.
[0013]
Therefore, according to the semiconductor device of (1), it is possible to arbitrarily change the AC timing between the host CPU and the first semiconductor device even after the actual chip is completed. The delay amount can be automatically corrected. As a result, after the semiconductor device is mounted on the substrate, the AC timing is automatically corrected for each chip, and the optimum AC timing according to the mounting environment can be realized.
[0014]
(2) A semiconductor device according to the present invention includes a clock recovery circuit that reproduces a clock signal to the outside and outputs it as an external clock signal, an input / output circuit that inputs and outputs a data signal to the outside, and a clock recovery circuit. A phase adjustment circuit for adjusting a relative phase between an external clock signal to be reproduced and a data signal input / output by an input / output circuit. In this configuration, a second semiconductor device having a circuit for inputting and outputting a data signal in synchronization with an external clock signal is connected to the outside (lower).
[0015]
Therefore, according to the semiconductor device of (2), it is possible to arbitrarily change the AC timing between the lower-level second semiconductor device and the actual semiconductor chip, similarly to the semiconductor device of (1), In addition, since the variable delay amount can be automatically corrected, the AC timing is automatically corrected for each chip after the semiconductor device is mounted on the substrate, so that the optimum AC timing according to the mounting environment can be realized. .
[0016]
(3) In the semiconductor device of (1) or (2), the phase adjustment circuit sets the phase of the internal clock signal reproduced by the clock reproduction circuit to the setup time, hold time, The adjustment is made according to the delay time. The clock recovery circuit includes a PLL, DLL, or SMD that variably adjusts the delay time of the internal clock signal. The adjustment of the phase of the internal clock signal is controlled by the BIOS or the OS, and the initial value before the adjustment is stored in the BIOS. Adjustment of the phase of the internal clock signal is performed at power-on reset, at regular time intervals, when environmental conditions fluctuate, or when a signal transmission error is detected. In addition, it is adjusted according to the usage environment. It is intended to be.
[0017]
Therefore, according to the semiconductor device of (3), the phase of the internal clock signal can be adjusted according to the setup time, the hold time, and the delay time of the data signal. In addition, the phase of the internal clock signal can be adjusted at power-on reset, at regular time intervals, when environmental conditions fluctuate, or when a signal transmission error is detected, and can be adjusted according to the usage environment. At this time, the phase can be adjusted in the direction of advancing or in the direction of delaying.
[0018]
(4) A system according to the present invention includes a CPU having a means for generating a clock signal, a means for inputting and outputting a data signal, and a second semiconductor device having a circuit for inputting and outputting a data signal in synchronization with an external clock signal. , A third semiconductor device connected between the CPU and the second semiconductor device. The third semiconductor device has the same configuration as the semiconductor device of (1) (and the semiconductor device of (3)).
[0019]
Therefore, according to the system of (4), after mounting the CPU, the second semiconductor device, and the third semiconductor device on the substrate, the AC timing is automatically corrected for each chip, and the optimum AC timing according to the mounting environment is adjusted. Can be realized.
[0020]
(5) A system according to the present invention includes a first semiconductor device having a circuit for generating a clock signal, a circuit for inputting and outputting a data signal, and a second semiconductor device having a circuit for inputting and outputting a data signal in synchronization with an external clock signal. And a third semiconductor device connected between the first semiconductor device and the second semiconductor device. The third semiconductor device has a configuration similar to that of the semiconductor device of (2) (further, the semiconductor device of (3)).
[0021]
Therefore, according to the system of (5), after the first semiconductor device, the second semiconductor device, and the third semiconductor device are mounted on the substrate, the AC timing is automatically corrected for each chip, and is adjusted to the mounting environment. Optimum AC timing can be realized.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.
[0023]
(Embodiment 1)
First, an example of the configuration of the semiconductor device according to the first embodiment of the present invention will be described with reference to FIG. FIG. 1 shows a configuration diagram of the semiconductor device of the present embodiment.
[0024]
The semiconductor device of the present embodiment is, for example, an LSI 1 that performs timing correction on signal transmission with an externally connected CPU, and has an internal logic circuit 11 that performs a logical operation on a data signal, and inputs and outputs a data signal to and from an external device. And an automatic timing correction circuit 13 for correcting the timing of signal transmission with the outside. The LSI 1 is connected to a CPU 2 having a means for generating a clock signal, a means for inputting and outputting a data signal, and the like.
[0025]
The LSI 1 is provided with a system clock input terminal, a plurality of data input / output terminals, and the like. A system clock signal is input from an external CPU 2, and a data signal is input to and output from the CPU 2. Further, the LSI 1 is provided with a reception data output terminal and a delay control value input terminal, and reads the value of the reception data storage register 14 from the reception data output terminal to determine whether the data transmitted by the CPU 2 can be received by the LSI 1. The AC timing of the LSI 1 is corrected by inputting an optimum delay control value from the delay control value input terminal while controlling the automatic timing correction circuit 13.
[0026]
The input / output circuit 12 is connected to, for example, a data input / output terminal and includes an input circuit 15 including a plurality of buffers and flip-flops, an output circuit 16 including a plurality of buffers and flip-flops, and the like. The circuit 16 is connected to the internal logic circuit 11. The input clock signal after correction is supplied from the automatic timing correction circuit 13 to the first-stage flip-flop of the input circuit 15 in the input / output circuit 12, and the input data is synchronized with the system clock signal. Similarly, the output clock signal after correction from the automatic timing correction circuit 13 is also supplied to the last-stage flip-flop of the output circuit 16, and the output data is synchronized with the system clock signal.
[0027]
Further, the input / output circuit 12 is provided with a reception data storage register 14 after the first stage flip-flop of the input circuit 15, and stores data transmitted by the CPU 2. The reception data storage register 14 can be directly read and written by the CPU 2.
[0028]
The automatic timing correction circuit 13 receives a clock signal from the CPU 2 as an input to reproduce an internal clock signal, an internal clock signal reproduced by the clock reproduction circuit 17, and data input / output by the input / output circuit 12. A phase adjusting circuit 18 for adjusting a relative phase with a signal is provided.
[0029]
The clock recovery circuit 17 is, for example, a PLL (Phase Locked Loop) or a DLL (Delay Locked Loop) or an SMD (Synchronous Mirror Delay), and is a circuit that variably adjusts the replica delay time. The clock recovery circuit 17 includes a reference clock input terminal RFCLK, a feedback clock input terminal FBCLK, and a clock output terminal CLKOUT.
[0030]
The phase adjustment circuit 18 includes, for example, a plurality of circuits connected to each input terminal and output terminal of the clock recovery circuit 17, and includes four variable delay circuits (A) 19, (B) 20, (C) 21, and (D). ) 22, four decoders 23 to 26 for controlling the variable delay circuits 19 to 22, two frequency dividers (A) 27 and (B) 28 for dividing the clock signal, and a delay for controlling the delay amount. It comprises a control value storage register 29 and the like.
[0031]
As described above, in the automatic timing correction circuit 13 including the clock recovery circuit 17 and the phase adjustment circuit 18, timing adjustment is performed in the following four paths.
[0032]
(1) The input from the system clock input terminal to which the system clock signal is supplied from the CPU 2 through the variable delay circuit (A) 19 and the frequency dividing circuit (A) 27 to the reference clock input terminal RFCLK to the clock recovery circuit 17 Provide a path. The variable delay circuit (A) 19 is set in the delay control value storage register 29 via the decoder 23, and can realize an arbitrary delay time (T1 + TA). Here, the path-specific delay time excluding the delay time TA is defined as T1.
[0033]
(2) An input path is provided from the clock output terminal CLKOUT of the clock recovery circuit 17 to the feedback clock input terminal FBCLK of the clock recovery circuit 17 through the variable delay circuit (B) 20 and the frequency divider (B) 28. The variable delay circuit (B) 20 is set via the decoder 24 in the delay control value storage register 29, and can realize an arbitrary delay time (T2 + TB). Here, the path-specific delay time excluding the delay time TB is defined as T2.
[0034]
(3) A path is provided from the clock output terminal CLKOUT of the clock recovery circuit 17 to the first stage flip-flop of the input circuit 15 through the variable delay circuit (C) 21. The variable delay circuit (C) 21 is set via the decoder 25 in the delay control value storage register 29, and can realize an arbitrary delay time (T3 + TC). Here, the path-specific delay time excluding the delay time TC is defined as T3.
[0035]
(4) A path is provided from the clock output terminal CLKOUT of the clock recovery circuit 17 to the final stage flip-flop of the output circuit 16 through the variable delay circuit (D) 22. The variable delay circuit (D) is set via the decoder 26 in the delay control value storage register 29, and can realize an arbitrary delay time (T4 + TD). Here, the path-specific delay time excluding the delay time TD is T4.
[0036]
In the present embodiment, the CPU 2 connected to the outside of the LSI 1 can directly control the automatic timing correction circuit 13 of the LSI 1. The CPU 2 checks whether the data transmitted by itself has been received by the LSI 1 by reading the value of the reception data storage register 14, and corrects the AC timing of the LSI 1 while controlling the automatic timing correction circuit 13.
[0037]
Next, an example of the configuration of the clock recovery circuit in the LSI according to the present embodiment will be described with reference to FIGS. FIG. 2 is a configuration diagram of a PLL circuit, and FIG. 3 is a configuration diagram of a DLL circuit.
[0038]
As shown in FIG. 2, the PLL circuit has a basic configuration including a phase comparator 51, a low-pass filter 52, a VCO 53, and the like, and determines a phase difference between a reference clock signal RFCLK and a feedback clock signal FBCLK output from the VCO 53 by a phase comparator. The output according to the phase difference is filtered to a DC voltage by a low-pass filter 52 and input to the VCO 53 as a control voltage. The VCO 53 is an oscillation circuit whose output frequency changes according to the control voltage. The output clock signal CLKOUT is input to the phase comparator 51 again as a feedback clock signal FBCLK. As described above, the feedback loop is configured so that the phase of the output clock signal CLKOUT of the VCO 53 is synchronized with the phase of the reference clock signal RFCLK. When, for example, a 1 / N frequency divider 54 is connected between the low-pass filter 52 and the VCO 53 of the basic PLL circuit, an output clock signal CLKOUT having a frequency N times the reference clock signal RFCLK can be obtained. it can.
[0039]
As shown in FIG. 3, the DLL circuit includes a variable delay circuit 61, a phase comparator 62, a bias controller 63, a replica delay circuit 64, and the like. Similar to the PLL circuit, the reference clock signal RFCLK is supplied to the variable delay circuit 61. The output clock signal CLKOUT is input to the variable delay circuit 61 via the replica delay circuit 64, the phase comparator 62 and the bias controller 63 as the feedback clock signal FBCLK. The delay amount of the variable delay circuit 61 is controlled by the bias controller 63 based on the output of the phase comparator 62.
[0040]
Next, an example of the configuration of a system using the LSI according to the present embodiment will be described with reference to FIG. FIG. 4 shows a configuration diagram of the system.
[0041]
The system includes the above-described devices of the LSI 1 and the CPU 2, the device of the CPU system clock generation circuit 3, the USB (Universal Serial Bus) -compatible device 4 (hereinafter simply referred to as USB) as a lower device, and the ATAPI (AT Attachment Packet). An interface compatible device 5 (hereinafter simply referred to as ATAPI), a memory device 6 (hereinafter simply referred to as memory), a crystal oscillator 7 for USB clock generation, and the like. The LSI 1 of the present embodiment is used for an interface with the CPU 2 and also for interfaces with a plurality of types of lower-order devices 4 to 6.
[0042]
The LSI 1 includes an input / output circuit 12 and an automatic timing correction circuit 13 between the internal logic circuit 11 and the CPU 2, an input / output circuit 12 a with the USB 4, an automatic timing correction circuit 13 a and a clock generation circuit 30 a, an ATAPI 5 An input / output circuit 12b, an automatic timing correction circuit 13b, a clock generation circuit 30b, and an input / output circuit 12c, an automatic timing correction circuit 13c, and a clock generation circuit 30c between the memory 6 are provided. The internal logic circuit 11 is divided into an operation unit for the CPU 2 and the memory 6, an operation unit for the USB4, and an operation unit for the ATAPI5 according to a clock signal required for the operation. Each of the input / output circuits 12, 12a to 12c and each of the automatic timing correction circuits 13, 13a to 13c have the same circuit configuration as that of FIG.
[0043]
In this system, although not limited to this, for example, a 100 MHz system clock signal is generated from the CPU system clock generating circuit 3, and the CPU 2 operates in synchronization with the 100 MHz system clock signal. The 100 MHz system clock signal is frequency-divided to 50 MHz by the clock generation circuit 30b and supplied to the ATAPI 5, and is supplied to the memory 6 at 100MHz by the clock generation circuit 30c. For the USB 4, 48 MHz is generated by the clock generation circuit 30 a from the clock signal oscillated by the crystal oscillator 7 and supplied to the USB 4.
[0044]
Next, an example of the phase relationship between clock signals in the LSI according to the present embodiment will be described with reference to FIG. FIGS. 5A and 5B are explanatory diagrams of the phase relationship between clock signals in an LSI. FIG. 5 shows a phase relationship when the delay times of the variable delay circuits (A), (B), (C), and (D) are not corrected.
[0045]
In the LSI 1, the signal at the clock input terminal of the chip terminal is (C), the signal at the reference clock input terminal RFCLK in the clock recovery circuit 17 is (R), the signal at the feedback clock input terminal FBCLK is (F), and the clock output is The signal at the terminal CLKOUT is (A), the signal at the clock input terminal of the first-stage flip-flop of the input circuit 15 in the input / output circuit 12 is (I), and the signal at the clock input terminal of the last-stage flip-flop of the output circuit 16 is (O).
[0046]
The delay time of the variable delay circuit (A) 19 is T1, the delay time of the variable delay circuit (B) 20 is T2, the delay time of the variable delay circuit (C) 21 is T3, and the delay time of the variable delay circuit (D) 22 is Time is set to T4.
[0047]
Since the clock recovery circuit 17 operates to match the phases of (R) and (F), if T2> T1, the phase of (A) is earlier than the phase of (C). If T2 <T1, the phase of (A) lags behind the phase of (C).
[0048]
From the relationship between T2 and T1, the phases of (I) and (O) can be controlled before and after the phase of (C). That is, the phases of (I) and (O) can be controlled in the direction of advancing or retarding.
[0049]
From the relationship between T3 and T4, the AC timing for data input and the AC timing for data output can be controlled separately.
[0050]
Next, an example of a timing relationship between a clock signal and a data signal in the LSI according to the present embodiment will be described with reference to FIG. FIG. 6 is an explanatory diagram of a timing relationship between a clock signal and a data signal in an LSI.
[0051]
In the LSI 1, when a data signal is input to the system clock signal (C), the setup and hold when the phase of the clock signal (I) is not corrected are set as an initial setup value and an initial hold value, and the timing is adjusted as follows. It becomes possible.
[0052]
For example, by generating a delay time TB by the variable delay circuit (B) 20 at the input of the data signal, the phase of the clock signal of (I) is advanced by TB, the setup is smaller than the initial setup value, and the hold is the initial hold. Can be larger than the value.
[0053]
Alternatively, by generating a delay time TA by the variable delay circuit (A) 19 at the input of the data signal, the phase of the clock signal of (I) is delayed by TA, the setup is larger than the initial setup value, and the hold is initially held. Can be smaller than the value.
[0054]
Further, in the output of the data signal, the timing can be adjusted as follows, using the delay value when the phase of the clock signal (O) is not corrected as the initial delay value.
[0055]
For example, by generating a delay time TB by the variable delay circuit (B) 20 in the output of the data signal, the phase of the clock signal (O) is advanced by TB and the delay value can be advanced by TB.
[0056]
Alternatively, by generating a delay time TA by the variable delay circuit (A) 19 in the output of the data signal, the phase of the clock signal (O) can be delayed by TA and the delay value can be delayed by TA.
[0057]
Next, an example of a procedure of automatic timing correction in the LSI according to the present embodiment will be described with reference to FIGS. FIGS. 7 and 8 show flowcharts of automatic timing correction in the LSI.
[0058]
This automatic timing correction is controlled by the BIOS or the OS, and the initial value before adjustment is stored in the BIOS. The phase adjustment is performed at power-on reset, at regular time intervals set by a timer, when environmental conditions detected by a sensor fluctuate, when a signal transmission error is detected, and the like. Is
[0059]
At the start of automatic timing correction, the system clock signal is in an input state, and each register is in an initialized state.
[0060]
After the start, first, the value of the delay control value storage register 29 is set to the minimum value (step S1), data is input from the connected CPU 2 (step S2), and the value of the received data storage register 14 is changed by the CPU 2 Reading (step S3), the value of the reception data storage register 14 is compared with the expected value (step S4).
[0061]
As a result of the comparison in step S4, if the value of the received data storage register 14 is different from the expected value, the value of the delay control value storage register 29 is added by +1 (step S5), and the processing from step S3 is repeated. If the comparison results are the same, the CPU 2 stores the value of the delay control value storage register 29 in the memory as an input initial pass value (step S6).
[0062]
Further, after adding +1 to the value of the delay control value storage register 29 (step S7), the CPU 2 reads the value of the reception data storage register 14 (step S8), and compares the value of the reception data storage register 14 with the expected value. (Step S9).
[0063]
As a result of the comparison in step S9, if the value of the received data storage register 14 is equal to the expected value, the value of the delay control value storage register 29 is incremented by +1 (step S10), and the processing from step S8 is repeated. If the comparison results are different, the CPU 2 stores the value of -1 of the delay control value storage register 29 in the memory as the input final pass value (step S11).
[0064]
Then, an intermediate value between the input initial pass value and the input final pass value stored in the memory is set as the input optimum value (step S12). As described above, the optimum value for the input is obtained.
[0065]
Subsequently, when obtaining the optimum value for output, first, the value of the delay control value storage register 29 is set to the minimum value (step S13), data is output from the present LSI 1 (step S14), and the connection destination CPU 2 After inputting the data (step S15), the CPU 2 reads the value of the reception data storage register 14 (step S16), and compares the value of the reception data storage register 14 with an expected value (step S17). In step S15, the value of the delay control value storage register 29 is returned to the input optimum value only at the time of input.
[0066]
As a result of the comparison in step S17, if the value of the received data storage register 14 is different from the expected value, the value of the delay control value storage register 29 is added by +1 (step S18), and the processing from step S14 is repeated. If the comparison results are the same, the CPU 2 stores the value of the delay control value storage register 29 in the memory as an output initial pass value (step S19).
[0067]
Further, +1 is added to the value of the delay control value storage register 29 (step S20), data is output from the LSI 1 (step S21), and data is input from the connected CPU 2 (step S22). Is read by the CPU 2 (step S23), and the value of the reception data storage register 14 is compared with the expected value (step S24). In step S22, the value of the delay control value storage register 29 is returned to the input optimum value only when reading.
[0068]
As a result of the comparison in step S24, if the value of the received data storage register 14 is equal to the expected value, the value of the delay control value storage register 29 is added by +1 (step S25), and the processing from step S21 is repeated. If the comparison results are different, the CPU 2 stores the value of -1 of the delay control value storage register 29 in the memory as the output final pass value (step S26).
[0069]
Then, an intermediate value between the output initial pass value and the output final pass value stored in the memory is set as the output optimum value (step S27). Finally, the difference between the optimal input value and the optimal output value is adjusted by the variable delay circuit (C) 21 and the variable delay circuit (D) 22 (step S28).
[0070]
As described above, according to the LSI 1 of the present embodiment, the automatic timing correction circuit 13 that realizes the desired AC timing, which includes the clock recovery circuit 17 such as a PLL circuit, a DLL circuit, or an SMD circuit, and the phase adjustment circuit 18, etc. The variable delay circuits 19 and 20 provided at two places, ie, the input clock delay path of the clock recovery circuit 17 and the delay path in the feedback loop, the variable delay circuits 21 and 22 provided at the output path of the clock recovery circuit 17, and the CPU 2 By incorporating a delay control value storage register 29 that can be directly controlled, decoders 23 to 26 for variable delay circuit control, and a reception data storage register 14, the AC timing can be arbitrarily changed even after the actual chip is completed. By automatically correcting the amount of delay, the AC timing is automatically corrected for each chip after mounting on the board. And, it is possible to achieve optimum AC timing tailored to the implementation environment.
[0071]
(Embodiment 2)
An example of the configuration of the semiconductor device according to the second embodiment of the present invention will be described with reference to FIG. FIG. 9 shows a configuration diagram of the semiconductor device of the present embodiment.
[0072]
The semiconductor device according to the present embodiment is an LSI 1a that performs timing correction for signal transmission with an externally connected LSI or a lower device such as a memory, and has an internal logic circuit 11 that performs a logical operation on a data signal, An input / output circuit 12 for inputting / outputting data signals via an input / output circuit 12 and an automatic timing correction circuit 13 for correcting the timing of signal transmission to and from a lower device of an external LSI (or memory) 8. It is controlled by the CPU 2a.
[0073]
That is, the LSI 1a according to the present embodiment has an internal logic clock generation circuit 31 added to the configuration of the LSI 1 according to the first embodiment, and the internal logic clock generation circuit 31 includes a CPU 2a connected to the outside. The input clock signal is generated as an internal logic clock signal and supplied to a lower device of an externally connected LSI (or memory or the like) 8. Note that the other configuration has the same function as that of the first embodiment.
[0074]
In the present embodiment, the data transmitted by the lower device of the LSI (or memory) 8 is stored in the reception data storage register 14 provided after the first-stage flip-flop of the input circuit 15. The reception data storage register 14 can be directly read and written by the CPU 2a.
[0075]
Further, the CPU 2a connected to the outside of the LSI 1a can directly control the automatic correction timing circuit 13 of the LSI 1a. The CPU 2a checks whether the data transmitted by the lower device of the LSI (or memory) 8 can be received by the LSI 1a by reading the value of the reception data storage register 14, and controls the automatic timing correction circuit 13 while controlling the automatic timing correction circuit 13. The AC timing of the LSI 1a can be corrected.
[0076]
Therefore, according to the LSI 1a of the present embodiment, the AC timing can be arbitrarily changed even after the actual chip is completed, similarly to the first embodiment, particularly with the lower device of the LSI (or a memory or the like) 8, as in the first embodiment. In addition, since the variable delay amount can be automatically corrected, the AC timing is automatically corrected for each chip after mounting on the board, and the optimum AC timing according to the mounting environment can be realized.
[0077]
(Embodiment 3)
An example of the configuration of the semiconductor device according to the third embodiment of the present invention will be described with reference to FIG. FIG. 10 shows a configuration diagram of the semiconductor device of the present embodiment.
[0078]
The semiconductor device according to the present embodiment is, for example, an LSI 1b that performs timing correction for signal transmission with an externally connected LSI, and has an internal logic circuit 11 that performs a logical operation on a data signal, and inputs and outputs a data signal to and from an external device And an automatic timing correction circuit 13 for correcting the timing of signal transmission with the external LSI 9.
[0079]
That is, the LSI 1b of the present embodiment is different from the configuration of the LSI 1 of the first embodiment in that the expected value circuit 32 for storing the expected value, the reception data stored in the reception data storage register 14 and the expected value of the expected value circuit. A comparison circuit 33 for comparing the value with a value, a test data generation circuit 34 for generating test data, an input optimum value storage register 35 for storing an input optimum value, an output optimum value storage register 36 for storing an output optimum value, and a correction value are determined. A correction value determination circuit 37, an initial path value storage register 38 for storing an initial path value, and a final path value storage register 39 for storing a final path value are added. In this configuration, the expected value circuit 32, the reception data storage register 14, and the comparison circuit 33 are referred to as an expected value comparison circuit.
[0080]
The start signal generation circuit 41, the system clock generation circuit 42, the test data generation circuit 43, the internal logic circuit 44, the input / output circuit 45, the expected value comparison circuit are provided in the LSI 9 connected to the outside of the LSI 1b of the present embodiment. (Including an expected value circuit, a received data storage register, and a comparison circuit) 46 are provided. The activation signal generation circuit 41 is a circuit for generating a signal for activating the LSI 9 and the LSI 1b. The system clock generation circuit 42 is a circuit for generating a system clock signal. The test data generation circuit 43, the internal logic circuit 44, the input / output circuit 45, and the expected value comparison circuit 46 have functions similar to those of the LSI 1b.
[0081]
In the present embodiment, a reception data storage register 14 is provided after the first-stage flip-flop of the input circuit 15 in the LSI 1b, and stores data transmitted by the LSI 9. Conversely, a reception data storage register is provided after the first-stage flip-flop of the input circuit in the LSI 9 to store the data transmitted by the LSI 1b. Also, the LSI 9 has a test data generation circuit 43 and sends the same value as the expected value possessed by the LSI 1b to the LSI 1b. Conversely, the LSI 1b also has the test data generating circuit 34 and sends the same value as the expected value possessed by the LSI 9 to the LSI 9.
[0082]
In the connection between the LSI 1b and the LSI 9 configured as described above, the timing adjustment in the automatic timing correction circuit 13 is the same as that in the first embodiment except for the connection configuration. After adjusting the timing, the correction value determination circuit 37 of the LSI 1b obtains the results of the expected value comparison circuits 33 and 46 of the LSI 1b and the LSI 9 based on the test data transmitted from the LSI 1b and the LSI 9, thereby passing the comparison result to the initial path. The values are stored in the value storage register 38 and the final pass value storage register 39, and the input optimum value and the output optimum value can be finally determined.
[0083]
Next, an example of a procedure of automatic timing correction in the LSI according to the present embodiment will be described with reference to FIGS. FIGS. 11 and 12 show flowcharts of automatic timing correction in the LSI.
[0084]
At the start of the automatic timing correction, first, a system clock signal is input from the system clock generation circuit 42 of the LSI 9 (step S31), a start signal is input from the start signal generation circuit 41 (step S32), and each register in the LSI 1b is set. Is initialized (step S33).
[0085]
Subsequently, the value of the delay control value storage register 29 is set to the minimum value (step S34), and after inputting test data from the connected LSI 9 (step S35), it is compared with the expected value of the LSI 1b (step 36). .
[0086]
If the result of the comparison in step S36 is different from the expected value of the LSI 1b, the value of the delay control value storage register 29 is added by +1 (step S37), and the processing from step S36 is repeated. The correction value determination circuit 37 stores the value of the delay control value storage register 29 in the initial pass value storage register 38 (Step S38).
[0087]
Further, it is compared with the expected value of the LSI 1b (step S40). As a result of the comparison in step S40, when the value of the received data storage register 14 and the expected value of the expected value circuit 32 are the same, the value of the delay control value storage register 29 is added by +1 (step S41), and the processing from step S40 is started. On the other hand, if the comparison results are different, the correction value determination circuit 37 stores the value of -1 in the delay control value storage register 29 in the final path value storage register 39 (step S42).
[0088]
Then, an intermediate value between the value of the initial path value storage register 38 and the value of the final path value storage register 39 is stored in the input optimum value storage register 35 (step S43). As described above, the optimum value for the input is obtained.
[0089]
Subsequently, when obtaining the optimum value for the output, first, the value of the delay control value storage register 29 is set to the minimum value (step S44), the test data is output from the present LSI 1b (step S45), and the correction value of the LSI 1b is obtained. After the decision circuit 37 obtains the expected value comparison result of the connected LSI 9 (step S46), it compares the result with the expected value of the LSI 9 (step S47).
[0090]
If the result of the comparison in step S47 is different from the expected value of the LSI 9, the value of the delay control value storage register 29 is added by +1 (step S48), and the processing from step S45 is repeated. The correction value determination circuit 37 stores the value of the delay control value storage register 29 in the initial pass value storage register 38 (Step S49).
[0091]
Further, +1 is added to the value of the delay control value storage register 29 (step S50), test data is output from the present LSI 1b (step S51), and the correction value determination circuit 37 of the LSI 1b obtains the expected value comparison result of the connected LSI 9 After that (step S52), it is compared with the expected value of the LSI 9 (step S53).
[0092]
If the result of the comparison in step S53 is the same as the expected value of the LSI 9, the value of the delay control value storage register 29 is added by +1 (step S54), and the processing from step S51 is repeated. The correction value determination circuit 37 stores the value of −1 of the delay control value storage register 29 in the final pass value storage register 39 (Step S55).
[0093]
Then, an intermediate value between the value of the initial path value storage register 38 and the value of the final path value storage register 39 is stored in the output optimum value storage register 36 (step S56). Finally, the difference between the optimum input value and the optimum output value is adjusted by the variable delay circuits C and D (step S57).
[0094]
As described above, according to the LSI 1b of the present embodiment, the automatic timing correction circuit 13 that realizes desired AC timing including the clock recovery circuit 17 such as a PLL circuit, a DLL circuit, or an SMD circuit and the phase adjustment circuit 18 has Variable delay circuits 19 and 20 provided at two positions of an input clock delay path and a delay path in a feedback loop of the clock recovery circuit 17, variable delay circuits 21 and 22 provided at an output path of the clock recovery circuit 17, and delay control. The value storage register 29, the initial path value storage register 38, the final path value storage register 39, the input optimum value storage register 35, the output optimum value storage register 36, and the variable delay circuit control decoders 23 to 26, and can be activated by an external activation signal. Correction value determination circuit 37, expected value circuit 32, received data storage register 14, and ratio By incorporating the circuit 33 and the test data generation circuit 34, the AC timing can be arbitrarily changed between the connected LSI 9 and the LSI 9 after completion of the actual chip, similarly to the first embodiment. Since the variable delay amount can be automatically corrected, the AC timing is automatically corrected for each chip after the board is mounted, and the optimum AC timing according to the mounting environment can be realized.
[0095]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist thereof. Needless to say.
[0096]
For example, as described above, the present invention is suitable for a product having an interface in which AC timing is strict and has a high-speed operation. Further, the number of pins is limited, and a plurality of common pins are used by using a pin multiplex or the like. The present invention can be applied to a product that needs to realize a module combination (for example, a product that automatically realizes an arbitrary AC timing even when a pin function changes).
[0097]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0098]
(1) In a semiconductor device connected to a host CPU or a first semiconductor device, a relative phase between an internal clock signal reproduced by a clock reproduction circuit and a data signal input / output by an input / output circuit is adjusted. By having the phase adjustment circuit, the AC timing can be arbitrarily changed between the host CPU and the first semiconductor device even after the actual chip is completed, and in addition, the variable delay amount is automatically corrected. Therefore, it is possible to automatically correct the AC timing for each chip after the semiconductor device is mounted on the substrate, and to realize the optimum AC timing according to the mounting environment.
[0099]
(2) In a semiconductor device connected to a lower second semiconductor device, phase adjustment for adjusting a relative phase between an external clock signal reproduced by a clock recovery circuit and a data signal input / output by an input / output circuit. With the circuit, the AC timing can be arbitrarily changed between the lower-order second semiconductor device and even after the actual chip is completed, and in addition, the variable delay amount can be automatically corrected. After the semiconductor device is mounted on the substrate, the AC timing is automatically corrected for each chip, so that the optimum AC timing according to the mounting environment can be realized.
[0100]
(3) According to the semiconductor devices of (1) and (2), the phase of the internal clock signal can be adjusted according to the setup time, hold time, and delay time of the data signal. In addition, the phase of the internal clock signal can be adjusted at power-on reset, at regular time intervals, when environmental conditions fluctuate, or when a signal transmission error is detected, and can be adjusted according to the usage environment. At this time, it is possible to adjust the phase in a direction to advance or to delay it.
[0101]
(4) In a system in which a CPU, a second semiconductor device, and a third semiconductor device are mounted on a board, after these are mounted on the board, the AC timing is automatically corrected for each chip, and an optimal AC timing suitable for the mounting environment is obtained. Since timing can be realized, signal transmission optimized as a system can be realized.
[0102]
(5) In a system in which the first semiconductor device, the second semiconductor device, and the third semiconductor device are mounted on a substrate, after these are mounted on the substrate, the AC timing is automatically corrected for each chip, and is adjusted to a mounting environment. Since the optimum AC timing can be realized, signal transmission optimized as a system can be realized.
[0103]
(6) According to the above (1) to (5), signal transmission optimized for each chip can be realized, so that chip manufacturing variation can be allowed. Also, since signal transmission optimized for each mounting environment can be realized, it is possible to realize a high-speed interface with strict AC timing specifications, and to perform dynamic AC timing correction according to environmental changes. It can be realized. Further, since the AC timing can be automatically corrected for each chip, a high-precision tester is not required for mass production.
[Brief description of the drawings]
FIG. 1 is a configuration diagram illustrating a semiconductor device according to a first embodiment of the present invention;
FIG. 2 is a configuration diagram showing a PLL circuit constituting a clock recovery circuit in the semiconductor device according to the first embodiment of the present invention;
FIG. 3 is a configuration diagram showing a DLL circuit forming a clock recovery circuit in the semiconductor device according to the first embodiment of the present invention;
FIG. 4 is a configuration diagram showing a system using the semiconductor device according to the first embodiment of the present invention;
FIGS. 5A and 5B are explanatory diagrams illustrating a phase relationship of a clock signal in the semiconductor device according to the first embodiment of the present invention; FIGS.
FIG. 6 is an explanatory diagram illustrating a timing relationship between a clock signal and a data signal in the semiconductor device according to the first embodiment of the present invention;
FIG. 7 is a flowchart showing automatic timing correction in the semiconductor device according to the first embodiment of the present invention;
FIG. 8 is a flowchart showing automatic timing correction subsequent to FIG. 7 in the semiconductor device according to the first embodiment of the present invention;
FIG. 9 is a configuration diagram illustrating a semiconductor device according to a second embodiment of the present invention;
FIG. 10 is a configuration diagram showing a semiconductor device according to a third embodiment of the present invention.
FIG. 11 is a flowchart showing automatic timing correction in the semiconductor device according to the third embodiment of the present invention.
FIG. 12 is a flowchart showing automatic timing correction subsequent to FIG. 11 in the semiconductor device according to the third embodiment of the present invention;
[Explanation of symbols]
1,1a, 1b LSI
2,2a CPU
3 CPU system clock generation circuit
4 USB
5 ATAPI
6 memory
7 Crystal oscillator
8 LSI (or memory, etc.)
9 LSI
11 Internal logic circuit
12, 12a-12c I / O circuit
13, 13a to 13c Automatic timing correction circuit
14 Receive data storage register
15 Input circuit
16 output circuit
17 Clock recovery circuit
18 Phase adjustment circuit
19-22 Variable delay circuit
23-26 decoder
27/28 frequency divider
29 Delay control value storage register
30a-30c clock generation circuit
31 Internal logic clock generation circuit
32 expected value circuit
33 Comparison circuit
34 Test Data Generation Circuit
35 Input optimum value storage register
36 Output optimum value storage register
37 Correction value determination circuit
38 Initial path value storage register
39 Last pass value storage register
41 Start signal generation circuit
42 System clock generation circuit
43 Test Data Generation Circuit
44 Internal logic circuit
45 I / O circuit
46 Expected value comparison circuit
51 Basic configuration is a phase comparator
52 Low-pass filter
53 VCO
54 1 / N frequency divider
61 Variable delay circuit
62 phase comparator
63 bias controller
64 replica delay circuit

Claims (19)

A clock recovery circuit for recovering an internal clock signal by receiving an external clock signal;
An input / output circuit for inputting / outputting a data signal to / from the outside,
A semiconductor device comprising: a phase adjustment circuit that adjusts a relative phase between an internal clock signal reproduced by the clock reproduction circuit and a data signal input / output by the input / output circuit. The semiconductor device according to claim 1,
A CPU having means for generating the clock signal and means for inputting and outputting the data signal is connected to the outside,
The clock recovery circuit receives the clock signal output from the CPU as an input to recover an internal clock signal,
The input / output circuit inputs and outputs a data signal to and from the CPU.
The semiconductor device, wherein the phase adjustment circuit adjusts a relative phase between an internal clock signal reproduced by the clock reproduction circuit and a data signal input / output by the input / output circuit. The semiconductor device according to claim 1,
A first semiconductor device having a circuit for generating the clock signal and a circuit for inputting and outputting the data signal is connected to the outside,
The clock regeneration circuit regenerates an internal clock signal with a clock signal output from the first semiconductor device as an input,
The input / output circuit inputs / outputs a data signal to / from the first semiconductor device;
The semiconductor device, wherein the phase adjustment circuit adjusts a relative phase between an internal clock signal reproduced by the clock reproduction circuit and a data signal input / output by the input / output circuit. The semiconductor device according to claim 1,
Wherein the phase adjustment circuit adjusts a phase of an internal clock signal reproduced by the clock reproduction circuit in accordance with a setup time, a hold time, and a delay time of a data signal input / output by the input / output circuit. apparatus. The semiconductor device according to claim 1,
The semiconductor device, wherein the clock recovery circuit is a PLL, a DLL, or an SMD that variably adjusts a delay time of the internal clock signal. The semiconductor device according to claim 1,
A semiconductor device, wherein the adjustment of the phase of the internal clock signal is controlled by a BIOS or an OS, and an initial value before the adjustment is stored in the BIOS. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the adjustment of the phase of the internal clock signal is performed at a power-on reset, at regular time intervals, when environmental conditions change, or when a signal transmission error is detected. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the adjustment of the phase of the internal clock signal is performed according to a use environment. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the adjustment of the phase of the internal clock signal enables both advance and delay. A clock recovery circuit that recovers a clock signal to the outside and outputs it as an external clock signal;
An input / output circuit for inputting / outputting a data signal to / from the outside,
A semiconductor device comprising: a phase adjustment circuit that adjusts a relative phase between an external clock signal reproduced by the clock reproduction circuit and a data signal input / output by the input / output circuit. The semiconductor device according to claim 10,
A second semiconductor device having a circuit for inputting and outputting the data signal in synchronization with the external clock signal is connected to the outside,
The clock recovery circuit reproduces a clock signal for the second semiconductor device and outputs the clock signal as an external clock signal;
The input / output circuit inputs / outputs a data signal to / from the second semiconductor device;
The semiconductor device according to claim 1, wherein the phase adjustment circuit adjusts a relative phase between an external clock signal reproduced by the clock reproduction circuit and a data signal input / output by the input / output circuit. The semiconductor device according to claim 10,
Wherein the phase adjustment circuit adjusts a phase of an external clock signal reproduced by the clock reproduction circuit in accordance with a setup time, a hold time, and a delay time of a data signal input / output by the input / output circuit. apparatus. The semiconductor device according to claim 10,
The semiconductor device, wherein the clock recovery circuit is a PLL, a DLL, or an SMD that variably adjusts a delay time of the external clock signal. The semiconductor device according to claim 10,
A semiconductor device, wherein the adjustment of the phase of the external clock signal is controlled by a BIOS or an OS, and an initial value before the adjustment is stored in the BIOS. The semiconductor device according to claim 10,
The semiconductor device according to claim 1, wherein the adjustment of the phase of the external clock signal is performed at power-on reset, at regular time intervals, when environmental conditions change, or when a signal transmission error is detected. The semiconductor device according to claim 10,
The semiconductor device according to claim 1, wherein the adjustment of the phase of the external clock signal is performed in accordance with a use environment. The semiconductor device according to claim 10,
The semiconductor device according to claim 1, wherein the adjustment of the phase of the external clock signal enables both advance and delay. A CPU having means for generating a clock signal, and means for inputting and outputting a data signal;
A second semiconductor device having a circuit for inputting and outputting a data signal in synchronization with an external clock signal;
A clock recovery circuit that is connected between the CPU and the second semiconductor device and that receives a clock signal from the CPU as an input to reproduce an internal clock signal and outputs the clock signal as an external clock signal; A relative input / output circuit for inputting / outputting a data signal to / from the semiconductor device, an internal clock signal reproduced by the clock reproducing circuit, and a data signal input / output to / from the CPU by the input / output circuit; A phase adjustment circuit that adjusts a phase and adjusts a relative phase between an external clock signal reproduced by the clock reproduction circuit and a data signal input / output to / from the second semiconductor device by the input / output circuit. And a third semiconductor device having the following. A first semiconductor device having a circuit for generating a clock signal and a circuit for inputting and outputting a data signal;
A second semiconductor device having a circuit for inputting and outputting a data signal in synchronization with an external clock signal;
A clock recovery circuit connected between the first semiconductor device and the second semiconductor device, for recovering an internal clock signal with a clock signal from the first semiconductor device as an input, and outputting the clock signal as an external clock signal; An input / output circuit for inputting / outputting a data signal to / from the first semiconductor device and the second semiconductor device; an internal clock signal reproduced by the clock reproduction circuit; The input / output circuit adjusts the relative phase between the data signal input / output by the input / output circuit, and inputs / outputs the external clock signal reproduced by the clock reproduction circuit from / to the second semiconductor device by the input / output circuit. A third semiconductor device having a phase adjustment circuit for adjusting a relative phase with the data signal.

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