JP2004071943A - Electronic equipment - Google Patents

Abstract

An electron formed by covering the surface of a metal wiring layer formed on one surface of a substrate with an insulating protective film and bonding the metal wiring layer and a solder bump through an opening formed in the protective film. In the apparatus, deterioration of the protective film that occurs after solder reflow is suppressed.
A metal wiring layer 20 includes an Au layer 22 made of Au capable of forming an alloy by diffusing Sn components constituting solder bumps 40 by heat during solder reflow. By making the film thickness of the Au layer 22 0.01 μm or more and 0.1 μm or less, Sn constituting the solder bumps diffuses into the Au layer 22 located under the protective film 30 during the solder reflow, and Au− The growth of the Sn alloy layer 52 is suppressed.
[Selection] Figure 2

Description

[0001]
BACKGROUND OF THE INVENTION
In the present invention, the surface of a metal wiring layer formed on one surface of a substrate is covered with an insulating protective film, and the metal wiring layer and the solder bump are joined through an opening formed in the protective film. The electronic device can be applied to a wafer level CSP (chip size package) and various wiring boards.
[0002]
[Prior art]
A general electronic apparatus of this type will be described with reference to FIG. A metal wiring layer 20 is formed on one surface of the substrate 10. In FIG. 8, the metal wiring layer 20 is formed by laminating a first layer 21 made of Ni or the like and a second layer 22 made of Au or the like from the substrate 10 side.
[0003]
An insulating protective film 30 that covers the surface of the metal wiring layer 20 is formed on the metal wiring layer 20, and an opening 31 for exposing the lower metal wiring layer 20 is formed in the protective film 30. Is formed. Solder bumps 40 are formed on the metal wiring layer 20 exposed from the openings 31, and the solder bumps 40 and the metal wiring layer 20 are electrically and mechanically joined.
[0004]
[Problems to be solved by the invention]
By the way, the electronic device as described above is applied to a wafer level CSP and various wiring boards. In the case of a wafer level CSP, a solder ball is mounted in a wafer state, and the solder ball is reflowed before dicing cut of the wafer and formed on the solder bump 40.
[0005]
Also, when used for various wiring boards, the solder bumps 40 are used for joining with a mating member such as a mother board, and therefore, solder reflow is performed when mounting on the mating member. In any case, in this type of electronic device, the solder bump 40 is reflowed at least once.
[0006]
The present inventors have studied this type of electronic device in which such solder reflow is performed. As a result, after the solder reflow, the protective film 30 is deteriorated in strength, peeled, cracked, etc., and deteriorated. Was found to occur. Such deterioration of the protective film 30 may lead to deterioration of reliability such as deterioration of moisture resistance and leakage.
[0007]
In view of the above problems, the present invention covers the surface of a metal wiring layer formed on one surface of a substrate with an insulating protective film, and connects the metal wiring layer and the solder bumps through openings formed in the protective film. It is an object of the present invention to suppress deterioration of a protective film that occurs after solder reflow in a bonded electronic device.
[0008]
[Means for Solving the Problems]
As a result of intensive studies to achieve the above object, it has been found that the above-described deterioration of the protective film is caused by the combination of the metal wiring layer and the solder bump.
[0009]
The combination is a case where the metal component that constitutes the solder bump and the metal component that constitutes the metal diffusion layer that is the base diffuse to each other due to heat during solder reflow to form an alloy layer at the interface between the two. is there. Specifically, Sn etc. are mentioned as a metal component of a solder bump, Au, Cu, etc. are mentioned as a metal component of a metal diffusion layer.
[0010]
The cross-sectional configuration shown in FIG. 2 shows a state in which this alloy layer is formed, and this configuration has been experimentally confirmed as a result of examinations such as observation by an electron microscope by the present inventors. . Here, although not limited, the metal wiring layer 20 has an example in which the first layer 21 is Ni, the second layer 22 is Au, and the solder bump 40 is Sn-rich.
[0011]
The configuration shown in FIG. 2 is a state after the solder reflow is performed. The Sn of the solder bump 40 is diffused into the second layer 22 of the metal wiring layer 20 to form an Au—Sn alloy layer 52 made of an Au—Sn alloy, and the Sn of the solder bump 40 and the metal wiring layer 20 are formed. A Ni—Sn alloy layer 51 is similarly formed for Ni in the first layer 21.
[0012]
According to the study by the present inventors, in particular, the Au—Sn alloy layer 52 is easy to grow because the mutual metal components are more easily diffused, and penetrates under the protective film 30 from the root portion of the solder bump 40. It is in shape.
[0013]
Therefore, as a result of the protective film 30 being pushed up by the Au—Sn alloy layer 52, the protective film 30 is reduced in strength, peeled off, cracked, etc., and the protective film 30 is deteriorated. The present invention has been made with a focus on controlling the alloy layer formed by such solder bumps and metal wiring layers.
[0014]
That is, in the first aspect of the invention, the substrate (10), the metal wiring layer (20) formed on one surface of the substrate, and the insulating layer formed on the metal wiring layer and covering the surface of the metal wiring layer. The protective film (30), the opening (31) formed in the protective film for exposing the metal wiring layer, and the metal wiring layer exposed from the opening of the protective film are joined to the metal wiring layer. In an electronic device comprising a solder bump (40), the metal wiring layer is made of a material containing a metal component capable of forming an alloy by diffusing the metal component constituting the solder bump by heat during solder reflow. The layer is characterized in that it has a diffusion suppressing structure that suppresses diffusion of metal components constituting the solder bumps to the metal wiring layer located under the protective film during solder reflow.
[0015]
According to this, since the metal component constituting the solder bump can be prevented from diffusing into the metal wiring layer located under the protective film at the time of solder reflow, the alloy layer of the solder bump and the metal wiring layer is formed on the protective film. It can suppress the growth and intrusion. Therefore, according to the present invention, it is possible to suppress deterioration of the protective film that occurs after solder reflow.
[0016]
Here, as in the invention described in claim 2, the metal wiring layer (20) uses Au as a metal component capable of forming an alloy with the metal component constituting the solder bump (40), and is made of this Au. In the case of having an Au layer (22), a structure in which the film thickness of the Au layer is 0.01 μm or more and 0.1 μm or less can be adopted as the diffusion suppressing structure.
[0017]
In the metal wiring layer according to the second aspect, as in the invention according to the third aspect, a laminated structure having the Ni layer (21) as a base of the Au layer (22) can be adopted.
[0018]
In the invention according to claim 4, the substrate (10), the metal wiring layer (20) formed on one surface of the substrate, and the insulating protective film formed on the metal wiring layer and covering the surface of the metal wiring layer (30), an opening (31) for exposing the metal wiring layer formed in the protective film, and a solder bump formed on the metal wiring layer exposed from the opening of the protective film and bonded to the metal wiring layer (40), the inner peripheral end face (31a) in the opening of the protective film has a taper smaller than the complementary angle (θ2) of the solder contact angle (θ1) in the shape of the solder bump after solder reflow The taper shape has an angle (θ3).
[0019]
The present invention has been made by paying attention to the property that a solder tends to become spherical due to surface tension during reflow. In the present invention, the inner peripheral end face in the opening of the protective film is a tapered surface, and the taper angle is smaller than the complementary angle of the solder contact angle in the solder bump shape after solder reflow.
[0020]
Therefore, at the time of reflow, the solder bump and the inner peripheral end face of the opening of the protective film can hardly contact (that is, hardly interfere), and the solder does not easily flow to the outer peripheral, that is, the metal wiring layer under the protective film.
[0021]
Thereby, it can suppress that the metal component which comprises a solder bump at the time of solder reflow diffuses into the metal wiring layer located under a protective film. Therefore, similarly to the first aspect of the invention, it is possible to suppress deterioration of the protective film that occurs after solder reflow.
[0022]
The metal wiring layer according to claim 4 can also employ a laminated structure having an Au layer (22) as the outermost layer and a Ni layer (21) as the underlayer as in the invention according to claim 5. .
[0023]
In the invention described in claim 6, the substrate (10), the metal wiring layer (20) formed on one surface of the substrate, and the insulating protective film formed on the metal wiring layer and covering the surface of the metal wiring layer (30), an opening (31) for exposing the metal wiring layer formed in the protective film, and a solder bump formed on the metal wiring layer exposed from the opening of the protective film and bonded to the metal wiring layer (40), the metal wiring layer is formed by laminating a plurality of layers made of different materials, and the outermost layer (22) of the metal wiring layer has solder bumps formed by heat during solder reflow. The metal component is made of a material containing a metal that can be diffused to form an alloy, and a portion of the metal wiring layer that is located around the opening of the protective film is provided with a portion that does not have an outermost layer. And
[0024]
According to this, an alloy layer is formed by the solder bump and the outermost layer of the metal wiring layer in the opening portion of the protective film, and the alloy layer tries to grow around the opening portion, that is, under the protective film. The growth of the alloy layer stops at the nonexistent portion. Therefore, no further alloy layer grows under the protective film.
[0025]
Therefore, also by this invention, degradation of the protective film which generate | occur | produces after solder reflow can be suppressed.
[0026]
In the invention according to claim 7, the substrate (10), the metal wiring layer (20) formed on one surface of the substrate, and the insulating protective film formed on the metal wiring layer and covering the surface of the metal wiring layer (30), an opening (31) for exposing the metal wiring layer formed in the protective film, and a solder bump formed on the metal wiring layer exposed from the opening of the protective film and bonded to the metal wiring layer In the electronic device comprising (40), the metal component constituting the solder bump can be diffused by heat during solder reflow to form an alloy only in a portion of the metal wiring layer exposed from the opening of the protective film. A layer made of a material containing a metal is provided as the outermost layer (22) of the metal wiring layer.
[0027]
When it is necessary to provide a layer made of a material containing a metal that can form an alloy with the metal component of the solder bump as the base of the solder bump in the metal wiring layer, only the joint with the solder bump as in the present invention. Should be provided. Thereby, since an alloy layer is not formed under the protective film, it is possible to suppress deterioration of the protective film that occurs after solder reflow.
[0028]
Here, in the sixth and seventh aspects as well, the metal wiring layer (20) can have the Au layer (22) as the outermost layer and the Ni layer (21) as the underlying layer.
[0029]
Moreover, as a metal component which comprises the solder bump (40) in each said means, what has Sn as a main component is employable.
[0030]
In addition, the code | symbol in the bracket | parenthesis of each said means is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.
[0031]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments shown in the drawings will be described below. In the following embodiments, the same reference numerals are assigned to the same parts in the drawings for the sake of simplicity.
[0032]
(First embodiment)
In the first embodiment of the present invention, the electronic device of the present invention will be described as applied to a wafer level CSP. First, the basic configuration of the CSP will be described with reference to FIG.
[0033]
The substrate 10 is a semiconductor substrate on which a semiconductor element such as a transistor is formed. On one surface side of the substrate 10, wirings 11 and lead electrodes (pads) 12 made of aluminum or the like that are electrically connected to the semiconductor element are formed.
[0034]
On one surface of the substrate 10, a passivation film 13 made of a silicon nitride film that covers and protects the semiconductor element and the wiring 11 is formed. Here, the passivation film 13 is opened on the extraction electrode 12. The semiconductor element, the wiring 11, the extraction electrode 12, and the passivation film 13 can be formed by a known semiconductor process.
[0035]
An interlayer film 14 made of an insulating film material is formed on the passivation film 13. The interlayer film 14 plays a role of stress relaxation between the upper metal wiring layer 20 and the substrate 10 and can be formed by applying and curing polyimide or the like, for example. Further, the interlayer film 14 is removed by etching or the like above the extraction electrode 12 to form an opening 15.
[0036]
A metal wiring layer 20 is formed in a predetermined pattern on the interlayer film 14 via the seed layer 16. The metal wiring layer 20 is necessary for electrically connecting the solder bumps 40 and the extraction electrodes 12 that are aligned and arranged at a predetermined pitch in the CSP.
[0037]
The seed layer 16 is a base for the metal wiring layer 20, and a film of Cu, Cr, or the like can be formed by a sputtering method or the like. The seed layer 16 has a pattern that matches the metal wiring layer 20.
[0038]
The metal wiring layer 20 is electrically connected to the extraction electrode 12 through the opening 15 of the interlayer film 14 and has a predetermined wiring pattern from the opening 15 of the interlayer film 14 to the portion where the solder bump 40 is disposed. It extends. In the present embodiment, the metal wiring layer 20 is formed by laminating a first layer 21 made of Ni and a second layer 22 made of Au or the like from the substrate 10 side.
[0039]
Such a metal wiring layer 20 can be formed by forming a plating film by an electrolytic plating method or the like in a state where a wiring pattern is partitioned using a resist on the substrate 10 on which the seed layer is formed. In the metal wiring layer 20 of this example, the first layer 21 serving as the base is the Ni layer 21 plated with Ni, and the second layer 22 as the outermost layer is the Au layer 22 plated with Au.
[0040]
Note that the first layer 21 serving as the base of the Au layer 22 may be a layer made of a material other than Ni. Further, a Ni layer and a layer made of a material different from Ni (for example, Cu) may be further provided under the Ni layer.
[0041]
An insulating protective film 30 that covers the surface of the metal wiring layer 20 is formed on the metal wiring layer 20, and an opening 31 for exposing the lower metal wiring layer 20 to the protective film 30. Is formed. The protective film 30 is formed by depositing a resin or ceramic insulating film such as polyimide or silicon nitride film by spin coating or sputtering.
[0042]
A solder bump 40 is formed on the metal wiring layer 20 exposed from the opening 31 of the protective film 30, and the solder bump 40 and the metal wiring layer 20 are electrically and mechanically joined. In this example, the solder bump 40 is made of Sn-rich solder containing Sn as a main component.
[0043]
A CSP as such an electronic device is manufactured as follows, for example, as a wafer level CSP. A semiconductor element, wiring 11, a passivation film 13 and the like are formed on the semiconductor substrate 10 in a wafer state using a semiconductor process.
[0044]
Next, an interlayer film 14 made of polyimide or the like is formed on the passivation film 13, and then the interlayer film 14 is removed by etching or the like above the extraction electrode 12 on the substrate 10 to form an opening 15. .
[0045]
Next, a seed layer 16 formed by sputtering such as Cr or Cu is formed on the entire surface of the interlayer film 14 including the extraction electrode 12 exposed from the opening 15. Next, a resist having an opening at a portion where the metal wiring layer 20 is to be formed in the surface of the seed layer 16 is patterned. That is, a resist is formed in a part where the metal wiring layer 20 is not formed, and the part is covered with the resist.
[0046]
Next, a Ni layer 21 and an Au layer 22 are formed on the surface of the seed layer 16 exposed from the resist opening by electrolytic plating. Thereafter, the resist is removed using a stripping solution or the like, and the seed layer 16 in the portion where the resist is removed is etched and removed using an etching solution such as an acid. Thus, the seed layer 16 and the metal wiring layer 20 having a desired pattern are formed.
[0047]
Thereafter, a protective film 30 made of polyimide or the like is formed on the substrate 10. The protective film 30 is formed in a state where the connection portion with the solder bump 40 in the metal wiring layer 20 is opened. Then, solder bumps 40 are formed using a technique such as electrolytic plating, printing, or solder balls, and the metal wiring layer 20 and the solder bumps 40 are electrically and mechanically connected through the openings 31 of the protective film 30. . Thus, the CSP structure shown in FIG. 1 is completed.
[0048]
Thereafter, the solder bumps 40 are reflowed to obtain a stable state, and then dicing cut is performed. Then, the CSP formed as a chip is mounted on a mating member such as a mother board, and is mounted on the mating member by reflowing the solder bumps 40.
[0049]
Here, in the present embodiment, the joint between the metal wiring layer 20 and the solder bump 40 has the following characteristics. This feature will be described with reference to FIG. 2 described in the section “Solution means”.
[0050]
FIG. 2 is an enlarged view of the alloy layer portion in the vicinity of the solder bump bonding portion in FIG. 2 and FIGS. 5 to 7 to be described later, the wiring 11, the passivation film 13, the interlayer film 14, and the seed layer 16 located between the substrate 10 and the metal wiring layer 20 are omitted.
[0051]
The metal wiring layer 20 is made of a material containing a metal component that can form an alloy by diffusing the metal component constituting the solder bump 40 by heat during solder reflow. That is, in this example, the metal component constituting the solder bump 40 is Sn, and the metal components of the metal wiring layer 20 are Au and Ni.
[0052]
Here, alloy layers 51 and 52 of the metal wiring layer 20 and the solder bumps 40 are formed by diffusion due to heat during solder reflow. In this example, the Sn of the solder bump 40 is diffused in the Au layer 22 of the metal wiring layer 20 and the Au—Sn alloy layer 52 made of an Au—Sn alloy, and the Sn of the solder bump 40 is the metal wiring layer 20. And a Ni—Sn alloy layer 51 made of a Ni—Sn alloy formed by diffusing in the Ni layer 21.
[0053]
These alloy layers 51 and 52 extend from the root portion of the solder bump 40 along the surface direction of one surface of the substrate 10. In particular, the Au—Sn alloy layer 52 is easy to grow because the mutual metal components are more easily diffused, and has a shape that penetrates under the protective film 30 from the root portion of the solder bump 40.
[0054]
Here, as shown in FIG. 2, the penetration length L1 of the Ni—Sn alloy layer and the Au—Sn alloy layer 52 protect the length of the portion where the Ni—Sn alloy layer 51 penetrates under the protective film 30. The length of the portion penetrating under the film 30 is defined as an intrusion length L2 of the Au—Sn alloy layer.
[0055]
In this example, the penetration length L2 of the Au—Sn alloy layer is larger than the penetration length L1 of the Ni—Sn alloy layer, and the penetration length L2 of the Au—Sn alloy layer is about 10 μm. Moreover, when peeling has occurred in the protective film 30, the peeling length of the protective film is indicated by a length L3 in FIG. In this example, even if peeling of the protective film 30 occurs, the peeling length L3 of the protective film is about 2 to 3 μm.
[0056]
Thus, by suppressing the penetration length L2 of the Au—Sn alloy layer to the above range, the peeling length L3 of the protective film can be suppressed to a level that does not cause a problem, and deterioration of the protective film 30 can be suppressed. ing.
[0057]
As a configuration of the metal wiring layer 20 that suppresses the deterioration of the protective film 30, a configuration in which the film thickness of the Au layer 22 is 0.01 μm or more and 0.1 μm or less is employed in this example.
[0058]
As a result, Sn constituting the solder bump 40 is prevented from diffusing into the Au layer 22 located under the protective film 30 during solder reflow, and the Au—Sn alloy layer 52 grows under the protective film 30. Therefore, it is possible to suppress deterioration of the protective film 30 that occurs after solder reflow.
[0059]
The grounds for adopting the film thickness range of the Au layer 22 will be described. In the configuration of this example, the relationship between the film thickness of the Au layer 22 and the penetration lengths L1 and L2 of the alloy layer and the relationship between the film thickness of the Au layer 22 and the peeling length L3 of the protective film were examined. Each dimension can be confirmed by a cross-sectional SEM or the like.
[0060]
FIG. 3 is a diagram showing the relationship between the thickness of the Au layer 22 and the penetration lengths L1 and L2 of the alloy layer, and FIG. 4 shows the relationship between the thickness of the Au layer 22 and the peeling length L3 of the protective film. FIG. These relationships are the results after one solder reflow.
[0061]
As can be seen from FIG. 3, when the film thickness of the Au layer 22 is 0.1 μm or less, the increments of the penetration lengths L1 and L2 of each alloy layer are very small. The penetration length L2 of the Sn alloy layer increases rapidly. That is, the penetration length L2 of the Au—Sn alloy layer is a main factor causing deterioration such as peeling of the protective film 30. The effect of suppressing the penetration length L2 of the Au—Sn alloy layer is as follows. A clear difference was observed with a film thickness of 0.1 μm as a boundary.
[0062]
As for the protective film peeling length L3 that is actually an indicator of the degree of deterioration of the protective film 30, as can be seen from FIG. 4, when the film thickness of the Au layer 22 is 0.1 μm or less, the peeling length is concerned. While L3 can be suppressed as small as possible, when the thickness exceeds 0.1 μm, the degree of increase in peel length L3 suddenly increases.
[0063]
If the Au layer 22 is made thin in this way, the diffusion and growth of the Au—Sn alloy layer 52 can be suppressed because the amount of Au necessary to form the alloy can be reduced in the first place.
[0064]
Further, by making the Au layer 22 thinner, the Au layer 22 may become an island-like discontinuous film at the early stage of solder wetting. Then, the growth of the alloy layer of the Au layer 22 and the Sn of the solder bump 40 stops at the discontinuous portion, and it is considered that this also suppresses the growth of the alloy layer.
[0065]
On the other hand, if the Au layer 22 is too thin, the wettability of the solder bumps 40 is deteriorated. In this example, if the Au layer 22 is too thin, the underlying Ni layer 21 is oxidized and solder wettability cannot be ensured. From such a viewpoint, the lower limit of the film thickness of the Au layer 22 needs to be 0.01 μm or more.
[0066]
Based on the above examination results, as the configuration of the metal wiring layer 20 that suppresses the deterioration of the protective film 30, in this example, the configuration in which the film thickness of the Au layer 22 is 0.01 μm or more and 0.1 μm or less is adopted. Yes.
[0067]
(Second Embodiment)
FIG. 5 is a schematic cross-sectional view of an electronic device according to the second embodiment of the present invention. In this embodiment, the inner peripheral end surface 31a in the opening 31 of the protective film 30 has a tapered shape having a taper angle θ3 smaller than the complementary angle θ2 of the solder contact angle θ1 in the shape of the solder bump 40 after solder reflow. It is characterized by being.
[0068]
This embodiment is made by paying attention to the property that the solder tends to become spherical due to surface tension during reflow. The shape of the solder bump 40 after solder reflow substantially inherits the shape of the solder bump 40 that has become liquid during solder reflow.
[0069]
Therefore, the inner peripheral end surface 31a in the opening 31 of the protective film 30 is a tapered surface, and the taper angle θ3 is made smaller than the complementary angle θ2 of the solder contact angle θ1 in the shape of the solder bump 40 during solder reflow. At the time of reflow, the solder bump 40 and the inner peripheral end surface 31a of the opening 31 of the protective film 30 can hardly contact (that is, hardly interfere).
[0070]
Therefore, at the time of reflow, the solder hardly flows to the outer periphery, that is, the metal wiring layer 20 under the protective film 30. Thereby, it can suppress that the metal component which comprises the solder bump 40 at the time of solder reflow diffuses into the metal wiring layer 20 located under the protective film 30. FIG.
[0071]
Therefore, also in the present embodiment, as in the first embodiment, it is possible to suppress deterioration of the protective film 30 that occurs after solder reflow.
[0072]
Here, processing the inner peripheral end face 31a in the opening 31 of the protective film 30 into a tapered surface can be realized by a generally known technique such as isotropic etching. The taper angle θ3 can be about 20 °, for example.
[0073]
(Third embodiment)
FIG. 6 is a schematic cross-sectional view of an electronic device according to a third embodiment of the present invention. In the present embodiment, the metal wiring layer 20 is formed by laminating a plurality of layers of different materials, and the outermost layer 22 of the metal wiring layer 20 has a metal component constituting the solder bump 40 by heat during solder reflow. In the case where the metal wiring layer 20 is made of a material containing a metal that can be diffused to form an alloy, a portion where the outermost layer 22 does not exist is provided in a portion located around the opening 31 of the protective film 30 in the metal wiring layer 20. It is a feature.
[0074]
In the example shown in FIG. 6, the metal wiring layer 20 is the same as the example shown in the first embodiment, and the base layer is the Ni layer 21 and the outermost layer is the Au layer 22. At this time, as shown in FIG. 6, a portion of the metal wiring layer 20 including only the Ni layer 21 without the Au layer 22 is formed around the opening 31 of the protective film 30.
[0075]
This configuration can be realized, for example, by forming an etching hole 32 in the protective film 30 and etching away the Au layer 22 with an iodine-based etching solution through the hole 32.
[0076]
Although the above-described alloy layer is omitted in FIG. 6, according to the present embodiment, an Au—Sn alloy layer formed by the solder bump 40 and the Au layer 22 of the metal wiring layer 20 is formed in the opening 31 of the protective film 30. Arise. This alloy layer tries to grow around the opening 31, that is, under the protective film 30, but the growth of the alloy layer stops at a portion where the Au layer 22 does not exist, so that the alloy layer is further under the protective film 30. It will never grow.
[0077]
Therefore, also by this embodiment, deterioration of the protective film 30 generated after solder reflow can be suppressed. 6 may be filled with a protective material in a later step.
[0078]
(Fourth embodiment)
FIG. 7 is a schematic cross-sectional view of an electronic device according to a fourth embodiment of the present invention. In the present embodiment, a metal capable of forming an alloy by diffusing the metal components constituting the solder bumps 40 by heat during solder reflow only in a portion of the metal wiring layer 20 exposed from the opening 31 of the protective film 30. A layer made of the containing material is provided as the outermost layer 22 of the metal wiring layer 20.
[0079]
In the example shown in FIG. 7, the metal wiring layer 20 is the same as the example shown in the first embodiment, and the base layer is the Ni layer 21 and the outermost layer is the Au layer 22. At this time, as shown in FIG. 7, the metal wiring layer 20 in which the Au layer 22 is formed only on the surface of the Ni layer 21 that substantially matches the opening 31 of the protective film 30. This configuration can be realized by partially forming the Au layer 22 by performing selective electrolytic plating.
[0080]
When it is necessary to provide the layer 22 made of a material containing a metal capable of forming an alloy with the metal component of the solder bump 40 as the base of the solder bump 40 in the metal wiring layer 20 as in the present embodiment, the metal layer 20 may be provided only at the joint with the solder bump 40. Thereby, since an alloy layer is not formed under the protective film 30, deterioration of the protective film 30 generated after solder reflow can be suppressed.
[0081]
(Other embodiments)
As the metal wiring layer 20, in addition to the Au layer as the outermost layer described above and the Au / Ni laminated structure having the Ni layer as the underlying layer, a three-layer laminated structure of Au / Ni / Cu, a laminated structure of Au / Cu Etc. may be adopted.
[0082]
In each of the above embodiments, a semiconductor substrate used in a semiconductor device such as a wafer level CSP is used as the substrate 10. However, as other substrates, a resin wiring substrate such as a printed circuit board, a ceramic wiring substrate, or a metal substrate is used. A board | substrate etc. can be employ | adopted.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view of an electronic device according to a first embodiment of the present invention.
2 is an enlarged schematic cross-sectional view of an alloy layer portion of a solder bump joint portion of the electronic device in FIG.
FIG. 3 is a diagram showing the relationship between the thickness of the Au layer and the penetration length of the alloy layer in the first embodiment.
FIG. 4 is a diagram showing the relationship between the thickness of the Au layer and the peeling length of the protective film in the first embodiment.
FIG. 5 is a schematic cross-sectional view of an electronic device according to a second embodiment of the present invention.
FIG. 6 is a schematic cross-sectional view of an electronic device according to a third embodiment of the present invention.
FIG. 7 is a schematic cross-sectional view of an electronic device according to a fourth embodiment of the present invention.
FIG. 8 is a schematic cross-sectional view of a conventional general electronic device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Board | substrate, 20 ... Metal wiring layer, 21 ... Ni layer as a 1st layer,
22 ... Au layer as second layer, 30 ... protective film, 31 ... opening,
31a ... inner peripheral end face of opening of protective film, 40 ... solder bump,
θ1 is a solder contact angle, θ2 is a complementary angle of the solder contact angle, θ3 is a taper angle.

Claims (9)

A substrate (10);
A metal wiring layer (20) formed on one surface of the substrate;
An insulating protective film (30) formed on the metal wiring layer and covering the surface of the metal wiring layer;
An opening (31) formed in the protective film for exposing the metal wiring layer, and a solder formed on the metal wiring layer exposed from the opening of the protective film and bonded to the metal wiring layer An electronic device comprising a bump (40),
The metal wiring layer is made of a material containing a metal component capable of forming an alloy by diffusing the metal component constituting the solder bump by heat during solder reflow,
The metal wiring layer has a diffusion suppressing structure that suppresses diffusion of a metal component constituting the solder bump to the metal wiring layer located under the protective film during the solder reflow. An electronic device. The metal wiring layer (20) uses Au as a metal component capable of forming an alloy with the metal component constituting the solder bump (40), and has an Au layer (22) made of Au.
2. The electronic device according to claim 1, wherein the diffusion suppressing structure has a configuration in which a film thickness of the Au layer is 0.01 μm or more and 0.1 μm or less. The electronic device according to claim 2, wherein the metal wiring layer (20) has a laminated structure in which the Au layer (22) is an outermost layer and a Ni layer (21) is provided on the underlayer. A substrate (10);
A metal wiring layer (20) formed on one surface of the substrate;
An insulating protective film (30) formed on the metal wiring layer and covering the surface of the metal wiring layer;
An opening (31) formed on the protective film for exposing the metal wiring layer, and a solder formed on the metal wiring layer exposed from the opening of the protective film and bonded to the metal wiring layer An electronic device comprising a bump (40),
An inner peripheral end surface (31a) in the opening of the protective film has a taper shape (θ3) having a smaller taper angle (θ3) than the complementary angle (θ2) of the solder contact angle (θ1) in the shape of the solder bump after solder reflow. An electronic device characterized in that The electronic device according to claim 4, wherein the metal wiring layer (20) has a laminated structure having an Au layer (22) as an outermost layer and a Ni layer (21) as an underlayer. A substrate (10);
A metal wiring layer (20) formed on one surface of the substrate;
An insulating protective film (30) formed on the metal wiring layer and covering the surface of the metal wiring layer;
An opening (31) formed in the protective film for exposing the metal wiring layer, and a solder formed on the metal wiring layer exposed from the opening of the protective film and bonded to the metal wiring layer An electronic device comprising a bump (40),
The metal wiring layer is formed by laminating a plurality of layers having different materials,
The outermost layer (22) of the metal wiring layer is made of a material containing a metal capable of forming an alloy by diffusing metal components constituting the solder bumps by heat during solder reflow,
An electronic device comprising: a portion of the metal wiring layer located around the opening of the protective film so that the outermost layer does not exist. A substrate (10);
A metal wiring layer (20) formed on one surface of the substrate;
An insulating protective film (30) formed on the metal wiring layer and covering the surface of the metal wiring layer;
An opening (31) formed on the protective film for exposing the metal wiring layer, and a solder formed on the metal wiring layer exposed from the opening of the protective film and bonded to the metal wiring layer An electronic device comprising a bump (40),
A layer made of a material containing a metal that can form an alloy by diffusing metal components constituting the solder bumps by heat at the time of solder reflowing only in a portion of the metal wiring layer exposed from the opening of the protective film. Is provided as an outermost layer (22) of the metal wiring layer. The electronic device according to claim 6 or 7, wherein the metal wiring layer (20) has an Au layer (22) as the outermost layer and a Ni layer (21) as an underlayer. 9. The electronic device according to claim 1, wherein the metal component constituting the solder bump (40) is mainly composed of Sn.

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