JP2004061290A

JP2004061290A - Evaluation equipment for semiconductor devices

Info

Publication number: JP2004061290A
Application number: JP2002219889A
Authority: JP
Inventors: Akihiko Yamamoto; 山本　昭彦; Masayuki Kubota; 久保田　雅之
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 2002-07-29
Filing date: 2002-07-29
Publication date: 2004-02-26

Abstract

【課題】高周波コンタクタを使用することなく被評価半導体装置と評価基板との十分な電極間接触を得ることができる半導体装置用評価装置を提供する。
【解決手段】基体を構成するマウント部１、このマウント部１に装着され被評価半導体装置７の電極７１、７２が直接圧接される接触部３Ｃ、３Ｄを有する電極部３Ａ、３Ｂと、上記接触部３Ｃ、３Ｄの周縁部に設けられ表裏を貫通する貫通部３０とを有する半導体装置用評価基板２及び上記マウント部１に設けられ先端部が上記貫通部３０を経て上記電極部とほぼ同一面に位置し、上記被評価半導体装置７のグランド電極７３と当接し得るようにされたグランド端子部３３を備えた構成とする。
【選択図】　　　　図１An evaluation device for a semiconductor device is provided that can obtain sufficient inter-electrode contact between a semiconductor device to be evaluated and an evaluation substrate without using a high-frequency contactor.
A contact part (3A, 3B) having contact parts (3C, 3D) mounted on the mount part (1) and directly contacting electrodes (71, 72) of a semiconductor device under evaluation (7) mounted on the mount part (1), The semiconductor device evaluation substrate 2 having a through-hole 30 penetrating the front and back provided on the peripheral edge of the portions 3C and 3D, and the tip portion provided on the mount 1 is substantially flush with the electrode through the through-hole 30. And a ground terminal portion 33 that can be brought into contact with the ground electrode 73 of the semiconductor device 7 to be evaluated.
[Selection diagram] Fig. 1

Description

【０００１】
【発明の属する技術分野】
この発明は、半導体装置用評価装置に関するものである。
【０００２】
【従来の技術】
図７は、従来の半導体装置用評価装置の構成を概略的に示す分解斜視図である。この図において、１は半導体装置用評価装置の基体を構成するマウント部で、導電性及び放熱性に優れたアルミ、銅等で構成されている。２は上記マウント部１の上面に装着される半導体装置用評価基板（以下、評価基板という）で、熱硬化性のテフロン（登録商標）、ガラスエポキシ等により構成されている。３Ａ、３Ｂは評価基板２の表面に設けられたライン状パターンからなる電極部で、３Ａと３Ｂは評価基板２のほぼ中央部で所定の間隔を介して配置されると共に、Ｌ、Ｃ等の図示しないマッチング回路を含み、評価基板２の端縁部において図示しない評価装置に接続されている。４は評価基板２をマウント部に固定するためのねじ孔、５は後述する高周波コンタクタの固定ねじを貫通させるための貫通孔、６は被評価半導体装置７を装着して評価基板２の電極部３Ａ、３Ｂに接続するための高周波コンタクタで、一方の面から他方の面に貫通してそれぞれの面で電気接触部を形成する所定数の金属ピン８を有し、一方の面の接触部は被評価半導体装置７の電極（図示せず）と接触し得るように配置され、他方の面の接触部は高周波コンタクタ６を評価基板２の所定位置に固定した時、電極部３Ａ、３Ｂに接触し得るように配置されている。
【０００３】
９は高周波コンタクタ６を固定するためのねじ孔で、このねじ孔９に挿入された固定ねじ（図示せず）は評価基板２の貫通孔５を貫通してマウント部１にねじ止めされ、高周波コンタクタ６を評価基板２の所定位置に固定する。
被評価半導体装置７の評価は、被評価半導体装置７の電極が高周波コンタクタ６の一方の面の各接触部と接触するように高周波コンタクタ６上に装着し、図示しない押さえ機構によって被評価半導体装置７の全電極が高周波コンタクタ６の接触部及びグランドと十分に接触するまで押圧した状態で実施される。
【０００４】
【発明が解決しようとする課題】
従来の半導体装置用評価装置は以上のように構成され、被評価半導体装置７を評価基板２に接続する手段として高周波コンタクタ６を使用していたため、高周波コンタクタ６自体のインダクタンスとコンダクタンスを含めた測定が行なわれ、被評価半導体装置７の特性値を正確に測定、評価できないことから、高周波コンタクタ６自体のインダクタンスとコンダクタンスを除外するための測定値補正を行なう必要があるという問題点があった。
また、高周波コンタクタ６を使用するため、被評価半導体装置７の装着部近傍にチップ部品を装着することがむつかしくなる結果、評価できない半導体装置が発生していた。また、高周波コンタクタ６は多数の被評価半導体装置７との精密な接触構造を必要とするため、製作に長期間を要し、高価であるため評価コストが高くなるという問題点もあった。
【０００５】
この発明は、上記のような問題点を解消するためになされたもので、高周波コンタクタを使用することなく被評価半導体装置と評価基板との十分な電極間接触を得ることができる半導体装置用評価装置を提供することを目的とする。
【０００６】
【課題を解決するための手段】
この発明に係る半導体装置用評価装置は、基体を構成するマウント部と、表裏を貫通する貫通部が形成され、この貫通部の周縁に設けられ被評価半導体装置の電極が圧接される接触部を具備する電極部を有し、上記マウント部に装着される半導体装置用評価基板と、上記貫通部を経て上記電極部とほぼ同一面に位置して、上記被評価半導体装置のグランド電極と当接し得るようにマウント部に設けられたグランド端子部とを備えたものである。
【０００７】
この発明に係る半導体装置用評価装置は、また、上記接触部下面の半導体装置用評価基板と上記マウント部との間に押圧手段を設け、上記接触部とその下面の半導体装置用評価基板が上記被評価半導体装置側へ反り上がるようにしたものである。
【０００８】
この発明に係る半導体装置用評価装置は、また、上記接触部下面の半導体装置用評価基板の上記マウント部側を削り込み、上記貫通部と削り込まれた上記半導体装置用評価基板とで形成される個所に上記押圧手段を装着するようにしたものである。
【０００９】
この発明に係る半導体装置用評価装置は、また、上記グランド端子部が、上記マウント部に装着される装着部と、この装着部より幅狭に形成され上記装着部から上記電極面に向けて延在する延在部とを有するものである。
【００１０】
この発明に係る半導体装置用評価装置は、また、上記マウント部に凹所を形成し、この凹所に上記グランド端子部の装着部を嵌入したものである。
【００１１】
この発明に係る半導体装置用評価装置は、また、上記半導体装置用評価基板の上記接触部下面の削り込まれたマウント部側の面と上記電極部を有する面との間にグランド層を形成したものである。
【００１２】
【発明の実施の形態】
実施の形態１．
以下、この発明の実施の形態１を図にもとづいて説明する。図１は、実施の形態１の構成を概略的に示す分解斜視図、図２は、図１のＩＩ―ＩＩ線からみた断面図、図３は、評価基板を裏面からみた斜視図である。
これらの図において、１は半導体装置用評価装置の基体を構成するマウント部で、導電性及び放熱性に優れたアルミ、銅等で構成されている。２は上記マウント部１の上面に装着される評価基板で、熱硬化性のテフロン（登録商標）、ガラスエポキシ等により構成されている。３Ａ、３Ｂは評価基板２の表面に設けられたライン状パターンからなる電極部で、３Ａと３Ｂは評価基板２のほぼ中央部で所定の間隔を介して配置されると共に、Ｌ、Ｃ等の図示しないマッチング回路を含み、評価基板２の端縁部において図示しない評価装置に接続されている。
３０は評価基板２のほぼ中央部において、電極部３Ａ、３Ｂの内端の接触部３Ｃ、３Ｄの下面に位置する部分を除く形で接触部３Ｃ、３Ｄの周縁部に設けられ、評価基板２の表裏を貫通する貫通部である。なお、評価基板２は電極部３Ａ、３Ｂを含めて０．６ｍｍ程度の厚さとされているが、接触部３Ｃ、３Ｄの下面に位置する部分の評価基板２は図２及び図３に示すように、裏面、即ちマウント部側が一部削り込まれ、電極部内端の接触部３Ｃ、３Ｄを含めた厚さが０．２ｍｍ程度となるように薄くされている。
【００１３】
３１は評価基板２とマウント部１との間で貫通部３０に嵌合された押圧手段で、絶縁ゴム材によって構成され、図２に示すように、電極部の接触部３Ｃ、３Ｄ及びその下面に位置する評価基板２に対して図において上方向の押圧力を作用させ、電極部の接触部３Ｃ、３Ｄ及びその下面に位置する評価基板２の先端部を図２に示すように、０．１ｍｍ程度、反り上がらせるものである。また、押圧手段である絶縁ゴム材３１には、その中央部に貫通孔３２が形成されている。
３３はマウント部１に設けられたグランド端子部で、金属または導電性ゴムによって構成され、被評価半導体装置７のグランド接続及び放熱を目的として図２に示すように絶縁ゴム材３１の貫通孔３２を貫通して先端面、即ち図において上端面が電極部３Ａ、３Ｂとほぼ同一面となるようにされている。
【００１４】
このような構成において、半導体装置の評価を行なう場合には、図１及び図２に示すように、被評価半導体装置７の電極７１、７２及びグランド端子７３を評価基板２の貫通部３０の直上から電極部３Ａ、３Ｂの接触部３Ｃ、３Ｄに向けて図示しない押さえ機構によって押し下げる。この時、電極部３Ａ、３Ｂの接触部３Ｃ、３Ｄは図２に示すように反り上がっているため、先ず、被評価半導体装置７の電極７１と接触部３Ｄ及び電極７２と接触部３Ｃが接触する。
押さえ機構によって被評価半導体装置７を更に押し下げると接触部３Ｃ、３Ｄは接圧を保って押し下げられ、被評価半導体装置７のグランド端子７３がグランド端子部である金属または導電性ゴム３３に接触する。この状態を保持して被評価半導体装置７の評価のための測定が行なわれる。
測定が完了すると、図示しない押さえ機構を上昇させ、被評価半導体装置７を取り替えて上述の動作を繰り返す。
【００１５】
この実施の形態によれば、被評価半導体装置７は評価基板２の電極部の接触部３Ｃ、３Ｄ及びグランド端子部３３に直接接触し、従来、使用していた高価な高周波コンタクタを必要としないため、安価に構成することができると共に、高周波コンタクタ自体の特性の補正を行なう必要もない。
また、高周波コンタクタを使用していた場合に搭載することができなかったチップ部品が高周波コンタクタがないために搭載可能となり、評価可能な半導体装置を拡大することができる。
更に、電極部の接触部３Ｃ、３Ｄの下面に位置する評価基板２を削り込んで接触部３Ｃ、３Ｄ部分の厚さを薄くしているため、押圧手段である絶縁ゴム材３１の押圧力を受けて電極部の接触部３Ｃ、３Ｄ及びその下面に位置する評価基板２が反り上がり易くなり、被評価半導体装置７の電極との接圧が確保される結果、被評価半導体装置７と電極部の接触部３Ｃ、３Ｄとの直接接触で的確な評価が可能となるものである。更にまた、接触部３Ｃ、３Ｄの厚さを薄くすることにより、評価基板２とマウント部１との間に絶縁ゴム材３１の嵌合スペースを確保することができるため、評価装置をコンパクトに構成することができる。
【００１６】
実施の形態２．
次に、この発明の実施の形態２を図にもとづいて説明する。図４は、実施の形態２の構成を概略的に示す分解斜視図、図５は、マウント部へのグランド端子部と押圧手段である絶縁ゴム材との装着状態を示す断面図である。
これらの図において、図１〜図３と同一または相当部分にはそれぞれ同一符号を付して説明を省略する。図１〜図３と異なる点は、グランド端子部を、マウント部に装着される装着部と、この装着部より幅狭に形成され上記装着部から電極面に向けて延在する延在部とから構成するようにした点である。即ち、図４において、３４はグランド端子部で、マウント部１に装着される装着部３４Ａと、この装着部３４Ａより幅狭に形成され、装着部３４Ａから電極部３Ａまたは３Ｂの面に向けて延在する延在部３４Ｂとから構成されている。
【００１７】
また、３５はマウント部１に形成された凹所で、図５に示されるように、グランド端子３４の装着部３４Ａが嵌入され、押圧手段である絶縁ゴム材３１がマウント部１の上面に接する形で延在部３４Ｂに嵌装されることになる。なお、グランド端子部が図１及び図２に３３で示されるように、単純な平板状である場合には、その下端部を凹所３５に嵌入してもよい。
このような構成とすることにより、グランド端子部３３あるいは３４の位置ずれと外れを防止することができる。また、グランド端子部が図４及び図５に３４で示す構成とされる場合においても、マウント部１に装着される評価基板２は図１に示す構成のものが使用されることは云うまでもない。
【００１８】
実施の形態３．
次に、この発明の実施の形態３を図にもとづいて説明する。図６は、実施の形態３における評価基板２の構成を概略的に示す断面図である。評価基板以外の構成は実施の形態１あるいは２と同様であるため説明を省略する。
この実施の形態は、図６に示すように、電極部３Ａ、３Ｂの接触部３Ｃ、３Ｄの下面に位置する評価基板２が削り込まれたマウント部側の面と電極部３Ａ、３Ｂを有する面との中間部にグランド層４０を設けることを特徴とする。
このような構成とすることにより、評価基板の高周波特性への削り込みによる影響を受けにくくすることができる。
【００１９】
【発明の効果】
この発明に係る半導体装置用評価装置は、基体を構成するマウント部と、表裏を貫通する貫通部が形成され、この貫通部の周縁に設けられ被評価半導体装置の電極が圧接される接触部を具備する電極部を有し、上記マウント部に装着される半導体装置用評価基板と、上記貫通部を経て上記電極部とほぼ同一面に位置して、上記被評価半導体装置のグランド電極と当接し得るようにマウント部に設けられたグランド端子部とを備えたものであるため、高価な高周波コンタクタを用いることなく半導体装置の評価を行なうことができ、評価基板上の被評価半導体装置近傍へのチップ部品の搭載も可能となり、評価可能な半導体装置を拡大することができる。
また、被評価半導体装置が評価基板に直接接触するので、半導体装置の特性を正確に測定、評価することができ、高周波コンタクタの測定値補正も行なう必要がない。
【００２０】
この発明に係る半導体装置用評価装置は、また、上記接触部下面の半導体装置用評価基板と上記マウント部との間に押圧手段を設け、上記接触部とその下面の半導体装置用評価基板が上記被評価半導体装置側へ反り上がるようにしたため、被評価半導体装置の電極と評価基板の電極部とを十分な接圧で接触させることができ、高周波コンタクタを用いなくても半導体装置の特性を正確に測定、評価することが可能となる。
【００２１】
この発明に係る半導体装置用評価装置は、また、上記接触部下面の半導体装置用評価基板の上記マウント部側を削り込み、上記貫通部と削り込まれた上記半導体装置用評価基板とで形成される個所に上記押圧手段を装着するようにしたため、評価基板の電極部の被評価半導体装置電極との接触部が薄くなり、被評価半導体装置側へ反り上がり易くなるため、半導体装置の電極との接触時に更に十分な接圧を確保することができる。
【００２２】
この発明に係る半導体装置用評価装置は、また、上記グランド端子部が、上記マウント部に装着される装着部と、この装着部より幅狭に形成され上記装着部から上記電極面に向けて延在する延在部とを有するものであるため、延在部を絶縁ゴム材の貫通孔に挿入することにより、グランド端子部の外れを防止することができる。
【００２３】
この発明に係る半導体装置用評価装置は、また、上記マウント部に凹所を形成し、この凹所に上記グランド端子部の装着部を嵌入したため、グランド端子部の位置ずれを防止することができ、被評価半導体装置のグランド接続を確実に行なうことができる。
【００２４】
この発明に係る半導体装置用評価装置は、また、上記半導体装置用評価基板の上記接触部下面の削り込まれたマウント部側の面と上記電極部を有する面との間にグランド層を形成したため、評価基板の高周波特性への削り込みによる影響を受けにくくすることができる。
【図面の簡単な説明】
【図１】この発明の実施の形態１の構成を概略的に示す分解斜視図である。
【図２】図１のＩＩ−ＩＩ線からみた断面図である。
【図３】実施の形態１における評価基板を裏面からみた斜視図である。
【図４】この発明の実施の形態２の構成を概略的に示す分解斜視図である。
【図５】実施の形態２におけるマウント部へのグランド端子部と絶縁ゴム材との装着状態を示す断面図である。
【図６】この発明の実施の形態３における評価基板の構成を概略的に示す断面図である。
【図７】従来の半導体装置用評価装置の構成を概略的に示す分解斜視図である。
【符号の説明】
１　マウント部、　　２　評価基板、　　３Ａ、３Ｂ　電極部、　　３Ｃ、３Ｄ　接触部、　　７　被評価半導体装置、　　３０　貫通部、　　３１　押圧手段、　　３３　グランド端子部。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an evaluation device for a semiconductor device.
[0002]
[Prior art]
FIG. 7 is an exploded perspective view schematically showing a configuration of a conventional semiconductor device evaluation device. In this figure, reference numeral 1 denotes a mount portion constituting a base of the semiconductor device evaluation device, which is made of aluminum, copper, or the like having excellent conductivity and heat dissipation. Reference numeral 2 denotes an evaluation board for a semiconductor device (hereinafter referred to as an evaluation board) mounted on the upper surface of the mount section 1 and is made of thermosetting Teflon (registered trademark), glass epoxy, or the like. Reference numerals 3A and 3B denote electrode portions formed of a linear pattern provided on the surface of the evaluation substrate 2, and 3A and 3B are disposed at a predetermined center in a substantially central portion of the evaluation substrate 2 and have L, C, etc. It includes a matching circuit (not shown), and is connected to an evaluation device (not shown) at the edge of the evaluation board 2. Reference numeral 4 denotes a screw hole for fixing the evaluation substrate 2 to the mounting portion, 5 denotes a through hole for passing a fixing screw of a high-frequency contactor described later, 6 denotes an electrode portion of the evaluation substrate 2 on which the semiconductor device 7 to be evaluated is mounted. A high frequency contactor for connecting to 3A, 3B, having a predetermined number of metal pins 8 penetrating from one surface to the other surface to form electrical contacts on each surface, and the contact portion on one surface is The contact portion on the other surface is arranged so as to be able to come into contact with an electrode (not shown) of the semiconductor device 7 to be evaluated. When the high-frequency contactor 6 is fixed at a predetermined position on the evaluation substrate 2, it comes into contact with the electrode portions 3 A, 3 B It is arranged to be able to.
[0003]
Reference numeral 9 denotes a screw hole for fixing the high-frequency contactor 6. A fixing screw (not shown) inserted into the screw hole 9 passes through the through-hole 5 of the evaluation board 2, and is screwed to the mount unit 1. The contactor 6 is fixed at a predetermined position on the evaluation board 2.
The evaluation of the semiconductor device under evaluation 7 is performed by mounting the semiconductor device under evaluation 7 on the high frequency contactor 6 such that the electrodes of the semiconductor device 7 under evaluation come into contact with the respective contact portions on one surface of the high frequency contactor 6, and by a pressing mechanism (not shown). 7 is carried out in a state in which it is pressed until all the electrodes 7 sufficiently contact the contact portion of the high-frequency contactor 6 and the ground.
[0004]
[Problems to be solved by the invention]
The conventional evaluation apparatus for semiconductor devices is configured as described above, and uses the high-frequency contactor 6 as a means for connecting the semiconductor device 7 to be evaluated to the evaluation board 2, so that the measurement including the inductance and conductance of the high-frequency contactor 6 itself is performed. Is performed, and the characteristic value of the semiconductor device 7 to be evaluated cannot be accurately measured and evaluated. Therefore, there is a problem that it is necessary to perform a measurement value correction for excluding the inductance and the conductance of the high-frequency contactor 6 itself.
Further, since the high-frequency contactor 6 is used, it is difficult to mount a chip component in the vicinity of the mounting portion of the semiconductor device 7 to be evaluated. As a result, some semiconductor devices cannot be evaluated. In addition, since the high-frequency contactor 6 requires a precise contact structure with a large number of semiconductor devices 7 to be evaluated, there is also a problem that a long period of time is required for the manufacture, and the cost is high and the evaluation cost is high.
[0005]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has been made in consideration of a semiconductor device evaluation capable of obtaining sufficient interelectrode contact between a semiconductor device to be evaluated and an evaluation substrate without using a high-frequency contactor. It is intended to provide a device.
[0006]
[Means for Solving the Problems]
An evaluation device for a semiconductor device according to the present invention is characterized in that a mount portion constituting a base and a penetrating portion penetrating the front and back are formed, and a contact portion provided on a peripheral edge of the penetrating portion and pressed against an electrode of the semiconductor device to be evaluated. An evaluation board for a semiconductor device to be mounted on the mount portion, and being located on substantially the same plane as the electrode portion via the through portion, and in contact with a ground electrode of the semiconductor device to be evaluated. And a ground terminal portion provided on the mount portion so as to obtain the same.
[0007]
The evaluation device for a semiconductor device according to the present invention may further include a pressing unit provided between the semiconductor device evaluation substrate on the lower surface of the contact portion and the mount portion. The semiconductor device is warped toward the semiconductor device to be evaluated.
[0008]
The evaluation device for a semiconductor device according to the present invention is also formed by shaving the mount portion side of the evaluation board for a semiconductor device on the lower surface of the contact portion, and including the penetrating portion and the evaluation board for the semiconductor device that is cut. The above-mentioned pressing means is mounted at a predetermined position.
[0009]
In the semiconductor device evaluation device according to the present invention, the ground terminal portion may be formed to be narrower than the mounting portion to be mounted on the mount portion and extend from the mounting portion toward the electrode surface. And an existing extending portion.
[0010]
In the semiconductor device evaluation device according to the present invention, a recess is formed in the mount portion, and a mounting portion of the ground terminal portion is fitted into the recess.
[0011]
In the semiconductor device evaluation device according to the present invention, a ground layer is formed between the surface of the mounting portion side of the contact portion lower surface of the semiconductor device evaluation substrate and the surface having the electrode portion. Things.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. 1 is an exploded perspective view schematically showing the configuration of the first embodiment, FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1, and FIG. 3 is a perspective view of the evaluation board seen from the back.
In these figures, reference numeral 1 denotes a mount portion which constitutes a base of a semiconductor device evaluation device, and is made of aluminum, copper, or the like having excellent conductivity and heat dissipation. Reference numeral 2 denotes an evaluation board mounted on the upper surface of the mount section 1 and is made of thermosetting Teflon (registered trademark), glass epoxy, or the like. Reference numerals 3A and 3B denote electrode portions formed of a linear pattern provided on the surface of the evaluation substrate 2, and 3A and 3B are disposed at a predetermined center in a substantially central portion of the evaluation substrate 2 and have L, C, etc. It includes a matching circuit (not shown), and is connected to an evaluation device (not shown) at the edge of the evaluation board 2.
Reference numeral 30 denotes a substantially central portion of the evaluation board 2 provided on the peripheral edge of the contact portions 3C and 3D except for the portion located on the lower surface of the contact portions 3C and 3D at the inner ends of the electrode portions 3A and 3B. Is a penetrating part penetrating through the front and back of the. The evaluation substrate 2 has a thickness of about 0.6 mm including the electrode portions 3A and 3B. However, the evaluation substrate 2 located on the lower surface of the contact portions 3C and 3D is as shown in FIGS. Then, the back surface, that is, the mount portion side is partially cut away, and the thickness including the contact portions 3C and 3D at the inner end of the electrode portion is reduced to about 0.2 mm.
[0013]
Reference numeral 31 denotes a pressing unit fitted between the evaluation board 2 and the mount unit 1 to the penetrating unit 30 and is made of an insulating rubber material. As shown in FIG. 2, the contact units 3C and 3D of the electrode unit and the lower surface thereof In the figure, an upward pressing force is applied to the evaluation substrate 2 located at the position shown in FIG. Warp up about 1 mm. Further, a through hole 32 is formed in the center of the insulating rubber material 31 serving as the pressing means.
Reference numeral 33 denotes a ground terminal portion provided on the mount portion 1 and is made of metal or conductive rubber. For the purpose of ground connection and heat radiation of the semiconductor device 7 to be evaluated, as shown in FIG. , The top end surface, that is, the upper end surface in the figure, is substantially flush with the electrode portions 3A and 3B.
[0014]
In such a configuration, when the evaluation of the semiconductor device is performed, as shown in FIGS. 1 and 2, the electrodes 71 and 72 and the ground terminal 73 of the semiconductor device 7 to be evaluated are placed directly above the penetrating portion 30 of the evaluation substrate 2. From below to the contact portions 3C and 3D of the electrode portions 3A and 3B by a pressing mechanism (not shown). At this time, since the contact portions 3C and 3D of the electrode portions 3A and 3B are warped as shown in FIG. 2, first, the electrode 71 and the contact portion 3D of the semiconductor device 7 to be evaluated and the electrode 72 and the contact portion 3C contact each other. I do.
When the semiconductor device 7 to be evaluated is further pushed down by the pressing mechanism, the contact portions 3C and 3D are pushed down while maintaining the contact pressure, and the ground terminal 73 of the semiconductor device 7 to be evaluated comes into contact with the metal or the conductive rubber 33 as the ground terminal portion. . While maintaining this state, measurement for evaluation of the semiconductor device 7 to be evaluated is performed.
When the measurement is completed, the pressing mechanism (not shown) is raised, the semiconductor device 7 to be evaluated is replaced, and the above operation is repeated.
[0015]
According to this embodiment, the semiconductor device 7 to be evaluated directly contacts the contact portions 3C and 3D of the electrode portions of the evaluation substrate 2 and the ground terminal portion 33, and does not require an expensive high-frequency contactor conventionally used. Therefore, the configuration can be made at a low cost, and there is no need to correct the characteristics of the high-frequency contactor itself.
In addition, chip components that could not be mounted when a high-frequency contactor was used can be mounted because there is no high-frequency contactor, and the number of semiconductor devices that can be evaluated can be increased.
Furthermore, since the thickness of the contact portions 3C and 3D is reduced by shaving the evaluation substrate 2 located on the lower surface of the contact portions 3C and 3D of the electrode portion, the pressing force of the insulating rubber material 31 as the pressing means is reduced. The contact portions 3C and 3D of the receiving electrode portion and the evaluation substrate 2 located on the lower surface thereof are easily warped, and the contact pressure between the electrode of the semiconductor device 7 to be evaluated and the electrode portion is secured. It is possible to perform an accurate evaluation by direct contact with the contact portions 3C and 3D. Furthermore, by reducing the thickness of the contact portions 3C and 3D, a space for fitting the insulating rubber material 31 between the evaluation substrate 2 and the mount portion 1 can be ensured. can do.
[0016]
Embodiment 2 FIG.
Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 4 is an exploded perspective view schematically showing a configuration of the second embodiment, and FIG. 5 is a cross-sectional view showing a mounting state of a ground terminal portion on a mount portion and an insulating rubber material as a pressing means.
In these drawings, the same or corresponding parts as those in FIGS. 1 to 3 are denoted by the same reference numerals, and description thereof is omitted. The difference from FIGS. 1 to 3 is that the ground terminal portion has a mounting portion mounted on the mounting portion, and an extending portion formed narrower than the mounting portion and extending from the mounting portion toward the electrode surface. This is the point that is configured. That is, in FIG. 4, reference numeral 34 denotes a ground terminal portion, which is a mounting portion 34A mounted on the mount portion 1 and formed narrower than the mounting portion 34A, and extends from the mounting portion 34A toward the surface of the electrode portion 3A or 3B. And an extending portion 34B that extends.
[0017]
Reference numeral 35 denotes a recess formed in the mount portion 1, as shown in FIG. 5, into which the mounting portion 34 A of the ground terminal 34 is fitted, and the insulating rubber material 31 serving as a pressing means contacts the upper surface of the mount portion 1. It will be fitted in the extension part 34B in the form. When the ground terminal portion has a simple flat plate shape as indicated by 33 in FIGS. 1 and 2, the lower end portion may be fitted into the recess 35.
With such a configuration, it is possible to prevent the ground terminal portion 33 or 34 from being displaced and coming off. In addition, even when the ground terminal portion has the configuration indicated by 34 in FIGS. 4 and 5, it goes without saying that the evaluation board 2 mounted on the mount portion 1 has the configuration illustrated in FIG. Absent.
[0018]
Embodiment 3 FIG.
Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a sectional view schematically showing a configuration of the evaluation board 2 according to the third embodiment. The configuration other than the evaluation board is the same as that of the first or second embodiment, and thus the description is omitted.
In this embodiment, as shown in FIG. 6, there is provided a surface on the mount portion side where the evaluation substrate 2 located on the lower surface of the contact portions 3C and 3D of the electrode portions 3A and 3B is cut off, and the electrode portions 3A and 3B. The ground layer 40 is provided at an intermediate portion between the plane and the surface.
With such a configuration, it is possible to make the evaluation board less susceptible to being cut into the high-frequency characteristics.
[0019]
【The invention's effect】
An evaluation device for a semiconductor device according to the present invention is characterized in that a mount portion constituting a base and a penetrating portion penetrating the front and back are formed, and a contact portion provided on a peripheral edge of the penetrating portion and pressed against an electrode of the semiconductor device to be evaluated. An evaluation board for a semiconductor device to be mounted on the mount portion, and being located on substantially the same plane as the electrode portion via the through portion, and in contact with a ground electrode of the semiconductor device to be evaluated. And a ground terminal provided on the mount portion so that the semiconductor device can be evaluated without using an expensive high-frequency contactor. Chip components can be mounted, and the number of semiconductor devices that can be evaluated can be increased.
In addition, since the semiconductor device to be evaluated is in direct contact with the evaluation substrate, the characteristics of the semiconductor device can be accurately measured and evaluated, and there is no need to correct the measured value of the high-frequency contactor.
[0020]
The evaluation device for a semiconductor device according to the present invention may further include a pressing unit provided between the semiconductor device evaluation substrate on the lower surface of the contact portion and the mount portion. Since the semiconductor device to be evaluated is warped upward, the electrodes of the semiconductor device to be evaluated and the electrode portions of the evaluation substrate can be brought into contact with a sufficient contact pressure, and the characteristics of the semiconductor device can be accurately measured without using a high-frequency contactor. Measurement and evaluation.
[0021]
The evaluation device for a semiconductor device according to the present invention is also formed by shaving the mount portion side of the evaluation board for a semiconductor device on the lower surface of the contact portion, and including the penetrating portion and the evaluation board for the semiconductor device that is cut. The contact portion of the electrode portion of the evaluation board with the electrode of the semiconductor device to be evaluated is thinned, and the electrode portion of the evaluation device is easily warped toward the semiconductor device to be evaluated. A more sufficient contact pressure can be secured at the time of contact.
[0022]
In the semiconductor device evaluation device according to the present invention, the ground terminal portion may be formed to be narrower than the mounting portion to be mounted on the mount portion and extend from the mounting portion toward the electrode surface. Since the extension portion is present, the detachment of the ground terminal portion can be prevented by inserting the extension portion into the through hole of the insulating rubber material.
[0023]
In the semiconductor device evaluation device according to the present invention, a recess is formed in the mount portion, and the mounting portion of the ground terminal portion is fitted into the recess, so that the displacement of the ground terminal portion can be prevented. In addition, the ground connection of the semiconductor device to be evaluated can be reliably performed.
[0024]
In the semiconductor device evaluation device according to the present invention, the ground layer is formed between the surface on the mount portion side where the lower surface of the contact portion is cut off and the surface having the electrode portion of the semiconductor device evaluation substrate. In addition, it is possible to make the evaluation board less susceptible to shaving on the high frequency characteristics.
[Brief description of the drawings]
FIG. 1 is an exploded perspective view schematically showing a configuration of a first embodiment of the present invention.
FIG. 2 is a sectional view taken along line II-II in FIG.
FIG. 3 is a perspective view of the evaluation board according to the first embodiment as viewed from the back surface.
FIG. 4 is an exploded perspective view schematically showing a configuration of a second embodiment of the present invention.
FIG. 5 is a cross-sectional view showing a mounting state of a ground terminal portion and an insulating rubber material on a mount portion according to a second embodiment.
FIG. 6 is a cross sectional view schematically showing a configuration of an evaluation board according to Embodiment 3 of the present invention.
FIG. 7 is an exploded perspective view schematically showing a configuration of a conventional semiconductor device evaluation device.
[Explanation of symbols]
Reference Signs List 1 mount part, 2 evaluation board, 3A, 3B electrode part, 3C, 3D contact part, 7 semiconductor device under evaluation, 30 penetrating part, 31 pressing means, 33 ground terminal part.

Claims

A mount portion forming a base, and a through portion penetrating the front and back sides are formed, and the mount portion includes an electrode portion provided on a peripheral edge of the through portion and having a contact portion to which an electrode of the semiconductor device to be evaluated is pressed. A semiconductor device evaluation board to be mounted on the semiconductor device, and a ground terminal provided on the mount portion so as to be located on substantially the same plane as the electrode portion via the through portion and to be in contact with a ground electrode of the semiconductor device to be evaluated. Evaluation device for a semiconductor device, comprising:

Pressing means is provided between the semiconductor device evaluation substrate on the lower surface of the contact portion and the mount portion, and the contact portion and the semiconductor device evaluation substrate on the lower surface thereof are warped toward the semiconductor device to be evaluated. The evaluation device for a semiconductor device according to claim 1, wherein:

The mounting portion side of the semiconductor device evaluation substrate on the lower surface of the contact portion is cut off, and the pressing means is attached to a location formed by the penetrating portion and the cut-out semiconductor device evaluation substrate. The evaluation device for a semiconductor device according to claim 2, wherein:

The ground terminal portion has a mounting portion mounted on the mount portion, and an extending portion formed narrower than the mounting portion and extending from the mounting portion toward the electrode surface. The evaluation device for a semiconductor device according to claim 1.

5. The evaluation device for a semiconductor device according to claim 4, wherein a recess is formed in the mount portion, and a mounting portion of the ground terminal portion is fitted into the recess.

2. The semiconductor device according to claim 1, wherein the evaluation board for a semiconductor device has a ground layer formed between a surface of the mount portion side on which the lower surface of the contact portion is cut and a surface having the electrode portion. Evaluation device.